1 # RFC ls009 SVP64 REMAP instructions
5 * <https://libre-soc.org/openpower/sv/>
6 * <https://libre-soc.org/openpower/sv/rfc/ls009/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1042>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
20 **Books and Section affected**:
23 Book I, new Zero-Overhead-Loop Chapter.
24 Appendix E Power ISA sorted by opcode
25 Appendix F Power ISA sorted by version
26 Appendix G Power ISA sorted by Compliancy Subset
27 Appendix H Power ISA sorted by mnemonic
33 svremap - Re-Mapping of Register Element Offsets
34 svindex - General-purpose setting of SHAPEs to be re-mapped
35 svshape - Hardware-level setting of SHAPEs for element re-mapping
36 svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
39 **Submitter**: Luke Leighton (Libre-SOC)
41 **Requester**: Libre-SOC
43 **Impact on processor**:
46 Addition of four new "Zero-Overhead-Loop-Control" DSP-style Vector-style
47 Management Instructions which provide advanced features such as Matrix
48 FFT DCT Hardware-Assist Schedules and general-purpose Index reordering.
51 **Impact on software**:
54 Requires support for new instructions in assembler, debuggers,
61 Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
62 Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
63 Digital Signal Processing (DSP)
68 These REMAP Management instructions provide state-of-the-art advanced capabilities
69 to dramatically decrease instruction count and power reduction whilst retaining
70 unprecedented general-purpose capability and a standard Sequential Execution Model.
72 **Notes and Observations**:
78 Add the following entries to:
80 * the Appendices of Book I
81 * Instructions of Book I as a new Section
82 * TODO-Form of Book I Section 1.6.1.6 and 1.6.2
88 # REMAP <a name="remap" />
90 REMAP is an advanced form of Vector "Structure Packing" that
91 provides hardware-level support for commonly-used *nested* loop patterns.
92 For more general reordering an Indexed REMAP mode is available.
94 REMAP allows the usual vector loop `0..VL-1` to be "reshaped" (re-mapped)
95 from a linear form to a 2D or 3D transposed form, or "offset" to permit
96 arbitrary access to elements (when elwidth overrides are used),
97 independently on each Vector src or dest
98 register. Aside from Indexed REMAP this is entirely Hardware-accelerated
99 reordering and consequently not costly in terms of register access. It
100 will however place a burden on Multi-Issue systems but no more than if
101 the equivalent Scalar instructions were explicitly
102 loop-unrolled without SVP64, and some advanced implementations may even find
103 the Deterministic nature of the Scheduling to be easier on resources.
105 The initial primary motivation of REMAP was for Matrix Multiplication, reordering
106 of sequential data in-place: in-place DCT and FFT were easily justified given the
107 high usage in Computer Science.
108 Four SPRs are provided which may be applied to any GPR, FPR or CR Field
109 so that for example a single FMAC may be
110 used in a single hardware-controlled 100% Deterministic loop to
111 perform 5x3 times 3x4 Matrix multiplication,
112 generating 60 FMACs *without needing explicit assembler unrolling*.
113 Additional uses include regular "Structure Packing"
114 such as RGB pixel data extraction and reforming.
116 REMAP, like all of SV, is abstracted out, meaning that unlike traditional
117 Vector ISAs which would typically only have a limited set of instructions
118 that can be structure-packed (LD/ST typically), REMAP may be applied to
119 literally any instruction: CRs, Arithmetic, Logical, LD/ST, anything.
121 Note that REMAP does not *directly* apply to sub-vector elements: that
122 is what swizzle is for. Swizzle *can* however be applied to the same
123 instruction as REMAP. As explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack EXTRA Mode bits
124 can extend down into Sub-vector elements to perform vec2/vec3/vec4
125 sequential reordering, but even here, REMAP is not extended down to
126 the actual sub-vector elements themselves.
128 In its general form, REMAP is quite expensive to set up, and on some
129 implementations may introduce
130 latency, so should realistically be used only where it is worthwhile.
131 Commonly-used patterns such as Matrix Multiply, DCT and FFT have
132 helper instruction options which make REMAP easier to use.
134 There are four types of REMAP:
136 * **Matrix**, also known as 2D and 3D reshaping, can perform in-place
137 Matrix transpose and rotate. The Shapes are set up for an "Outer Product"
139 * **FFT/DCT**, with full triple-loop in-place support: limited to
141 * **Indexing**, for any general-purpose reordering, also includes
142 limited 2D reshaping.
143 * **Parallel Reduction**, for scheduling a sequence of operations
144 in a Deterministic fashion, in a way that may be parallelised,
145 to reduce a Vector down to a single value.
147 Best implemented on top of a Multi-Issue Out-of-Order Micro-architecture,
148 REMAP Schedules are 100% Deterministic **including Indexing** and are
149 designed to be incorporated in between the Decode and Issue phases,
150 directly into Register Hazard Management.
152 Parallel Reduction is unusual in that it requires a full vector array
153 of results (not a scalar) and uses the rest of the result Vector for
154 the purposes of storing intermediary calculations. As these intermediary
155 results are Deterministically computed they may be useful.
156 Additionally, because the intermediate results are always written out
157 it is possible to service Precise Interrupts without affecting latency
158 (a common limitation of Vector ISAs implementing explicit
159 Parallel Reduction instructions).
163 * normal vector element read/write of operands would be sequential
165 * this is not appropriate for (e.g.) Matrix multiply which requires
166 accessing elements in alternative sequences (0 3 6 1 4 7 ...)
167 * normal Vector ISAs use either Indexed-MV or Indexed-LD/ST to "cope"
168 with this. both are expensive (copy large vectors, spill through memory)
169 and very few Packed SIMD ISAs cope with non-Power-2.
170 * REMAP **redefines** the order of access according to set
171 (Deterministic) "Schedules".
172 * The Schedules are not at all restricted to power-of-two boundaries
173 making it unnecessary to have for example specialised 3x4 transpose
174 instructions of other Vector ISAs.
176 Only the most commonly-used algorithms in computer science have REMAP
177 support, due to the high cost in both the ISA and in hardware. For
178 arbitrary remapping the `Indexed` REMAP may be used.
182 * `svshape` to set the type of reordering to be applied to an
183 otherwise usual `0..VL-1` hardware for-loop
184 * `svremap` to set which registers a given reordering is to apply to
186 * `sv.{instruction}` where any Vectorised register marked by `svremap`
187 will have its ordering REMAPPED according to the schedule set
190 The following illustrative example multiplies a 3x4 and a 5x3
195 svshape 5, 4, 3, 0, 0
196 svremap 15, 1, 2, 3, 0, 0, 0, 0
197 sv.fmadds *0, *8, *16, *0
200 * svshape sets up the four SVSHAPE SPRS for a Matrix Schedule
201 * svremap activates four out of five registers RA RB RC RT RS (15)
207 - RS Remapping to not be activated
208 * sv.fmadds has RT=0.v, RA=8.v, RB=16.v, RC=0.v
209 * With REMAP being active each register's element index is
210 *independently* transformed using the specified SHAPEs.
212 Thus the Vector Loop is arranged such that the use of
213 the multiply-and-accumulate instruction executes precisely the required
214 Schedule to perform an in-place in-registers Matrix Multiply with no
215 need to perform additional Transpose or register copy instructions.
216 The example above may be executed as a unit test and demo,
217 [here](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;h=c15479db9a36055166b6b023c7495f9ca3637333;hb=a17a252e474d5d5bf34026c25a19682e3f2015c3#l94)
221 This section summarises the motivation for each REMAP Schedule
222 and briefly goes over their characteristics and limitations.
223 Further details on the Deterministic Precise-Interruptible algorithms
224 used in these Schedules is found in the [[sv/remap/appendix]].
226 ### Matrix (1D/2D/3D shaping)
228 Matrix Multiplication is a huge part of High-Performance Compute,
230 In many PackedSIMD as well as Scalable Vector ISAs, non-power-of-two
231 Matrix sizes are a serious challenge. PackedSIMD ISAs, in order to
232 cope with for example 3x4 Matrices, recommend rolling data-repetition and loop-unrolling.
233 Aside from the cost of the load on the L1 I-Cache, the trick only
234 works if one of the dimensions X or Y are power-two. Prime Numbers
235 (5x7, 3x5) become deeply problematic to unroll.
237 Even traditional Scalable Vector ISAs have issues with Matrices, often
238 having to perform data Transpose by pushing out through Memory and back,
239 or computing Transposition Indices (costly) then copying to another
242 Matrix REMAP was thus designed to solve these issues by providing Hardware
244 "Schedules" that can view what would otherwise be limited to a strictly
245 linear Vector as instead being 2D (even 3D) *in-place* reordered.
246 With both Transposition and non-power-two being supported the issues
247 faced by other ISAs are mitigated.
249 Limitations of Matrix REMAP are that the Vector Length (VL) is currently
250 restricted to 127: up to 127 FMAs (or other operation)
251 may be performed in total.
252 Also given that it is in-registers only at present some care has to be
253 taken on regfile resource utilisation. However it is perfectly possible
254 to utilise Matrix REMAP to perform the three inner-most "kernel" loops of
255 the usual 6-level large Matrix Multiply, without the usual difficulties
256 associated with SIMD.
258 Also the `svshape` instruction only provides access to part of the
259 Matrix REMAP capability. Rotation and mirroring need to be done by
260 programming the SVSHAPE SPRs directly, which can take a lot more
263 ### FFT/DCT Triple Loop
265 DCT and FFT are some of the most astonishingly used algorithms in
266 Computer Science. Radar, Audio, Video, R.F. Baseband and dozens more. At least
267 two DSPs, TMS320 and Hexagon, have VLIW instructions specially tailored
270 An in-depth analysis showed that it is possible to do in-place in-register
271 DCT and FFT as long as twin-result "butterfly" instructions are provided.
272 These can be found in the [[openpower/isa/svfparith]] page if performing
273 IEEE754 FP transforms. *(For fixed-point transforms, equivalent 3-in 2-out
274 integer operations would be required)*. These "butterfly" instructions
275 avoid the need for a temporary register because the two array positions
276 being overwritten will be "in-flight" in any In-Order or Out-of-Order
279 DCT and FFT Schedules are currently limited to RADIX2 sizes and do not
280 accept predicate masks. Given that it is common to perform recursive
281 convolutions combining smaller Power-2 DCT/FFT to create larger DCT/FFTs
282 in practice the RADIX2 limit is not a problem. A Bluestein convolution
283 to compute arbitrary length is demonstrated by
284 [Project Nayuki](https://www.nayuki.io/res/free-small-fft-in-multiple-languages/fft.py)
288 The purpose of Indexing is to provide a generalised version of
289 Vector ISA "Permute" instructions, such as VSX `vperm`. The
290 Indexing is abstracted out and may be applied to much more
291 than an element move/copy, and is not limited for example
292 to the number of bytes that can fit into a VSX register.
293 Indexing may be applied to LD/ST (even on Indexed LD/ST
294 instructions such as `sv.lbzx`), arithmetic operations,
295 extsw: there is no artificial limit.
297 The only major caveat is that the registers to be used as
298 Indices must not be modified by any instruction after Indexed Mode
299 is established, and neither must MAXVL be altered. Additionally,
300 no register used as an Index may exceed MAXVL-1.
303 these conditions results in `UNDEFINED` behaviour.
304 These conditions allow a Read-After-Write (RAW) Hazard to be created on
305 the entire range of Indices to be subsequently used, but a corresponding
306 Write-After-Read Hazard by any instruction that modifies the Indices
307 **does not have to be created**. Given the large number of registers
308 involved in Indexing this is a huge resource saving and reduction
309 in micro-architectural complexity. MAXVL is likewise
310 included in the RAW Hazards because it is involved in calculating
311 how many registers are to be considered Indices.
313 With these Hazard Mitigations in place, high-performance implementations
314 may read-cache the Indices at the point where a given `svindex` instruction
315 is called (or SVSHAPE SPRs - and MAXVL - directly altered) by issuing
316 background GPR register file reads whilst other instructions are being
319 The original motivation for Indexed REMAP was to mitigate the need to add
320 an expensive `mv.x` to the Scalar ISA, which was likely to be rejected as
321 a stand-alone instruction. Usually a Vector ISA would add a non-conflicting
322 variant (as in VSX `vperm`) but it is common to need to permute by source,
323 with the risk of conflict, that has to be resolved, for example, in AVX-512
326 Indexed REMAP on the other hand **does not prevent conflicts** (overlapping
327 destinations), which on a superficial analysis may be perceived to be a
328 problem, until it is recalled that, firstly, Simple-V is designed specifically
329 to require Program Order to be respected, and that Matrix, DCT and FFT
330 all *already* critically depend on overlapping Reads/Writes: Matrix
331 uses overlapping registers as accumulators. Thus the Register Hazard
332 Management needed by Indexed REMAP *has* to be in place anyway.
334 The cost compared to Matrix and other REMAPs (and Pack/Unpack) is
335 clearly that of the additional reading of the GPRs to be used as Indices,
336 plus the setup cost associated with creating those same Indices.
337 If any Deterministic REMAP can cover the required task, clearly it
338 is adviseable to use it instead.
340 *Programmer's note: some algorithms may require skipping of Indices exceeding
341 VL-1, not MAXVL-1. This may be achieved programmatically by performing
342 an `sv.cmp *BF,*RA,RB` where RA is the same GPRs used in the Indexed REMAP,
343 and RB contains the value of VL returned from `setvl`. The resultant
344 CR Fields may then be used as Predicate Masks to exclude those operations
345 with an Index exceeding VL-1.*
347 ### Parallel Reduction
349 Vector Reduce Mode issues a deterministic tree-reduction schedule to the underlying micro-architecture. Like Scalar reduction, the "Scalar Base"
350 (Power ISA v3.0B) operation is leveraged, unmodified, to give the
351 *appearance* and *effect* of Reduction.
353 In Horizontal-First Mode, Vector-result reduction **requires**
354 the destination to be a Vector, which will be used to store
355 intermediary results.
357 Given that the tree-reduction schedule is deterministic,
358 Interrupts and exceptions
359 can therefore also be precise. The final result will be in the first
360 non-predicate-masked-out destination element, but due again to
361 the deterministic schedule programmers may find uses for the intermediate
364 When Rc=1 a corresponding Vector of co-resultant CRs is also
365 created. No special action is taken: the result *and its CR Field*
366 are stored "as usual" exactly as all other SVP64 Rc=1 operations.
368 Note that the Schedule only makes sense on top of certain instructions:
369 X-Form with a Register Profile of `RT,RA,RB` is fine because two sources
370 and the destination are all the same type. Like Scalar
371 Reduction, nothing is prohibited:
372 the results of execution on an unsuitable instruction may simply
373 not make sense. With care, even 3-input instructions (madd, fmadd, ternlogi)
374 may be used, and whilst it is down to the Programmer to walk through the
375 process the Programmer can be confident that the Parallel-Reduction is
376 guaranteed 100% Deterministic.
378 Critical to note regarding use of Parallel-Reduction REMAP is that,
379 exactly as with all REMAP Modes, the `svshape` instruction *requests*
380 a certain Vector Length (number of elements to reduce) and then
381 sets VL and MAXVL at the number of **operations** needed to be
382 carried out. Thus, equally as importantly, like Matrix REMAP
383 the total number of operations
384 is restricted to 127. Any Parallel-Reduction requiring more operations
385 will need to be done manually in batches (hierarchical
386 recursive Reduction).
388 Also important to note is that the Deterministic Schedule is arranged
389 so that some implementations *may* parallelise it (as long as doing so
390 respects Program Order and Register Hazards). Performance (speed)
392 implementation is neither strictly defined or guaranteed. As with
393 the Vulkan(tm) Specification, strict compliance is paramount whilst
394 performance is at the discretion of Implementors.
396 **Parallel-Reduction with Predication**
398 To avoid breaking the strict RISC-paradigm, keeping the Issue-Schedule
399 completely separate from the actual element-level (scalar) operations,
400 Move operations are **not** included in the Schedule. This means that
401 the Schedule leaves the final (scalar) result in the first-non-masked
402 element of the Vector used. With the predicate mask being dynamic
403 (but deterministic) this result could be anywhere.
405 If that result is needed to be moved to a (single) scalar register
406 then a follow-up `sv.mv/sm=predicate rt, *ra` instruction will be
407 needed to get it, where the predicate is the exact same predicate used
408 in the prior Parallel-Reduction instruction.
410 * If there was only a single
411 bit in the predicate then the result will not have moved or been altered
412 from the source vector prior to the Reduction
413 * If there was more than one bit the result will be in the
414 first element with a predicate bit set.
416 In either case the result is in the element with the first bit set in
419 Programmer's Note: For *some* hardware implementations
420 the vector-to-scalar copy may be a slow operation, as may the Predicated
421 Parallel Reduction itself.
422 It may be better to perform a pre-copy
423 of the values, compressing them (VREDUCE-style) into a contiguous block,
424 which will guarantee that the result goes into the very first element
425 of the destination vector, in which case clearly no follow-up
426 vector-to-scalar MV operation is needed.
430 The simplest usage is to perform an overwrite, specifying all three
431 register operands the same.
434 svshape parallelreduce, 6
438 The Reduction Schedule will issue the Parallel Tree Reduction spanning
439 registers 8 through 13, by adjusting the offsets to RT, RA and RB as
440 necessary (see "Parallel Reduction algorithm" in a later section).
442 A non-overwrite is possible as well but just as with the overwrite
443 version, only those destination elements necessary for storing
444 intermediary computations will be written to: the remaining elements
445 will **not** be overwritten and will **not** be zero'd.
448 svshape parallelreduce, 6
452 However it is critical to note that if the source and destination are
453 not the same then the trick of using a follow-up vector-scalar MV will
456 ### Sub-Vector Horizontal Reduction
458 To achieve Sub-Vector Horizontal Reduction, Pack/Unpack should be enabled,
459 which will turn the Schedule around such that issuing of the Scalar
460 Defined Words is done with SUBVL looping as the inner loop not the
461 outer loop. Rc=1 with Sub-Vectors (SUBVL=2,3,4) is `UNDEFINED` behaviour.
463 ## Determining Register Hazards
465 For high-performance (Multi-Issue, Out-of-Order) systems it is critical
466 to be able to statically determine the extent of Vectors in order to
467 allocate pre-emptive Hazard protection. The next task is to eliminate
468 masked-out elements using predicate bits, freeing up the associated
471 For non-REMAP situations `VL` is sufficient to ascertain early
472 Hazard coverage, and with SVSTATE being a high priority cached
473 quantity at the same level of MSR and PC this is not a problem.
475 The problems come when REMAP is enabled. Indexed REMAP must instead
476 use `MAXVL` as the earliest (simplest)
477 batch-level Hazard Reservation indicator (after taking element-width
478 overriding on the Index source into consideration),
479 but Matrix, FFT and Parallel Reduction must all use completely different
480 schemes. The reason is that VL is used to step through the total
481 number of *operations*, not the number of registers.
482 The "Saving Grace" is that all of the REMAP Schedules are 100% Deterministic.
484 Advance-notice Parallel computation and subsequent cacheing
485 of all of these complex Deterministic REMAP Schedules is
486 *strongly recommended*, thus allowing clear and precise multi-issue
487 batched Hazard coverage to be deployed, *even for Indexed Mode*.
488 This is only possible for Indexed due to the strict guidelines
489 given to Programmers.
491 In short, there exists solutions to the problem of Hazard Management,
492 with varying degrees of refinement possible at correspondingly
493 increasing levels of complexity in hardware.
495 A reminder: when Rc=1 each result register (element) has an associated
496 co-result CR Field (one per result element). Thus above when determining
497 the Write-Hazards for result registers the corresponding Write-Hazards for the
498 corresponding associated co-result CR Field must not be forgotten, *including* when
501 ## REMAP area of SVSTATE SPR
503 The following bits of the SVSTATE SPR are used for REMAP:
505 |32.33|34.35|36.37|38.39|40.41| 42.46 | 62 |
506 | -- | -- | -- | -- | -- | ----- | ------ |
507 |mi0 |mi1 |mi2 |mo0 |mo1 | SVme | RMpst |
509 mi0-2 and mo0-1 each select SVSHAPE0-3 to apply to a given register.
510 mi0-2 apply to RA, RB, RC respectively, as input registers, and
511 likewise mo0-1 apply to output registers (RT/FRT, RS/FRS) respectively.
512 SVme is 5 bits (one for each of mi0-2/mo0-1) and indicates whether the
513 SVSHAPE is actively applied or not.
515 * bit 0 of SVme indicates if mi0 is applied to RA / FRA / BA / BFA
516 * bit 1 of SVme indicates if mi1 is applied to RB / FRB / BB
517 * bit 2 of SVme indicates if mi2 is applied to RC / FRC / BC
518 * bit 3 of SVme indicates if mo0 is applied to RT / FRT / BT / BF
519 * bit 4 of SVme indicates if mo1 is applied to Effective Address / FRS / RS
520 (LD/ST-with-update has an implicit 2nd write register, RA)
522 The "persistence" bit if set will result in all Active REMAPs being applied
529 # svremap instruction <a name="svremap"> </a>
533 svremap SVme,mi0,mi1,mi2,mo0,mo2,pst
535 |0 |6 |11 |13 |15 |17 |19 |21 | 22.25 |26..31 |
536 | -- | -- | -- | -- | -- | -- | -- | -- | ---- | ----- |
537 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | pst | rsvd | XO |
541 * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
546 # registers RA RB RC RT EA/FRS SVSHAPE0-3 indices
547 SVSTATE[32:33] <- mi0
548 SVSTATE[34:35] <- mi1
549 SVSTATE[36:37] <- mi2
550 SVSTATE[38:39] <- mo0
551 SVSTATE[40:41] <- mo1
552 # enable bit for RA RB RC RT EA/FRS
553 SVSTATE[42:46] <- SVme
554 # persistence bit (applies to more than one instruction)
558 Special Registers Altered:
564 `svremap` determines the relationship between registers and SVSHAPE SPRs.
565 The bitmask `SVme` determines which registers have a REMAP applied, and mi0-mo1
566 determine which shape is applied to an activated register. the `pst` bit if
567 cleared indicated that the REMAP operation shall only apply to the immediately-following
568 instruction. If set then REMAP remains permanently enabled until such time as it is
569 explicitly disabled, either by `setvl` setting a new MAXVL, or with another
570 `svremap` instruction. `svindex` and `svshape2` are also capable of setting or
571 clearing persistence, as well as partially covering a subset of the capability of
572 `svremap` to set register-to-SVSHAPE relationships.
574 Programmer's Note: applying non-persistent `svremap` to an instruction that has
575 no REMAP enabled or is a Scalar operation will obviously have no effect but
576 the bits 32 to 46 will at least have been set in SVSTATE. This may prove useful
577 when using `svindex` or `svshape2`.
579 Hardware Architectural Note: when persistence is not set it is critically important
580 to treat the `svremap` and the following SVP64 instruction as an indivisible fused operation.
581 *No state* is stored in the SVSTATE SPR in order to allow continuation should an
582 Interrupt occur between the two instructions. Thus, Interrupts must be prohibited
583 from occurring or other workaround deployed. When persistence is set this issue
586 It is critical to note that if persistence is clear `svremap` is the **only** way
587 to activate REMAP on any given (following) instruction. If persistence is set however then
588 **all** SVP64 instructions go through REMAP as long as `SVme` is non-zero.
594 # SHAPE Remapping SPRs
596 There are four "shape" SPRs, SHAPE0-3, 32-bits in each,
597 which have the same format.
599 Shape is 32-bits. When SHAPE is set entirely to zeros, remapping is
600 disabled: the register's elements are a linear (1D) vector.
602 |31.30|29..28 |27..24| 23..21 | 20..18 | 17..12 |11..6 |5..0 | Mode |
603 |---- |------ |------| ------ | ------- | ------- |----- |----- | ----- |
604 |0b00 |skip |offset| invxyz | permute | zdimsz |ydimsz|xdimsz|Matrix |
605 |0b00 |elwidth|offset|sk1/invxy|0b110/0b111|SVGPR|ydimsz|xdimsz|Indexed|
606 |0b01 |submode|offset| invxyz | submode2| zdimsz |mode |xdimsz|DCT/FFT|
607 |0b10 |submode|offset| invxyz | rsvd | rsvd |rsvd |xdimsz|Preduce|
608 |0b11 | | | | | | | |rsvd |
610 mode sets different behaviours (straight matrix multiply, FFT, DCT).
612 * **mode=0b00** sets straight Matrix Mode
613 * **mode=0b00** with permute=0b110 or 0b111 sets Indexed Mode
614 * **mode=0b01** sets "FFT/DCT" mode and activates submodes
615 * **mode=0b10** sets "Parallel Reduction" Schedules.
617 ## Parallel Reduction Mode
619 Creates the Schedules for Parallel Tree Reduction.
621 * **submode=0b00** selects the left operand index
622 * **submode=0b01** selects the right operand index
624 * When bit 0 of `invxyz` is set, the order of the indices
625 in the inner for-loop are reversed. This has the side-effect
626 of placing the final reduced result in the last-predicated element.
627 It also has the indirect side-effect of swapping the source
628 registers: Left-operand index numbers will always exceed
629 Right-operand indices.
630 When clear, the reduced result will be in the first-predicated
631 element, and Left-operand indices will always be *less* than
633 * When bit 1 of `invxyz` is set, the order of the outer loop
634 step is inverted: stepping begins at the nearest power-of two
635 to half of the vector length and reduces by half each time.
636 When clear the step will begin at 2 and double on each
641 submode2=0 is for FFT. For FFT submode the following schedules may be
644 * **submode=0b00** selects the ``j`` offset of the innermost for-loop
646 * **submode=0b10** selects the ``j+halfsize`` offset of the innermost for-loop
648 * **submode=0b11** selects the ``k`` of exptable (which coefficient)
650 When submode2 is 1 or 2, for DCT inner butterfly submode the following
651 schedules may be selected. When submode2 is 1, additional bit-reversing
654 * **submode=0b00** selects the ``j`` offset of the innermost for-loop,
656 * **submode=0b010** selects the ``j+halfsize`` offset of the innermost for-loop,
657 in reverse-order, in-place
658 * **submode=0b10** selects the ``ci`` count of the innermost for-loop,
659 useful for calculating the cosine coefficient
660 * **submode=0b11** selects the ``size`` offset of the outermost for-loop,
661 useful for the cosine coefficient ``cos(ci + 0.5) * pi / size``
663 When submode2 is 3 or 4, for DCT outer butterfly submode the following
664 schedules may be selected. When submode is 3, additional bit-reversing
667 * **submode=0b00** selects the ``j`` offset of the innermost for-loop,
668 * **submode=0b01** selects the ``j+1`` offset of the innermost for-loop,
670 `zdimsz` is used as an in-place "Stride", particularly useful for
671 column-based in-place DCT/FFT.
675 In Matrix Mode, skip allows dimensions to be skipped from being included
676 in the resultant output index. this allows sequences to be repeated:
677 ```0 0 0 1 1 1 2 2 2 ...``` or in the case of skip=0b11 this results in
678 modulo ```0 1 2 0 1 2 ...```
680 * **skip=0b00** indicates no dimensions to be skipped
681 * **skip=0b01** sets "skip 1st dimension"
682 * **skip=0b10** sets "skip 2nd dimension"
683 * **skip=0b11** sets "skip 3rd dimension"
685 invxyz will invert the start index of each of x, y or z. If invxyz[0] is
686 zero then x-dimensional counting begins from 0 and increments, otherwise
687 it begins from xdimsz-1 and iterates down to zero. Likewise for y and z.
689 offset will have the effect of offsetting the result by ```offset``` elements:
693 GPR(RT + remap(i) + SVSHAPE.offset) = ....
696 this appears redundant because the register RT could simply be changed by a compiler, until element width overrides are introduced. also
697 bear in mind that unlike a static compiler SVSHAPE.offset may
698 be set dynamically at runtime.
700 xdimsz, ydimsz and zdimsz are offset by 1, such that a value of 0 indicates
701 that the array dimensionality for that dimension is 1. any dimension
702 not intended to be used must have its value set to 0 (dimensionality
703 of 1). A value of xdimsz=2 would indicate that in the first dimension
704 there are 3 elements in the array. For example, to create a 2D array
705 X,Y of dimensionality X=3 and Y=2, set xdimsz=2, ydimsz=1 and zdimsz=0
707 The format of the array is therefore as follows:
710 array[xdimsz+1][ydimsz+1][zdimsz+1]
713 However whilst illustrative of the dimensionality, that does not take the
714 "permute" setting into account. "permute" may be any one of six values
715 (0-5, with values of 6 and 7 indicating "Indexed" Mode). The table
716 below shows how the permutation dimensionality order works:
718 | permute | order | array format |
719 | ------- | ----- | ------------------------ |
720 | 000 | 0,1,2 | (xdim+1)(ydim+1)(zdim+1) |
721 | 001 | 0,2,1 | (xdim+1)(zdim+1)(ydim+1) |
722 | 010 | 1,0,2 | (ydim+1)(xdim+1)(zdim+1) |
723 | 011 | 1,2,0 | (ydim+1)(zdim+1)(xdim+1) |
724 | 100 | 2,0,1 | (zdim+1)(xdim+1)(ydim+1) |
725 | 101 | 2,1,0 | (zdim+1)(ydim+1)(xdim+1) |
726 | 110 | 0,1 | Indexed (xdim+1)(ydim+1) |
727 | 111 | 1,0 | Indexed (ydim+1)(xdim+1) |
729 In other words, the "permute" option changes the order in which
730 nested for-loops over the array would be done. See executable
731 python reference code for further details.
733 *Note: permute=0b110 and permute=0b111 enable Indexed REMAP Mode,
736 With all these options it is possible to support in-place transpose,
737 in-place rotate, Matrix Multiply and Convolutions, without being
738 limited to Power-of-Two dimension sizes.
742 Indexed Mode activates reading of the element indices from the GPR
743 and includes optional limited 2D reordering.
744 In its simplest form (without elwidth overrides or other modes):
748 return GPR((SVSHAPE.SVGPR<<1)+i) + SVSHAPE.offset
751 element_result = ....
752 GPR(RT + indexed_remap(i)) = element_result
755 With element-width overrides included, and using the pseudocode
756 from the SVP64 [[sv/svp64/appendix#elwidth]] elwidth section
761 svreg = SVSHAPE.SVGPR << 1
762 srcwid = elwid_to_bitwidth(SVSHAPE.elwid)
763 offs = SVSHAPE.offset
764 return get_polymorphed_reg(svreg, srcwid, i) + offs
767 element_result = ....
768 rt_idx = indexed_remap(i)
769 set_polymorphed_reg(RT, destwid, rt_idx, element_result)
772 Matrix-style reordering still applies to the indices, except limited
773 to up to 2 Dimensions (X,Y). Ordering is therefore limited to (X,Y) or
774 (Y,X) for in-place Transposition.
775 Only one dimension may optionally be skipped. Inversion of either
776 X or Y or both is possible (2D mirroring). Pseudocode for Indexed Mode (including elwidth
777 overrides) may be written in terms of Matrix Mode, specifically
778 purposed to ensure that the 3rd dimension (Z) has no effect:
781 def index_remap(ISHAPE, i):
782 MSHAPE.skip = 0b0 || ISHAPE.sk1
783 MSHAPE.invxyz = 0b0 || ISHAPE.invxy
784 MSHAPE.xdimsz = ISHAPE.xdimsz
785 MSHAPE.ydimsz = ISHAPE.ydimsz
786 MSHAPE.zdimsz = 0 # disabled
787 if ISHAPE.permute = 0b110 # 0,1
788 MSHAPE.permute = 0b000 # 0,1,2
789 if ISHAPE.permute = 0b111 # 1,0
790 MSHAPE.permute = 0b010 # 1,0,2
791 el_idx = remap_matrix(MSHAPE, i)
792 svreg = ISHAPE.SVGPR << 1
793 srcwid = elwid_to_bitwidth(ISHAPE.elwid)
795 return get_polymorphed_reg(svreg, srcwid, el_idx) + offs
798 The most important observation above is that the Matrix-style
799 remapping occurs first and the Index lookup second. Thus it
800 becomes possible to perform in-place Transpose of Indices which
801 may have been costly to set up or costly to duplicate
802 (waste register file space).
808 # svshape instruction <a name="svshape"> </a>
810 Form: SVM-Form SV "Matrix" Form (see [[isatables/fields.text]])
812 svshape SVxd,SVyd,SVzd,SVRM,vf
814 | 0.5|6.10 |11.15 |16..20 | 21..24 | 25 | 26..31| name |
815 | -- | -- | --- | ----- | ------ | -- | ------| -------- |
816 |OPCD| SVxd | SVyd | SVzd | SVRM | vf | XO | svshape |
819 # for convenience, VL to be calculated and stored in SVSTATE
821 mscale[0:5] <- 0b000001 # for scaling MAXVL
822 itercount[0:6] <- [0] * 7
823 SVSTATE[0:31] <- [0] * 32
824 # only overwrite REMAP if "persistence" is zero
825 if (SVSTATE[62] = 0b0) then
826 SVSTATE[32:33] <- 0b00
827 SVSTATE[34:35] <- 0b00
828 SVSTATE[36:37] <- 0b00
829 SVSTATE[38:39] <- 0b00
830 SVSTATE[40:41] <- 0b00
831 SVSTATE[42:46] <- 0b00000
834 # clear out all SVSHAPEs
835 SVSHAPE0[0:31] <- [0] * 32
836 SVSHAPE1[0:31] <- [0] * 32
837 SVSHAPE2[0:31] <- [0] * 32
838 SVSHAPE3[0:31] <- [0] * 32
840 # set schedule up for multiply
841 if (SVrm = 0b0000) then
842 # VL in Matrix Multiply is xd*yd*zd
843 xd <- (0b00 || SVxd) + 1
844 yd <- (0b00 || SVyd) + 1
845 zd <- (0b00 || SVzd) + 1
847 vlen[0:6] <- n[14:20]
848 # set up template in SVSHAPE0, then copy to 1-3
849 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
850 SVSHAPE0[6:11] <- (0b0 || SVyd) # ydim
851 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim
852 SVSHAPE0[28:29] <- 0b11 # skip z
854 SVSHAPE1[0:31] <- SVSHAPE0[0:31]
855 SVSHAPE2[0:31] <- SVSHAPE0[0:31]
856 SVSHAPE3[0:31] <- SVSHAPE0[0:31]
858 SVSHAPE1[18:20] <- 0b001 # permute x,z,y
859 SVSHAPE1[28:29] <- 0b01 # skip z
861 SVSHAPE2[18:20] <- 0b001 # permute x,z,y
862 SVSHAPE2[28:29] <- 0b11 # skip y
864 # set schedule up for FFT butterfly
865 if (SVrm = 0b0001) then
866 # calculate O(N log2 N)
869 if SVxd[4-n] = 0 then
872 n <- ((0b0 || SVxd) + 1) * n
874 # set up template in SVSHAPE0, then copy to 1-3
876 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
877 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D FFT)
878 mscale <- (0b0 || SVzd) + 1
879 SVSHAPE0[30:31] <- 0b01 # Butterfly mode
881 SVSHAPE1[0:31] <- SVSHAPE0[0:31]
882 SVSHAPE2[0:31] <- SVSHAPE0[0:31]
884 SVSHAPE1[28:29] <- 0b01 # j+halfstep schedule
886 SVSHAPE2[28:29] <- 0b10 # k schedule
888 # set schedule up for (i)DCT Inner butterfly
889 # SVrm Mode 2 (Mode 6 for iDCT) is for pre-calculated coefficients,
890 # SVrm Mode 4 (Mode 12 for iDCT) is for on-the-fly (Vertical-First Mode)
891 if ((SVrm = 0b0010) | (SVrm = 0b0100) |
892 (SVrm = 0b1010) | (SVrm = 0b1100)) then
893 # calculate O(N log2 N)
896 if SVxd[4-n] = 0 then
899 n <- ((0b0 || SVxd) + 1) * n
901 # set up template in SVSHAPE0, then copy to 1-3
903 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
904 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D DCT)
905 mscale <- (0b0 || SVzd) + 1
906 if (SVrm = 0b1011) then
907 SVSHAPE0[30:31] <- 0b11 # iDCT mode
908 SVSHAPE0[18:20] <- 0b011 # iDCT Outer Butterfly sub-mode
909 SVSHAPE0[21:23] <- 0b101 # "inverse" on outer and inner loop
911 SVSHAPE0[30:31] <- 0b01 # DCT mode
912 SVSHAPE0[18:20] <- 0b100 # DCT Outer Butterfly sub-mode
913 SVSHAPE0[6:11] <- 0b000010 # DCT Butterfly mode
915 SVSHAPE1[0:31] <- SVSHAPE0[0:31] # j+halfstep schedule
916 SVSHAPE2[0:31] <- SVSHAPE0[0:31] # costable coefficients
918 SVSHAPE1[28:29] <- 0b01 # j+halfstep schedule
919 # reset costable "striding" to 1
920 SVSHAPE2[12:17] <- 0b000000
922 # set schedule up for DCT COS table generation
923 if (SVrm = 0b0101) | (SVrm = 0b1101) then
924 # calculate O(N log2 N)
926 itercount[0:6] <- (0b00 || SVxd) + 0b0000001
927 itercount[0:6] <- (0b0 || itercount[0:5])
930 if SVxd[4-n] = 0 then
933 vlen[0:6] <- vlen + itercount
934 itercount[0:6] <- (0b0 || itercount[0:5])
935 # set up template in SVSHAPE0, then copy to 1-3
937 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
938 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D DCT)
939 mscale <- (0b0 || SVzd) + 1
940 SVSHAPE0[30:31] <- 0b01 # DCT/FFT mode
941 SVSHAPE0[6:11] <- 0b000100 # DCT Inner Butterfly COS-gen mode
942 if (SVrm = 0b0101) then
943 SVSHAPE0[21:23] <- 0b001 # "inverse" on outer loop for DCT
945 SVSHAPE1[0:31] <- SVSHAPE0[0:31]
946 SVSHAPE2[0:31] <- SVSHAPE0[0:31]
947 # for cos coefficient
948 SVSHAPE1[28:29] <- 0b10 # ci schedule
949 SVSHAPE2[28:29] <- 0b11 # size schedule
951 # set schedule up for iDCT / DCT inverse of half-swapped ordering
952 if (SVrm = 0b0110) | (SVrm = 0b1110) | (SVrm = 0b1111) then
953 vlen[0:6] <- (0b00 || SVxd) + 0b0000001
954 # set up template in SVSHAPE0
955 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
956 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D DCT)
957 mscale <- (0b0 || SVzd) + 1
958 if (SVrm = 0b1110) then
959 SVSHAPE0[18:20] <- 0b001 # DCT opposite half-swap
960 if (SVrm = 0b1111) then
961 SVSHAPE0[30:31] <- 0b01 # FFT mode
963 SVSHAPE0[30:31] <- 0b11 # DCT mode
964 SVSHAPE0[6:11] <- 0b000101 # DCT "half-swap" mode
966 # set schedule up for parallel reduction
967 if (SVrm = 0b0111) then
968 # calculate the total number of operations (brute-force)
970 itercount[0:6] <- (0b00 || SVxd) + 0b0000001
971 step[0:6] <- 0b0000001
973 do while step <u itercount
974 newstep <- step[1:6] || 0b0
976 do while (j+step <u itercount)
980 # VL in Parallel-Reduce is the number of operations
982 # set up template in SVSHAPE0, then copy to 1. only 2 needed
983 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
984 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D DCT)
985 mscale <- (0b0 || SVzd) + 1
986 SVSHAPE0[30:31] <- 0b10 # parallel reduce submode
988 SVSHAPE1[0:31] <- SVSHAPE0[0:31]
989 # set up right operand (left operand 28:29 is zero)
990 SVSHAPE1[28:29] <- 0b01 # right operand
992 # set VL, MVL and Vertical-First
993 m[0:12] <- vlen * mscale
994 maxvl[0:6] <- m[6:12]
995 SVSTATE[0:6] <- maxvl # MAVXL
996 SVSTATE[7:13] <- vlen # VL
1000 Special Registers Altered:
1006 `svshape` is a convenience instruction that reduces instruction
1007 count for common usage patterns, particularly Matrix, DCT and FFT. It sets up
1008 (overwrites) all required SVSHAPE SPRs and also modifies SVSTATE
1009 including VL and MAXVL. Using `svshape` therefore does not also
1014 * **SVxd** - SV REMAP "xdim"
1015 * **SVyd** - SV REMAP "ydim"
1016 * **SVzd** - SV REMAP "zdim"
1017 * **SVRM** - SV REMAP Mode (0b00000 for Matrix, 0b00001 for FFT etc.)
1018 * **vf** - sets "Vertical-First" mode
1020 *Note: SVxd, SVyz and SVzd are all stored "off-by-one". In the assembler
1021 mnemonic the values `1-32` are stored in binary as `0b00000..0b11111`*
1023 There are 14 REMAP Modes (2 bits are RESERVED for `svshape2`)
1025 | SVRM | Remap Mode description |
1027 | 0b0000 | Matrix 1/2/3D |
1028 | 0b0001 | FFT Butterfly |
1029 | 0b0010 | DCT Inner butterfly, pre-calculated coefficients |
1030 | 0b0011 | DCT Outer butterfly |
1031 | 0b0100 | DCT Inner butterfly, on-the-fly (Vertical-First Mode) |
1032 | 0b0101 | DCT COS table index generation |
1033 | 0b0110 | DCT half-swap |
1034 | 0b0111 | Parallel Reduction |
1035 | 0b1000 | reserved for svshape2 |
1036 | 0b1001 | reserved for svshape2 |
1037 | 0b1010 | iDCT Inner butterfly, pre-calculated coefficients |
1038 | 0b1011 | iDCT Outer butterfly |
1039 | 0b1100 | iDCT Inner butterfly, on-the-fly (Vertical-First Mode) |
1040 | 0b1101 | iDCT COS table index generation |
1041 | 0b1110 | iDCT half-swap |
1042 | 0b1111 | FFT half-swap |
1044 Examples showing how all of these Modes operate exists in the online
1045 [SVP64 unit tests](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD). Explaining
1046 these Modes further in detail is beyond the scope of this document.
1048 In Indexed Mode, there are only 5 bits available to specify the GPR
1049 to use, out of 128 GPRs (7 bit numbering). Therefore, only the top
1050 5 bits are given in the `SVxd` field: the bottom two implicit bits
1051 will be zero (`SVxd || 0b00`).
1053 `svshape` has *limited applicability* due to being a 32-bit instruction.
1054 The full capability of SVSHAPE SPRs may be accessed by directly writing
1055 to SVSHAPE0-3 with `mtspr`. Circumstances include Matrices with dimensions
1056 larger than 32, and in-place Transpose. Potentially a future v3.1 Prefixed
1057 instruction, `psvshape`, may extend the capability here.
1064 # svindex instruction <a name="svindex"> </a>
1068 | 0.5|6.10 |11.15 |16.20 | 21..25 | 26..31| name | Form |
1069 | -- | -- | --- | ---- | ----------- | ------| -------- | ---- |
1070 |OPCD| SVG | rmm | SVd | ew/yx/mm/sk | XO | svindex | SVI-Form |
1072 * svindex SVG,rmm,SVd,ew,SVyx,mm,sk
1077 # based on nearest MAXVL compute other dimension
1081 do while d*dim <u ([0]*4 || MVL)
1084 # set up template, then copy once location identified
1086 shape[30:31] <- 0b00 # mode
1088 shape[18:20] <- 0b110 # indexed xd/yd
1089 shape[0:5] <- (0b0 || SVd) # xdim
1090 if sk = 0 then shape[6:11] <- 0 # ydim
1091 else shape[6:11] <- 0b111111 # ydim max
1093 shape[18:20] <- 0b111 # indexed yd/xd
1094 if sk = 1 then shape[6:11] <- 0 # ydim
1095 else shape[6:11] <- d-1 # ydim max
1096 shape[0:5] <- (0b0 || SVd) # ydim
1097 shape[12:17] <- (0b0 || SVG) # SVGPR
1098 shape[28:29] <- ew # element-width override
1099 shape[21] <- sk # skip 1st dimension
1101 # select the mode for updating SVSHAPEs
1102 SVSTATE[62] <- mm # set or clear persistence
1104 # clear out all SVSHAPEs first
1105 SVSHAPE0[0:31] <- [0] * 32
1106 SVSHAPE1[0:31] <- [0] * 32
1107 SVSHAPE2[0:31] <- [0] * 32
1108 SVSHAPE3[0:31] <- [0] * 32
1109 SVSTATE[32:41] <- [0] * 10 # clear REMAP.mi/o
1110 SVSTATE[42:46] <- rmm # rmm exactly REMAP.SVme
1114 # activate requested shape
1115 if idx = 0 then SVSHAPE0 <- shape
1116 if idx = 1 then SVSHAPE1 <- shape
1117 if idx = 2 then SVSHAPE2 <- shape
1118 if idx = 3 then SVSHAPE3 <- shape
1119 SVSTATE[bit*2+32:bit*2+33] <- idx
1120 # increment shape index, modulo 4
1121 if idx = 3 then idx <- 0
1124 # refined SVSHAPE/REMAP update mode
1127 if idx = 0 then SVSHAPE0 <- shape
1128 if idx = 1 then SVSHAPE1 <- shape
1129 if idx = 2 then SVSHAPE2 <- shape
1130 if idx = 3 then SVSHAPE3 <- shape
1131 SVSTATE[bit*2+32:bit*2+33] <- idx
1132 SVSTATE[46-bit] <- 1
1135 Special Registers Altered:
1141 `svindex` is a convenience instruction that reduces instruction
1142 count for Indexed REMAP Mode. It sets up
1143 (overwrites) all required SVSHAPE SPRs and can modify the REMAP
1144 area of the SVSTATE SPR as well. The relevant SPRs *may* be directly programmed with
1145 `mtspr` however it is laborious to do so: svindex saves instructions
1146 covering much of Indexed REMAP capability.
1150 * **SVd** - SV REMAP x/y dim
1151 * **rmm** - REMAP mask: sets remap mi0-2/mo0-1 and SVSHAPEs,
1153 * **ew** - sets element width override on the Indices
1154 * **SVG** - GPR SVG<<2 to be used for Indexing
1155 * **yx** - 2D reordering to be used if yx=1
1156 * **mm** - mask mode. determines how `rmm` is interpreted.
1157 * **sk** - Dimension skipping enabled
1159 *Note: SVd, like SVxd, SVyz and SVzd of `svshape`, are all stored
1160 "off-by-one". In the assembler
1161 mnemonic the values `1-32` are stored in binary as `0b00000..0b11111`*.
1163 *Note: when `yx=1,sk=0` the second dimension is calculated as
1168 * `rmm`, like REMAP.SVme, has bit 0
1169 correspond to mi0, bit 1 to mi1, bit 2 to mi2,
1170 bit 3 to mo0 and bit 4 to mi1
1171 * all SVSHAPEs and the REMAP parts of SVSHAPE are first reset (initialised to zero)
1172 * for each bit set in the 5-bit `rmm`, in order, the first
1173 as-yet-unset SVSHAPE will be updated
1174 with the other operands in the instruction, and the REMAP
1176 * If all 5 bits of `rmm` are set then both mi0 and mo1 use SVSHAPE0.
1177 * SVSTATE persistence bit is cleared
1178 * No other alterations to SVSTATE are carried out
1180 Example 1: if rmm=0b00110 then SVSHAPE0 and SVSHAPE1 are set up,
1181 and the REMAP SPR set so that mi1 uses SVSHAPE0 and mi2
1182 uses mi2. REMAP.SVme is also set to 0b00110, REMAP.mi1=0
1183 (SVSHAPE0) and REMAP.mi2=1 (SVSHAPE1)
1185 Example 2: if rmm=0b10001 then again SVSHAPE0 and SVSHAPE1
1186 are set up, but the REMAP SPR is set so that mi0 uses SVSHAPE0
1187 and mo1 uses SVSHAPE1. REMAP.SVme=0b10001, REMAP.mi0=0, REMAP.mo1=1
1189 Rough algorithmic form:
1192 marray = [mi0, mi1, mi2, mo0, mo1]
1195 if not rmm[bit]: continue
1197 SVSTATE{marray[bit]} = idx
1198 idx = (idx+1) modulo 4
1203 * bits 0-2 (MSB0 numbering) of `rmm` indicate an index selecting mi0-mo1
1204 * bits 3-4 (MSB0 numbering) of `rmm` indicate which SVSHAPE 0-3 shall
1206 * only the selected SVSHAPE is overwritten
1207 * only the relevant bits in the REMAP area of SVSTATE are updated
1208 * REMAP persistence bit is set.
1210 Example 1: if `rmm`=0b01110 then bits 0-2 (MSB0) are 0b011 and
1211 bits 3-4 are 0b10. thus, mo0 is selected and SVSHAPE2
1212 to be updated. REMAP.SVme[3] will be set high and REMAP.mo0
1213 set to 2 (SVSHAPE2).
1215 Example 2: if `rmm`=0b10011 then bits 0-2 (MSB0) are 0b100 and
1216 bits 3-4 are 0b11. thus, mo1 is selected and SVSHAPE3
1217 to be updated. REMAP.SVme[4] will be set high and REMAP.mo1
1218 set to 3 (SVSHAPE3).
1220 Rough algorithmic form:
1223 marray = [mi0, mi1, mi2, mo0, mo1]
1227 SVSTATE{marray[bit]} = idx
1231 In essence, `mm=0` is intended for use to set as much of the
1232 REMAP State SPRs as practical with a single instruction,
1233 whilst `mm=1` is intended to be a little more refined.
1235 **Usage guidelines**
1237 * **Disable 2D mapping**: to only perform Indexing without
1238 reordering use `SVd=1,sk=0,yx=0` (or set SVd to a value larger
1240 * **Modulo 1D mapping**: to perform Indexing cycling through the
1241 first N Indices use `SVd=N,sk=0,yx=0` where `VL>N`. There is
1242 no requirement to set VL equal to a multiple of N.
1243 * **Modulo 2D transposed**: `SVd=M,sk=0,yx=1`, sets
1244 `xdim=M,ydim=CEIL(MAXVL/M)`.
1246 Beyond these mappings it becomes necessary to write directly to
1247 the SVSTATE SPRs manually.
1254 # svshape2 (offset) <a name="svshape2"> </a>
1256 `svshape2` is an additional convenience instruction that prioritises
1257 setting `SVSHAPE.offset`. Its primary purpose is for use when
1258 element-width overrides are used. It has identical capabilities to `svindex` and
1259 in terms of both options (skip, etc.) and ability to activate REMAP
1260 (rmm, mask mode) but unlike `svindex` it does not set GPR REMAP,
1261 only a 1D or 2D `svshape`, and
1262 unlike `svshape` it can set an arbirrary `SVSHAPE.offset` immediate.
1264 One of the limitations of Simple-V is that Vector elements start on the boundary
1265 of the Scalar regfile, which is fine when element-width overrides are not
1266 needed. If the starting point of a Vector with smaller elwidths must begin
1267 in the middle of a register, normally there would be no way to do so except
1268 through LD/ST. `SVSHAPE.offset` caters for this scenario and `svshape2`is
1271 svshape2 offs,yx,rmm,SVd,sk,mm
1273 | 0.5|6..9|10|11.15 |16..20 | 21..25 | 25 | 26..31| name |
1274 | -- |----|--| --- | ----- | ------ | -- | ------| -------- |
1275 |OPCD|offs|yx| rmm | SVd | 100/mm | sk | XO | svshape |
1277 * **offs** (4 bits) - unsigned offset
1278 * **yx** (1 bit) - swap XY to YX
1279 * **SVd** dimension size
1280 * **rmm** REMAP mask
1282 * **sk** (1 bit) skips 1st dimension if set
1284 Dimensions are calculated exactly as `svindex`. `rmm` and
1285 `mm` are as per `svindex`.
1287 *Programmer's Note: offsets for `svshape2` may be specified in the range
1288 0-15. Given that the principle of Simple-V is to fit on top of
1289 byte-addressable register files and that GPR and FPR are 64-bit (8 bytes)
1290 it should be clear that the offset may, when `elwidth=8`, begin an
1291 element-level operation starting element zero at any arbitrary byte.
1292 On cursory examination attempting to go beyond the range 0-7 seems
1293 unnecessary given that the **next GPR or FPR** is an
1294 alias for an offset in the range 8-15. Thus by simply increasing
1295 the starting Vector point of the operation to the next register it
1296 can be seen that the offset of 0-7 would be sufficient. Unfortunately
1297 however some operations are EXTRA2-encoded it is **not possible**
1298 to increase the GPR/FPR register number by one, because EXTRA2-encoding
1299 of GPR/FPR Vector numbers are restricted to even numbering.
1300 For CR Fields the EXTRA2 encoding is even more sparse.
1301 The additional offset range (8-15) helps overcome these limitations.*
1303 *Hardware Implementor's note: with the offsets only being immediates
1304 and with register numbering being entirely immediate as well it is
1305 possible to correctly compute Register Hazards without requiring
1306 reading the contents of any SPRs. If however there are
1307 instructions that have directly written to the SVSTATE or SVSHAPE
1308 SPRs and those instructions are still in-flight then this position
1309 is clearly **invalid**. This is why Programmers are strongly
1310 discouraged from directly writing to these SPRs.*
1318 Add the following to Book I, 1.6.1, SVI-Form
1321 |0 |6 |11 |16 |21 |23 |24|25|26 31|
1322 | PO | SVG|rmm | SVd |ew |SVyx|mm|sk| XO |
1325 Add the following to Book I, 1.6.1, SVM-Form
1328 |0 |6 |11 |16 |21 |25 |26 |31 |
1329 | PO | SVxd | SVyd | SVzd | SVrm |vf | XO |
1332 Add the following to Book I, 1.6.1, SVM2-Form
1335 |0 |6 |10 |11 |16 |21 |24|25 |26 |31 |
1336 | PO | SVo |SVyx| rmm | SVd |XO |mm|sk | XO |
1339 Add the following to Book I, 1.6.1, SVRM-Form
1342 |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 |
1343 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO |
1346 * Add `SVI, SVM, SVM2, SVRM` to `XO (26:31)` Field in Book I, 1.6.2
1348 Add the following to Book I, 1.6.2
1352 Field used in REMAP to select the SVSHAPE for 1st input register
1355 Field used in REMAP to select the SVSHAPE for 2nd input register
1358 Field used in REMAP to select the SVSHAPE for 3rd input register
1361 Field used to specify the meaning of the rmm field for SVI-Form
1365 Field used in REMAP to select the SVSHAPE for 1st output register
1368 Field used in REMAP to select the SVSHAPE for 2nd output register
1371 Field used in REMAP to indicate "persistence" mode (REMAP
1372 continues to apply to multiple instructions)
1375 REMAP Mode field for SVI-Form and SVM2-Form
1378 Field used to specify dimensional skipping in svindex
1381 Immediate field used to specify the size of the REMAP dimension
1382 in the svindex and svshape2 instructions
1385 Immediate field used to specify a 9-bit signed
1386 two's complement integer which is concatenated
1387 on the right with 0b00 and sign-extended to 64 bits.
1390 Field used to specify a GPR to be used as a
1391 source for indexing.
1394 Simple-V immediate field for setting VL or MVL
1397 Simple-V "REMAP" map-enable bits (0-4)
1400 Field used by the svshape2 instruction as an offset
1403 Simple-V "REMAP" Mode
1406 Simple-V "REMAP" x-dimension size
1409 Simple-V "REMAP" y-dimension size
1412 Simple-V "REMAP" z-dimension size
1418 Appendix E Power ISA sorted by opcode
1419 Appendix F Power ISA sorted by version
1420 Appendix G Power ISA sorted by Compliancy Subset
1421 Appendix H Power ISA sorted by mnemonic
1423 | Form | Book | Page | Version | mnemonic | Description |
1424 |------|------|------|---------|----------|-------------|
1425 | SVRM | I | # | 3.0B | svremap | REMAP enabling instruction |