1 # RFC ls009 SVP64 REMAP instructions
5 * <https://libre-soc.org/openpower/sv/>
6 * <https://libre-soc.org/openpower/sv/rfc/ls009/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1042>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
20 **Books and Section affected**:
23 Book I, new Zero-Overhead-Loop Chapter.
24 Appendix E Power ISA sorted by opcode
25 Appendix F Power ISA sorted by version
26 Appendix G Power ISA sorted by Compliancy Subset
27 Appendix H Power ISA sorted by mnemonic
33 svremap - Re-Mapping of Register Element Offsets
34 svindex - General-purpose setting of SHAPEs to be re-mapped
35 svshape - Hardware-level setting of SHAPEs for element re-mapping
36 svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
39 **Submitter**: Luke Leighton (Libre-SOC)
41 **Requester**: Libre-SOC
43 **Impact on processor**:
46 Addition of four new "Zero-Overhead-Loop-Control" DSP-style Vector-style
47 Management Instructions which provide advanced features such as Matrix
48 FFT DCT Hardware-Assist Schedules and general-purpose Index reordering.
51 **Impact on software**:
54 Requires support for new instructions in assembler, debuggers,
61 Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
62 Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
63 Digital Signal Processing (DSP)
68 These REMAP Management instructions provide state-of-the-art advanced capabilities
69 to dramatically decrease instruction count and power reduction whilst retaining
70 unprecedented general-purpose capability and a standard Sequential Execution Model.
72 **Notes and Observations**:
78 Add the following entries to:
80 * the Appendices of Book I
81 * Instructions of Book I as a new Section
82 * TODO-Form of Book I Section 1.6.1.6 and 1.6.2
88 # REMAP <a name="remap" />
90 REMAP is an advanced form of Vector "Structure Packing" that
91 provides hardware-level support for commonly-used *nested* loop patterns.
92 For more general reordering an Indexed REMAP mode is available.
94 REMAP allows the usual vector loop `0..VL-1` to be "reshaped" (re-mapped)
95 from a linear form to a 2D or 3D transposed form, or "offset" to permit
96 arbitrary access to elements (when elwidth overrides are used),
97 independently on each Vector src or dest
98 register. Aside from Indexed REMAP this is entirely Hardware-accelerated
99 reordering and consequently not costly in terms of register access. It
100 will however place a burden on Multi-Issue systems but no more than if
101 the equivalent Scalar instructions were explicitly
102 loop-unrolled without SVP64, and some advanced implementations may even find
103 the Deterministic nature of the Scheduling to be easier on resources.
105 The initial primary motivation of REMAP was for Matrix Multiplication, reordering
106 of sequential data in-place: in-place DCT and FFT were easily justified given the
107 high usage in Computer Science.
108 Four SPRs are provided which may be applied to any GPR, FPR or CR Field
109 so that for example a single FMAC may be
110 used in a single hardware-controlled 100% Deterministic loop to
111 perform 5x3 times 3x4 Matrix multiplication,
112 generating 60 FMACs *without needing explicit assembler unrolling*.
113 Additional uses include regular "Structure Packing"
114 such as RGB pixel data extraction and reforming.
116 REMAP, like all of SV, is abstracted out, meaning that unlike traditional
117 Vector ISAs which would typically only have a limited set of instructions
118 that can be structure-packed (LD/ST typically), REMAP may be applied to
119 literally any instruction: CRs, Arithmetic, Logical, LD/ST, anything.
121 Note that REMAP does not *directly* apply to sub-vector elements: that
122 is what swizzle is for. Swizzle *can* however be applied to the same
123 instruction as REMAP. As explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack EXTRA Mode bits
124 can extend down into Sub-vector elements to perform vec2/vec3/vec4
125 sequential reordering, but even here, REMAP is not extended down to
126 the actual sub-vector elements themselves.
128 In its general form, REMAP is quite expensive to set up, and on some
129 implementations may introduce
130 latency, so should realistically be used only where it is worthwhile.
131 Commonly-used patterns such as Matrix Multiply, DCT and FFT have
132 helper instruction options which make REMAP easier to use.
134 There are four types of REMAP:
136 * **Matrix**, also known as 2D and 3D reshaping, can perform in-place
137 Matrix transpose and rotate. The Shapes are set up for an "Outer Product"
139 * **FFT/DCT**, with full triple-loop in-place support: limited to
141 * **Indexing**, for any general-purpose reordering, also includes
142 limited 2D reshaping.
143 * **Parallel Reduction**, for scheduling a sequence of operations
144 in a Deterministic fashion, in a way that may be parallelised,
145 to reduce a Vector down to a single value.
147 Best implemented on top of a Multi-Issue Out-of-Order Micro-architecture,
148 REMAP Schedules are 100% Deterministic **including Indexing** and are
149 designed to be incorporated in between the Decode and Issue phases,
150 directly into Register Hazard Management.
152 Parallel Reduction is unusual in that it requires a full vector array
153 of results (not a scalar) and uses the rest of the result Vector for
154 the purposes of storing intermediary calculations. As these intermediary
155 results are Deterministically computed they may be useful.
156 Additionally, because the intermediate results are always written out
157 it is possible to service Precise Interrupts without affecting latency
158 (a common limitation of Vector ISAs implementing explicit
159 Parallel Reduction instructions).
163 * normal vector element read/write of operands would be sequential
165 * this is not appropriate for (e.g.) Matrix multiply which requires
166 accessing elements in alternative sequences (0 3 6 1 4 7 ...)
167 * normal Vector ISAs use either Indexed-MV or Indexed-LD/ST to "cope"
168 with this. both are expensive (copy large vectors, spill through memory)
169 and very few Packed SIMD ISAs cope with non-Power-2.
170 * REMAP **redefines** the order of access according to set
171 (Deterministic) "Schedules".
172 * The Schedules are not at all restricted to power-of-two boundaries
173 making it unnecessary to have for example specialised 3x4 transpose
174 instructions of other Vector ISAs.
176 Only the most commonly-used algorithms in computer science have REMAP
177 support, due to the high cost in both the ISA and in hardware. For
178 arbitrary remapping the `Indexed` REMAP may be used.
182 * `svshape` to set the type of reordering to be applied to an
183 otherwise usual `0..VL-1` hardware for-loop
184 * `svremap` to set which registers a given reordering is to apply to
186 * `sv.{instruction}` where any Vectorised register marked by `svremap`
187 will have its ordering REMAPPED according to the schedule set
190 The following illustrative example multiplies a 3x4 and a 5x3
195 svshape 5, 4, 3, 0, 0
196 svremap 15, 1, 2, 3, 0, 0, 0, 0
197 sv.fmadds *0, *8, *16, *0
200 * svshape sets up the four SVSHAPE SPRS for a Matrix Schedule
201 * svremap activates four out of five registers RA RB RC RT RS (15)
207 - RS Remapping to not be activated
208 * sv.fmadds has RT=0.v, RA=8.v, RB=16.v, RC=0.v
209 * With REMAP being active each register's element index is
210 *independently* transformed using the specified SHAPEs.
212 Thus the Vector Loop is arranged such that the use of
213 the multiply-and-accumulate instruction executes precisely the required
214 Schedule to perform an in-place in-registers Matrix Multiply with no
215 need to perform additional Transpose or register copy instructions.
216 The example above may be executed as a unit test and demo,
217 [here](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;h=c15479db9a36055166b6b023c7495f9ca3637333;hb=a17a252e474d5d5bf34026c25a19682e3f2015c3#l94)
221 This section summarises the motivation for each REMAP Schedule
222 and briefly goes over their characteristics and limitations.
223 Further details on the Deterministic Precise-Interruptible algorithms
224 used in these Schedules is found in the [[sv/remap/appendix]].
226 ### Matrix (1D/2D/3D shaping)
228 Matrix Multiplication is a huge part of High-Performance Compute,
230 In many PackedSIMD as well as Scalable Vector ISAs, non-power-of-two
231 Matrix sizes are a serious challenge. PackedSIMD ISAs, in order to
232 cope with for example 3x4 Matrices, recommend rolling data-repetition and loop-unrolling.
233 Aside from the cost of the load on the L1 I-Cache, the trick only
234 works if one of the dimensions X or Y are power-two. Prime Numbers
235 (5x7, 3x5) become deeply problematic to unroll.
237 Even traditional Scalable Vector ISAs have issues with Matrices, often
238 having to perform data Transpose by pushing out through Memory and back,
239 or computing Transposition Indices (costly) then copying to another
242 Matrix REMAP was thus designed to solve these issues by providing Hardware
244 "Schedules" that can view what would otherwise be limited to a strictly
245 linear Vector as instead being 2D (even 3D) *in-place* reordered.
246 With both Transposition and non-power-two being supported the issues
247 faced by other ISAs are mitigated.
249 Limitations of Matrix REMAP are that the Vector Length (VL) is currently
250 restricted to 127: up to 127 FMAs (or other operation)
251 may be performed in total.
252 Also given that it is in-registers only at present some care has to be
253 taken on regfile resource utilisation. However it is perfectly possible
254 to utilise Matrix REMAP to perform the three inner-most "kernel" loops of
255 the usual 6-level large Matrix Multiply, without the usual difficulties
256 associated with SIMD.
258 Also the `svshape` instruction only provides access to part of the
259 Matrix REMAP capability. Rotation and mirroring need to be done by
260 programming the SVSHAPE SPRs directly, which can take a lot more
263 ### FFT/DCT Triple Loop
265 DCT and FFT are some of the most astonishingly used algorithms in
266 Computer Science. Radar, Audio, Video, R.F. Baseband and dozens more. At least
267 two DSPs, TMS320 and Hexagon, have VLIW instructions specially tailored
270 An in-depth analysis showed that it is possible to do in-place in-register
271 DCT and FFT as long as twin-result "butterfly" instructions are provided.
272 These can be found in the [[openpower/isa/svfparith]] page if performing
273 IEEE754 FP transforms. *(For fixed-point transforms, equivalent 3-in 2-out
274 integer operations would be required)*. These "butterfly" instructions
275 avoid the need for a temporary register because the two array positions
276 being overwritten will be "in-flight" in any In-Order or Out-of-Order
279 DCT and FFT Schedules are currently limited to RADIX2 sizes and do not
280 accept predicate masks. Given that it is common to perform recursive
281 convolutions combining smaller Power-2 DCT/FFT to create larger DCT/FFTs
282 in practice the RADIX2 limit is not a problem. A Bluestein convolution
283 to compute arbitrary length is demonstrated by
284 [Project Nayuki](https://www.nayuki.io/res/free-small-fft-in-multiple-languages/fft.py)
288 The purpose of Indexing is to provide a generalised version of
289 Vector ISA "Permute" instructions, such as VSX `vperm`. The
290 Indexing is abstracted out and may be applied to much more
291 than an element move/copy, and is not limited for example
292 to the number of bytes that can fit into a VSX register.
293 Indexing may be applied to LD/ST (even on Indexed LD/ST
294 instructions such as `sv.lbzx`), arithmetic operations,
295 extsw: there is no artificial limit.
297 The only major caveat is that the registers to be used as
298 Indices must not be modified by any instruction after Indexed Mode
299 is established, and neither must MAXVL be altered. Additionally,
300 no register used as an Index may exceed MAXVL-1.
303 these conditions results in `UNDEFINED` behaviour.
304 These conditions allow a Read-After-Write (RAW) Hazard to be created on
305 the entire range of Indices to be subsequently used, but a corresponding
306 Write-After-Read Hazard by any instruction that modifies the Indices
307 **does not have to be created**. Given the large number of registers
308 involved in Indexing this is a huge resource saving and reduction
309 in micro-architectural complexity. MAXVL is likewise
310 included in the RAW Hazards because it is involved in calculating
311 how many registers are to be considered Indices.
313 With these Hazard Mitigations in place, high-performance implementations
314 may read-cache the Indices from the point where a given `svindex` instruction
315 is called (or SVSHAPE SPRs - and MAXVL- directly altered).
317 The original motivation for Indexed REMAP was to mitigate the need to add
318 an expensive `mv.x` to the Scalar ISA, which was likely to be rejected as
319 a stand-alone instruction. Usually a Vector ISA would add a non-conflicting
320 variant (as in VSX `vperm`) but it is common to need to permute by source,
321 with the risk of conflict, that has to be resolved, for example, in AVX-512
324 Indexed REMAP on the other hand **does not prevent conflicts** (overlapping
325 destinations), which on a superficial analysis may be perceived to be a
326 problem, until it is recalled that, firstly, Simple-V is designed specifically
327 to require Program Order to be respected, and that Matrix, DCT and FFT
328 all *already* critically depend on overlapping Reads/Writes: Matrix
329 uses overlapping registers as accumulators. Thus the Register Hazard
330 Management needed by Indexed REMAP *has* to be in place anyway.
332 The cost compared to Matrix and other REMAPs (and Pack/Unpack) is
333 clearly that of the additional reading of the GPRs to be used as Indices,
334 plus the setup cost associated with creating those same Indices.
335 If any Deterministic REMAP can cover the required task, clearly it
336 is adviseable to use it instead.
338 *Programmer's note: some algorithms may require skipping of Indices exceeding
339 VL-1, not MAXVL-1. This may be achieved programmatically by performing
340 an `sv.cmp *BF,*RA,RB` where RA is the same GPRs used in the Indexed REMAP,
341 and RB contains the value of VL returned from `setvl`. The resultant
342 CR Fields may then be used as Predicate Masks to exclude those operations
343 with an Index exceeding VL-1.*
345 ### Parallel Reduction
347 Vector Reduce Mode issues a deterministic tree-reduction schedule to the underlying micro-architecture. Like Scalar reduction, the "Scalar Base"
348 (Power ISA v3.0B) operation is leveraged, unmodified, to give the
349 *appearance* and *effect* of Reduction.
351 In Horizontal-First Mode, Vector-result reduction **requires**
352 the destination to be a Vector, which will be used to store
353 intermediary results.
355 Given that the tree-reduction schedule is deterministic,
356 Interrupts and exceptions
357 can therefore also be precise. The final result will be in the first
358 non-predicate-masked-out destination element, but due again to
359 the deterministic schedule programmers may find uses for the intermediate
362 When Rc=1 a corresponding Vector of co-resultant CRs is also
363 created. No special action is taken: the result and its CR Field
364 are stored "as usual" exactly as all other SVP64 Rc=1 operations.
366 Note that the Schedule only makes sense on top of certain instructions:
367 X-Form with a Register Profile of `RT,RA,RB` is fine because two sources
368 and the destination are all the same type. Like Scalar
369 Reduction, nothing is prohibited:
370 the results of execution on an unsuitable instruction may simply
371 not make sense. With care, even 3-input instructions (madd, fmadd, ternlogi)
374 Critical to note regarding use of Parallel-Reduction REMAP is that,
375 exactly as with all REMAP Modes, the `svshape` instruction *requests*
376 a certain Vector Length (number of elements to reduce) and then
377 sets VL and MAXVL at the number of **operations** needed to be
378 carried out. Thus, equally as importantly, like Matrix REMAP
379 the total number of operations
380 is restricted to 127. Any Parallel-Reduction requiring more operations
381 will need to be done manually in batches (hierarchical
382 recursive Reduction).
384 Also important to note is that the Deterministic Schedule is arranged
385 so that some implementations *may* parallelise it (as long as doing so
386 respects Program Order and Register Hazards). Performance (speed)
388 implementation is neither strictly defined or guaranteed. As with
389 the Vulkan(tm) Specification, strict compliance is paramount whilst
390 performance is at the discretion of Implementors.
392 **Parallel-Reduction with Predication**
394 To avoid breaking the strict RISC-paradigm, keeping the Issue-Schedule
395 completely separate from the actual element-level (scalar) operations,
396 Move operations are **not** included in the Schedule. This means that
397 the Schedule leaves the final (scalar) result in the first-non-masked
398 element of the Vector used. With the predicate mask being dynamic
399 (but deterministic) this result could be anywhere.
401 If that result is needed to be moved to a (single) scalar register
402 then a follow-up `sv.mv/sm=predicate rt, *ra` instruction will be
403 needed to get it, where the predicate is the exact same predicate used
404 in the prior Parallel-Reduction instruction.
406 * If there was only a single
407 bit in the predicate then the result will not have moved or been altered
408 from the source vector prior to the Reduction
409 * If there was more than one bit the result will be in the
410 first element with a predicate bit set.
412 In either case the result is in the element with the first bit set in
415 Programmer's Note: For *some* hardware implementations
416 the vector-to-scalar copy may be a slow operation, as may the Predicated
417 Parallel Reduction itself.
418 It may be better to perform a pre-copy
419 of the values, compressing them (VREDUCE-style) into a contiguous block,
420 which will guarantee that the result goes into the very first element
421 of the destination vector, in which case clearly no follow-up
422 vector-to-scalar MV operation is needed.
426 The simplest usage is to perform an overwrite, specifying all three
427 register operands the same.
430 svshape parallelreduce, 6
434 The Reduction Schedule will issue the Parallel Tree Reduction spanning
435 registers 8 through 13, by adjusting the offsets to RT, RA and RB as
436 necessary (see "Parallel Reduction algorithm" in a later section).
438 A non-overwrite is possible as well but just as with the overwrite
439 version, only those destination elements necessary for storing
440 intermediary computations will be written to: the remaining elements
441 will **not** be overwritten and will **not** be zero'd.
444 svshape parallelreduce, 6
448 However it is critical to note that if the source and destination are
449 not the same then the trick of using a follow-up vector-scalar MV will
452 ### Sub-Vector Horizontal Reduction
454 Note that when SVM is clear and SUBVL!=1 a Parallel Reduction is performed
455 on all first Subvector elements, followed by another separate independent
456 Parallel Reduction on all the second Subvector elements and so on.
458 for selectsubelement in (x,y,z,w):
459 parallelreduce(0..VL-1, selectsubelement)
461 By contrast, when SVM is set and SUBVL!=1, a Horizontal
462 Subvector mode is enabled, applying the Parallel Reduction
463 Algorithm to the Subvector Elements. The Parallel Reduction
464 is independently applied VL times, to each group of Subvector
465 elements. Bear in mind that predication is never applied down
466 into individual Subvector elements, but will be applied
467 to select whether the *entire* Parallel Reduction on each
468 group is performed or not.
470 Â for (i = 0; i < VL; i++)
471 if (predval & 1<<i) # predication
473 parallelreduction([el.x, el.y, el.z, el.w])
475 Note that as this is a Parallel Reduction, for best results
476 it should be an overwrite operation, where the result for
477 the Horizontal Reduction of each Subvector will be in the
478 first Subvector element.
479 Also note that use of Rc=1 is `UNDEFINED` behaviour.
481 In essence what is happening here is that Structure Packing is being
482 combined with Parallel Reduction. If the Subvector elements may be
483 laid out as a 2D matrix, with the Subvector elements on rows,
484 and Parallel Reduction is applied per row, then if `SVM` is **clear**
485 the Matrix is transposed (like Pack/Unpack)
486 before still applying the Parallel Reduction to the **row**.
488 ## Determining Register Hazards
490 For high-performance (Multi-Issue, Out-of-Order) systems it is critical
491 to be able to statically determine the extent of Vectors in order to
492 allocate pre-emptive Hazard protection. The next task is to eliminate
493 masked-out elements using predicate bits, freeing up the associated
496 For non-REMAP situations `VL` is sufficient to ascertain early
497 Hazard coverage, and with SVSTATE being a high priority cached
498 quantity at the same level of MSR and PC this is not a problem.
500 The problems come when REMAP is enabled. Indexed REMAP must instead
501 use `MAXVL` as the earliest (simplest)
502 batch-level Hazard Reservation indicator,
503 but Matrix, FFT and Parallel Reduction must all use completely different
504 schemes. The reason is that VL is used to step through the total
505 number of *operations*, not the number of registers. The "Saving Grace"
506 is that all of the REMAP Schedules are Deterministic.
508 Advance-notice Parallel computation and subsequent cacheing
509 of all of these complex Deterministic REMAP Schedules is
510 *strongly recommended*, thus allowing clear and precise multi-issue
511 batched Hazard coverage to be deployed, *even for Indexed Mode*.
512 This is only possible for Indexed due to the strict guidelines
513 given to Programmers.
515 In short, there exists solutions to the problem of Hazard Management,
516 with varying degrees of refinement possible at correspondingly
517 increasing levels of complexity in hardware.
519 ## REMAP area of SVSTATE
521 The following bits of the SVSTATE SPR are used for REMAP:
523 |32.33|34.35|36.37|38.39|40.41| 42.46 | 62 |
524 | -- | -- | -- | -- | -- | ----- | ------ |
525 |mi0 |mi1 |mi2 |mo0 |mo1 | SVme | RMpst |
527 mi0-2 and mo0-1 each select SVSHAPE0-3 to apply to a given register.
528 mi0-2 apply to RA, RB, RC respectively, as input registers, and
529 likewise mo0-1 apply to output registers (RT/FRT, RS/FRS) respectively.
530 SVme is 5 bits (one for each of mi0-2/mo0-1) and indicates whether the
531 SVSHAPE is actively applied or not.
533 * bit 0 of SVme indicates if mi0 is applied to RA / FRA
534 * bit 1 of SVme indicates if mi1 is applied to RB / FRB
535 * bit 2 of SVme indicates if mi2 is applied to RC / FRC
536 * bit 3 of SVme indicates if mo0 is applied to RT / FRT
537 * bit 4 of SVme indicates if mo1 is applied to Effective Address / FRS / RS
538 (LD/ST-with-update has an implicit 2nd write register, RA)
540 # svremap instruction <a name="svremap"> </a>
544 svremap SVme,mi0,mi1,mi2,mo0,mo2,pst
546 |0 |6 |11 |13 |15 |17 |19 |21 | 22.25 |26..31 |
547 | -- | -- | -- | -- | -- | -- | -- | -- | ---- | ----- |
548 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | pst | rsvd | XO |
552 * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
556 # registers RA RB RC RT EA/FRS SVSHAPE0-3 indices
557 SVSTATE[32:33] <- mi0
558 SVSTATE[34:35] <- mi1
559 SVSTATE[36:37] <- mi2
560 SVSTATE[38:39] <- mo0
561 SVSTATE[40:41] <- mo1
562 # enable bit for RA RB RC RT EA/FRS
563 SVSTATE[42:46] <- SVme
564 # persistence bit (applies to more than one instruction)
567 Special Registers Altered:
571 `svremap` determines the relationship between registers and SVSHAPE SPRs.
572 The bitmask `SVme` determines which registers have a REMAP applied, and mi0-mo1
573 determine which shape is applied to an activated register. the `pst` bit if
574 cleared indicated that the REMAP operation shall only apply to the immediately-following
575 instruction. If set then REMAP remains permanently enabled until such time as it is
576 explicitly disabled, either by `setvl` setting a new MAXVL, or with another
577 `svremap` instruction. `svindex` and `svshape2` are also capable of setting or
578 clearing persistence, as well as partially covering a subset of the capability of
579 `svremap` to set register-to-SVSHAPE relationships.
585 # SHAPE Remapping SPRs
587 There are four "shape" SPRs, SHAPE0-3, 32-bits in each,
588 which have the same format.
590 Shape is 32-bits. When SHAPE is set entirely to zeros, remapping is
591 disabled: the register's elements are a linear (1D) vector.
593 |31.30|29..28 |27..24| 23..21 | 20..18 | 17..12 |11..6 |5..0 | Mode |
594 |---- |------ |------| ------ | ------- | ------- |----- |----- | ----- |
595 |0b00 |skip |offset| invxyz | permute | zdimsz |ydimsz|xdimsz|Matrix |
596 |0b00 |elwidth|offset|sk1/invxy|0b110/0b111|SVGPR|ydimsz|xdimsz|Indexed|
597 |0b01 |submode|offset| invxyz | submode2| zdimsz |mode |xdimsz|DCT/FFT|
598 |0b10 |submode|offset| invxyz | rsvd | rsvd |rsvd |xdimsz|Preduce|
599 |0b11 | | | | | | | |rsvd |
601 mode sets different behaviours (straight matrix multiply, FFT, DCT).
603 * **mode=0b00** sets straight Matrix Mode
604 * **mode=0b00** with permute=0b110 or 0b111 sets Indexed Mode
605 * **mode=0b01** sets "FFT/DCT" mode and activates submodes
606 * **mode=0b10** sets "Parallel Reduction" Schedules.
608 ## Parallel Reduction Mode
610 Creates the Schedules for Parallel Tree Reduction.
612 * **submode=0b00** selects the left operand index
613 * **submode=0b01** selects the right operand index
615 * When bit 0 of `invxyz` is set, the order of the indices
616 in the inner for-loop are reversed. This has the side-effect
617 of placing the final reduced result in the last-predicated element.
618 It also has the indirect side-effect of swapping the source
619 registers: Left-operand index numbers will always exceed
620 Right-operand indices.
621 When clear, the reduced result will be in the first-predicated
622 element, and Left-operand indices will always be *less* than
624 * When bit 1 of `invxyz` is set, the order of the outer loop
625 step is inverted: stepping begins at the nearest power-of two
626 to half of the vector length and reduces by half each time.
627 When clear the step will begin at 2 and double on each
632 submode2=0 is for FFT. For FFT submode the following schedules may be
635 * **submode=0b00** selects the ``j`` offset of the innermost for-loop
637 * **submode=0b10** selects the ``j+halfsize`` offset of the innermost for-loop
639 * **submode=0b11** selects the ``k`` of exptable (which coefficient)
641 When submode2 is 1 or 2, for DCT inner butterfly submode the following
642 schedules may be selected. When submode2 is 1, additional bit-reversing
645 * **submode=0b00** selects the ``j`` offset of the innermost for-loop,
647 * **submode=0b010** selects the ``j+halfsize`` offset of the innermost for-loop,
648 in reverse-order, in-place
649 * **submode=0b10** selects the ``ci`` count of the innermost for-loop,
650 useful for calculating the cosine coefficient
651 * **submode=0b11** selects the ``size`` offset of the outermost for-loop,
652 useful for the cosine coefficient ``cos(ci + 0.5) * pi / size``
654 When submode2 is 3 or 4, for DCT outer butterfly submode the following
655 schedules may be selected. When submode is 3, additional bit-reversing
658 * **submode=0b00** selects the ``j`` offset of the innermost for-loop,
659 * **submode=0b01** selects the ``j+1`` offset of the innermost for-loop,
661 `zdimsz` is used as an in-place "Stride", particularly useful for
662 column-based in-place DCT/FFT.
666 In Matrix Mode, skip allows dimensions to be skipped from being included
667 in the resultant output index. this allows sequences to be repeated:
668 ```0 0 0 1 1 1 2 2 2 ...``` or in the case of skip=0b11 this results in
669 modulo ```0 1 2 0 1 2 ...```
671 * **skip=0b00** indicates no dimensions to be skipped
672 * **skip=0b01** sets "skip 1st dimension"
673 * **skip=0b10** sets "skip 2nd dimension"
674 * **skip=0b11** sets "skip 3rd dimension"
676 invxyz will invert the start index of each of x, y or z. If invxyz[0] is
677 zero then x-dimensional counting begins from 0 and increments, otherwise
678 it begins from xdimsz-1 and iterates down to zero. Likewise for y and z.
680 offset will have the effect of offsetting the result by ```offset``` elements:
683 GPR(RT + remap(i) + SVSHAPE.offset) = ....
685 this appears redundant because the register RT could simply be changed by a compiler, until element width overrides are introduced. also
686 bear in mind that unlike a static compiler SVSHAPE.offset may
687 be set dynamically at runtime.
689 xdimsz, ydimsz and zdimsz are offset by 1, such that a value of 0 indicates
690 that the array dimensionality for that dimension is 1. any dimension
691 not intended to be used must have its value set to 0 (dimensionality
692 of 1). A value of xdimsz=2 would indicate that in the first dimension
693 there are 3 elements in the array. For example, to create a 2D array
694 X,Y of dimensionality X=3 and Y=2, set xdimsz=2, ydimsz=1 and zdimsz=0
696 The format of the array is therefore as follows:
698 array[xdimsz+1][ydimsz+1][zdimsz+1]
700 However whilst illustrative of the dimensionality, that does not take the
701 "permute" setting into account. "permute" may be any one of six values
702 (0-5, with values of 6 and 7 indicating "Indexed" Mode). The table
703 below shows how the permutation dimensionality order works:
705 | permute | order | array format |
706 | ------- | ----- | ------------------------ |
707 | 000 | 0,1,2 | (xdim+1)(ydim+1)(zdim+1) |
708 | 001 | 0,2,1 | (xdim+1)(zdim+1)(ydim+1) |
709 | 010 | 1,0,2 | (ydim+1)(xdim+1)(zdim+1) |
710 | 011 | 1,2,0 | (ydim+1)(zdim+1)(xdim+1) |
711 | 100 | 2,0,1 | (zdim+1)(xdim+1)(ydim+1) |
712 | 101 | 2,1,0 | (zdim+1)(ydim+1)(xdim+1) |
713 | 110 | 0,1 | Indexed (xdim+1)(ydim+1) |
714 | 111 | 1,0 | Indexed (ydim+1)(xdim+1) |
716 In other words, the "permute" option changes the order in which
717 nested for-loops over the array would be done. See executable
718 python reference code for further details.
720 *Note: permute=0b110 and permute=0b111 enable Indexed REMAP Mode,
723 With all these options it is possible to support in-place transpose,
724 in-place rotate, Matrix Multiply and Convolutions, without being
725 limited to Power-of-Two dimension sizes.
729 Indexed Mode activates reading of the element indices from the GPR
730 and includes optional limited 2D reordering.
731 In its simplest form (without elwidth overrides or other modes):
735 return GPR((SVSHAPE.SVGPR<<1)+i) + SVSHAPE.offset
738 element_result = ....
739 GPR(RT + indexed_remap(i)) = element_result
742 With element-width overrides included, and using the pseudocode
743 from the SVP64 [[sv/svp64/appendix#elwidth]] elwidth section
748 svreg = SVSHAPE.SVGPR << 1
749 srcwid = elwid_to_bitwidth(SVSHAPE.elwid)
750 offs = SVSHAPE.offset
751 return get_polymorphed_reg(svreg, srcwid, i) + offs
754 element_result = ....
755 rt_idx = indexed_remap(i)
756 set_polymorphed_reg(RT, destwid, rt_idx, element_result)
759 Matrix-style reordering still applies to the indices, except limited
760 to up to 2 Dimensions (X,Y). Ordering is therefore limited to (X,Y) or
761 (Y,X) for in-place Transposition.
762 Only one dimension may optionally be skipped. Inversion of either
763 X or Y or both is possible (2D mirroring). Pseudocode for Indexed Mode (including elwidth
764 overrides) may be written in terms of Matrix Mode, specifically
765 purposed to ensure that the 3rd dimension (Z) has no effect:
768 def index_remap(ISHAPE, i):
769 MSHAPE.skip = 0b0 || ISHAPE.sk1
770 MSHAPE.invxyz = 0b0 || ISHAPE.invxy
771 MSHAPE.xdimsz = ISHAPE.xdimsz
772 MSHAPE.ydimsz = ISHAPE.ydimsz
773 MSHAPE.zdimsz = 0 # disabled
774 if ISHAPE.permute = 0b110 # 0,1
775 MSHAPE.permute = 0b000 # 0,1,2
776 if ISHAPE.permute = 0b111 # 1,0
777 MSHAPE.permute = 0b010 # 1,0,2
778 el_idx = remap_matrix(MSHAPE, i)
779 svreg = ISHAPE.SVGPR << 1
780 srcwid = elwid_to_bitwidth(ISHAPE.elwid)
782 return get_polymorphed_reg(svreg, srcwid, el_idx) + offs
785 The most important observation above is that the Matrix-style
786 remapping occurs first and the Index lookup second. Thus it
787 becomes possible to perform in-place Transpose of Indices which
788 may have been costly to set up or costly to duplicate
789 (waste register file space).
795 # svshape instruction <a name="svshape"> </a>
797 Form: SVM-Form SV "Matrix" Form (see [[isatables/fields.text]])
799 svshape SVxd,SVyd,SVzd,SVRM,vf
801 | 0.5|6.10 |11.15 |16..20 | 21..24 | 25 | 26..31| name |
802 | -- | -- | --- | ----- | ------ | -- | ------| -------- |
803 |OPCD| SVxd | SVyd | SVzd | SVRM | vf | XO | svshape |
806 # for convenience, VL to be calculated and stored in SVSTATE
808 mscale[0:5] <- 0b000001 # for scaling MAXVL
809 itercount[0:6] <- [0] * 7
810 SVSTATE[0:31] <- [0] * 32
811 # only overwrite REMAP if "persistence" is zero
812 if (SVSTATE[62] = 0b0) then
813 SVSTATE[32:33] <- 0b00
814 SVSTATE[34:35] <- 0b00
815 SVSTATE[36:37] <- 0b00
816 SVSTATE[38:39] <- 0b00
817 SVSTATE[40:41] <- 0b00
818 SVSTATE[42:46] <- 0b00000
821 # clear out all SVSHAPEs
822 SVSHAPE0[0:31] <- [0] * 32
823 SVSHAPE1[0:31] <- [0] * 32
824 SVSHAPE2[0:31] <- [0] * 32
825 SVSHAPE3[0:31] <- [0] * 32
827 # set schedule up for multiply
828 if (SVrm = 0b0000) then
829 # VL in Matrix Multiply is xd*yd*zd
830 xd <- (0b00 || SVxd) + 1
831 yd <- (0b00 || SVyd) + 1
832 zd <- (0b00 || SVzd) + 1
834 vlen[0:6] <- n[14:20]
835 # set up template in SVSHAPE0, then copy to 1-3
836 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
837 SVSHAPE0[6:11] <- (0b0 || SVyd) # ydim
838 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim
839 SVSHAPE0[28:29] <- 0b11 # skip z
841 SVSHAPE1[0:31] <- SVSHAPE0[0:31]
842 SVSHAPE2[0:31] <- SVSHAPE0[0:31]
843 SVSHAPE3[0:31] <- SVSHAPE0[0:31]
845 SVSHAPE1[18:20] <- 0b001 # permute x,z,y
846 SVSHAPE1[28:29] <- 0b01 # skip z
848 SVSHAPE2[18:20] <- 0b001 # permute x,z,y
849 SVSHAPE2[28:29] <- 0b11 # skip y
851 # set schedule up for FFT butterfly
852 if (SVrm = 0b0001) then
853 # calculate O(N log2 N)
856 if SVxd[4-n] = 0 then
859 n <- ((0b0 || SVxd) + 1) * n
861 # set up template in SVSHAPE0, then copy to 1-3
863 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
864 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D FFT)
865 mscale <- (0b0 || SVzd) + 1
866 SVSHAPE0[30:31] <- 0b01 # Butterfly mode
868 SVSHAPE1[0:31] <- SVSHAPE0[0:31]
869 SVSHAPE2[0:31] <- SVSHAPE0[0:31]
871 SVSHAPE1[28:29] <- 0b01 # j+halfstep schedule
873 SVSHAPE2[28:29] <- 0b10 # k schedule
875 # set schedule up for (i)DCT Inner butterfly
876 # SVrm Mode 2 (Mode 6 for iDCT) is for pre-calculated coefficients,
877 # SVrm Mode 4 (Mode 12 for iDCT) is for on-the-fly (Vertical-First Mode)
878 if ((SVrm = 0b0010) | (SVrm = 0b0100) |
879 (SVrm = 0b1010) | (SVrm = 0b1100)) then
880 # calculate O(N log2 N)
883 if SVxd[4-n] = 0 then
886 n <- ((0b0 || SVxd) + 1) * n
888 # set up template in SVSHAPE0, then copy to 1-3
890 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
891 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D DCT)
892 mscale <- (0b0 || SVzd) + 1
893 if (SVrm = 0b1011) then
894 SVSHAPE0[30:31] <- 0b11 # iDCT mode
895 SVSHAPE0[18:20] <- 0b011 # iDCT Outer Butterfly sub-mode
896 SVSHAPE0[21:23] <- 0b101 # "inverse" on outer and inner loop
898 SVSHAPE0[30:31] <- 0b01 # DCT mode
899 SVSHAPE0[18:20] <- 0b100 # DCT Outer Butterfly sub-mode
900 SVSHAPE0[6:11] <- 0b000010 # DCT Butterfly mode
902 SVSHAPE1[0:31] <- SVSHAPE0[0:31] # j+halfstep schedule
903 SVSHAPE2[0:31] <- SVSHAPE0[0:31] # costable coefficients
905 SVSHAPE1[28:29] <- 0b01 # j+halfstep schedule
906 # reset costable "striding" to 1
907 SVSHAPE2[12:17] <- 0b000000
909 # set schedule up for DCT COS table generation
910 if (SVrm = 0b0101) | (SVrm = 0b1101) then
911 # calculate O(N log2 N)
913 itercount[0:6] <- (0b00 || SVxd) + 0b0000001
914 itercount[0:6] <- (0b0 || itercount[0:5])
917 if SVxd[4-n] = 0 then
920 vlen[0:6] <- vlen + itercount
921 itercount[0:6] <- (0b0 || itercount[0:5])
922 # set up template in SVSHAPE0, then copy to 1-3
924 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
925 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D DCT)
926 mscale <- (0b0 || SVzd) + 1
927 SVSHAPE0[30:31] <- 0b01 # DCT/FFT mode
928 SVSHAPE0[6:11] <- 0b000100 # DCT Inner Butterfly COS-gen mode
929 if (SVrm = 0b0101) then
930 SVSHAPE0[21:23] <- 0b001 # "inverse" on outer loop for DCT
932 SVSHAPE1[0:31] <- SVSHAPE0[0:31]
933 SVSHAPE2[0:31] <- SVSHAPE0[0:31]
934 # for cos coefficient
935 SVSHAPE1[28:29] <- 0b10 # ci schedule
936 SVSHAPE2[28:29] <- 0b11 # size schedule
938 # set schedule up for iDCT / DCT inverse of half-swapped ordering
939 if (SVrm = 0b0110) | (SVrm = 0b1110) | (SVrm = 0b1111) then
940 vlen[0:6] <- (0b00 || SVxd) + 0b0000001
941 # set up template in SVSHAPE0
942 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
943 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D DCT)
944 mscale <- (0b0 || SVzd) + 1
945 if (SVrm = 0b1110) then
946 SVSHAPE0[18:20] <- 0b001 # DCT opposite half-swap
947 if (SVrm = 0b1111) then
948 SVSHAPE0[30:31] <- 0b01 # FFT mode
950 SVSHAPE0[30:31] <- 0b11 # DCT mode
951 SVSHAPE0[6:11] <- 0b000101 # DCT "half-swap" mode
953 # set schedule up for parallel reduction
954 if (SVrm = 0b0111) then
955 # calculate the total number of operations (brute-force)
957 itercount[0:6] <- (0b00 || SVxd) + 0b0000001
958 step[0:6] <- 0b0000001
960 do while step <u itercount
961 newstep <- step[1:6] || 0b0
963 do while (j+step <u itercount)
967 # VL in Parallel-Reduce is the number of operations
969 # set up template in SVSHAPE0, then copy to 1. only 2 needed
970 SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
971 SVSHAPE0[12:17] <- (0b0 || SVzd) # zdim - "striding" (2D DCT)
972 mscale <- (0b0 || SVzd) + 1
973 SVSHAPE0[30:31] <- 0b10 # parallel reduce submode
975 SVSHAPE1[0:31] <- SVSHAPE0[0:31]
976 # set up right operand (left operand 28:29 is zero)
977 SVSHAPE1[28:29] <- 0b01 # right operand
979 # set VL, MVL and Vertical-First
980 m[0:12] <- vlen * mscale
981 maxvl[0:6] <- m[6:12]
982 SVSTATE[0:6] <- maxvl # MAVXL
983 SVSTATE[7:13] <- vlen # VL
987 Special Registers Altered:
991 `svshape` is a convenience instruction that reduces instruction
992 count for common usage patterns, particularly Matrix, DCT and FFT. It sets up
993 (overwrites) all required SVSHAPE SPRs and also modifies SVSTATE
994 including VL and MAXVL. Using `svshape` therefore does not also
999 * **SVxd** - SV REMAP "xdim"
1000 * **SVyd** - SV REMAP "ydim"
1001 * **SVzd** - SV REMAP "zdim"
1002 * **SVRM** - SV REMAP Mode (0b00000 for Matrix, 0b00001 for FFT etc.)
1003 * **vf** - sets "Vertical-First" mode
1005 *Note: SVxd, SVyz and SVzd are all stored "off-by-one". In the assembler
1006 mnemonic the values `1-32` are stored in binary as `0b00000..0b11111`*
1008 There are 14 REMAP Modes (2 bits are RESERVED for `svshape2`)
1010 | SVRM | Remap Mode description |
1012 | 0b0000 | Matrix 1/2/3D |
1013 | 0b0001 | FFT Butterfly |
1014 | 0b0010 | DCT Inner butterfly, pre-calculated coefficients |
1015 | 0b0011 | DCT Outer butterfly |
1016 | 0b0100 | DCT Inner butterfly, on-the-fly (Vertical-First Mode) |
1017 | 0b0101 | DCT COS table index generation |
1018 | 0b0110 | DCT half-swap |
1019 | 0b0111 | Parallel Reduction |
1020 | 0b1000 | reserved for svshape2 |
1021 | 0b1001 | reserved for svshape2 |
1022 | 0b1010 | iDCT Inner butterfly, pre-calculated coefficients |
1023 | 0b1011 | iDCT Outer butterfly |
1024 | 0b1100 | iDCT Inner butterfly, on-the-fly (Vertical-First Mode) |
1025 | 0b1101 | iDCT COS table index generation |
1026 | 0b1110 | iDCT half-swap |
1027 | 0b1111 | FFT half-swap |
1029 Examples showing how all of these Modes operate exists in the online
1030 [SVP64 unit tests](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD). Explaining
1031 these Modes further in detail is beyond the scope of this document.
1033 In Indexed Mode, there are only 5 bits available to specify the GPR
1034 to use, out of 128 GPRs (7 bit numbering). Therefore, only the top
1035 5 bits are given in the `SVxd` field: the bottom two implicit bits
1036 will be zero (`SVxd || 0b00`).
1038 `svshape` has *limited applicability* due to being a 32-bit instruction.
1039 The full capability of SVSHAPE SPRs may be accessed by directly writing
1040 to SVSHAPE0-3 with `mtspr`. Circumstances include Matrices with dimensions
1041 larger than 32, and in-place Transpose. Potentially a future v3.1 Prefixed
1042 instruction, `psvshape`, may extend the capability here.
1049 # svindex instruction <a name="svindex"> </a>
1053 | 0.5|6.10 |11.15 |16.20 | 21..25 | 26..31| name | Form |
1054 | -- | -- | --- | ---- | ----------- | ------| -------- | ---- |
1055 |OPCD| SVG | rmm | SVd | ew/yx/mm/sk | XO | svindex | SVI-Form |
1057 * svindex SVG,rmm,SVd,ew,SVyx,mm,sk
1061 # based on nearest MAXVL compute other dimension
1065 do while d*dim <u ([0]*4 || MVL)
1068 # set up template, then copy once location identified
1070 shape[30:31] <- 0b00 # mode
1072 shape[18:20] <- 0b110 # indexed xd/yd
1073 shape[0:5] <- (0b0 || SVd) # xdim
1074 if sk = 0 then shape[6:11] <- 0 # ydim
1075 else shape[6:11] <- 0b111111 # ydim max
1077 shape[18:20] <- 0b111 # indexed yd/xd
1078 if sk = 1 then shape[6:11] <- 0 # ydim
1079 else shape[6:11] <- d-1 # ydim max
1080 shape[0:5] <- (0b0 || SVd) # ydim
1081 shape[12:17] <- (0b0 || SVG) # SVGPR
1082 shape[28:29] <- ew # element-width override
1083 shape[21] <- sk # skip 1st dimension
1085 # select the mode for updating SVSHAPEs
1086 SVSTATE[62] <- mm # set or clear persistence
1088 # clear out all SVSHAPEs first
1089 SVSHAPE0[0:31] <- [0] * 32
1090 SVSHAPE1[0:31] <- [0] * 32
1091 SVSHAPE2[0:31] <- [0] * 32
1092 SVSHAPE3[0:31] <- [0] * 32
1093 SVSTATE[32:41] <- [0] * 10 # clear REMAP.mi/o
1094 SVSTATE[42:46] <- rmm # rmm exactly REMAP.SVme
1098 # activate requested shape
1099 if idx = 0 then SVSHAPE0 <- shape
1100 if idx = 1 then SVSHAPE1 <- shape
1101 if idx = 2 then SVSHAPE2 <- shape
1102 if idx = 3 then SVSHAPE3 <- shape
1103 SVSTATE[bit*2+32:bit*2+33] <- idx
1104 # increment shape index, modulo 4
1105 if idx = 3 then idx <- 0
1108 # refined SVSHAPE/REMAP update mode
1111 if idx = 0 then SVSHAPE0 <- shape
1112 if idx = 1 then SVSHAPE1 <- shape
1113 if idx = 2 then SVSHAPE2 <- shape
1114 if idx = 3 then SVSHAPE3 <- shape
1115 SVSTATE[bit*2+32:bit*2+33] <- idx
1116 SVSTATE[46-bit] <- 1
1118 Special Registers Altered:
1122 `svindex` is a convenience instruction that reduces instruction
1123 count for Indexed REMAP Mode. It sets up
1124 (overwrites) all required SVSHAPE SPRs and can modify the REMAP
1125 area of the SVSTATE SPR as well. The relevant SPRs *may* be directly programmed with
1126 `mtspr` however it is laborious to do so: svindex saves instructions
1127 covering much of Indexed REMAP capability.
1131 * **SVd** - SV REMAP x/y dim
1132 * **rmm** - REMAP mask: sets remap mi0-2/mo0-1 and SVSHAPEs,
1134 * **ew** - sets element width override on the Indices
1135 * **SVG** - GPR SVG<<2 to be used for Indexing
1136 * **yx** - 2D reordering to be used if yx=1
1137 * **mm** - mask mode. determines how `rmm` is interpreted.
1138 * **sk** - Dimension skipping enabled
1140 *Note: SVd, like SVxd, SVyz and SVzd of `svshape`, are all stored
1141 "off-by-one". In the assembler
1142 mnemonic the values `1-32` are stored in binary as `0b00000..0b11111`*.
1144 *Note: when `yx=1,sk=0` the second dimension is calculated as
1149 * `rmm`, like REMAP.SVme, has bit 0
1150 correspond to mi0, bit 1 to mi1, bit 2 to mi2,
1151 bit 3 to mo0 and bit 4 to mi1
1152 * all SVSHAPEs and the REMAP parts of SVSHAPE are first reset (initialised to zero)
1153 * for each bit set in the 5-bit `rmm`, in order, the first
1154 as-yet-unset SVSHAPE will be updated
1155 with the other operands in the instruction, and the REMAP
1157 * If all 5 bits of `rmm` are set then both mi0 and mo1 use SVSHAPE0.
1158 * SVSTATE persistence bit is cleared
1159 * No other alterations to SVSTATE are carried out
1161 Example 1: if rmm=0b00110 then SVSHAPE0 and SVSHAPE1 are set up,
1162 and the REMAP SPR set so that mi1 uses SVSHAPE0 and mi2
1163 uses mi2. REMAP.SVme is also set to 0b00110, REMAP.mi1=0
1164 (SVSHAPE0) and REMAP.mi2=1 (SVSHAPE1)
1166 Example 2: if rmm=0b10001 then again SVSHAPE0 and SVSHAPE1
1167 are set up, but the REMAP SPR is set so that mi0 uses SVSHAPE0
1168 and mo1 uses SVSHAPE1. REMAP.SVme=0b10001, REMAP.mi0=0, REMAP.mo1=1
1170 Rough algorithmic form:
1172 marray = [mi0, mi1, mi2, mo0, mo1]
1175 if not rmm[bit]: continue
1177 SVSTATE{marray[bit]} = idx
1178 idx = (idx+1) modulo 4
1182 * bits 0-2 (MSB0 numbering) of `rmm` indicate an index selecting mi0-mo1
1183 * bits 3-4 (MSB0 numbering) of `rmm` indicate which SVSHAPE 0-3 shall
1185 * only the selected SVSHAPE is overwritten
1186 * only the relevant bits in the REMAP area of SVSTATE are updated
1187 * REMAP persistence bit is set.
1189 Example 1: if `rmm`=0b01110 then bits 0-2 (MSB0) are 0b011 and
1190 bits 3-4 are 0b10. thus, mo0 is selected and SVSHAPE2
1191 to be updated. REMAP.SVme[3] will be set high and REMAP.mo0
1192 set to 2 (SVSHAPE2).
1194 Example 2: if `rmm`=0b10011 then bits 0-2 (MSB0) are 0b100 and
1195 bits 3-4 are 0b11. thus, mo1 is selected and SVSHAPE3
1196 to be updated. REMAP.SVme[4] will be set high and REMAP.mo1
1197 set to 3 (SVSHAPE3).
1199 Rough algorithmic form:
1201 marray = [mi0, mi1, mi2, mo0, mo1]
1205 SVSTATE{marray[bit]} = idx
1208 In essence, `mm=0` is intended for use to set as much of the
1209 REMAP State SPRs as practical with a single instruction,
1210 whilst `mm=1` is intended to be a little more refined.
1212 **Usage guidelines**
1214 * **Disable 2D mapping**: to only perform Indexing without
1215 reordering use `SVd=1,sk=0,yx=0` (or set SVd to a value larger
1217 * **Modulo 1D mapping**: to perform Indexing cycling through the
1218 first N Indices use `SVd=N,sk=0,yx=0` where `VL>N`. There is
1219 no requirement to set VL equal to a multiple of N.
1220 * **Modulo 2D transposed**: `SVd=M,sk=0,yx=1`, sets
1221 `xdim=M,ydim=CEIL(MAXVL/M)`.
1223 Beyond these mappings it becomes necessary to write directly to
1224 the SVSTATE SPRs manually.
1231 # svshape2 (offset) <a name="svshape2"> </a>
1233 `svshape2` is an additional convenience instruction that prioritises
1234 setting `SVSHAPE.offset`. Its primary purpose is for use when
1235 element-width overrides are used. It has identical capabilities to `svindex` and
1236 in terms of both options (skip, etc.) and ability to activate REMAP
1237 (rmm, mask mode) but unlike `svindex` it does not set GPR REMAP,
1238 only a 1D or 2D `svshape`, and
1239 unlike `svshape` it can set an arbirrary `SVSHAPE.offset` immediate.
1241 One of the limitations of Simple-V is that Vector elements start on the boundary
1242 of the Scalar regfile, which is fine when element-width overrides are not
1243 needed. If the starting point of a Vector with smaller elwidths must begin
1244 in the middle of a register, normally there would be no way to do so except
1245 through LD/ST. `SVSHAPE.offset` caters for this scenario and `svshape2`is
1248 svshape2 offs,yx,rmm,SVd,sk,mm
1250 | 0.5|6..9|10|11.15 |16..20 | 21..25 | 25 | 26..31| name |
1251 | -- |----|--| --- | ----- | ------ | -- | ------| -------- |
1252 |OPCD|offs|yx| rmm | SVd | 100/mm | sk | XO | svshape |
1254 * **offs** (4 bits) - unsigned offset
1255 * **yx** (1 bit) - swap XY to YX
1256 * **SVd** dimension size
1257 * **rmm** REMAP mask
1259 * **sk** (1 bit) skips 1st dimension if set
1261 Dimensions are calculated exactly as `svindex`. `rmm` and
1262 `mm` are as per `svindex`.
1264 *Programmer's Note: offsets for `svshape2` may be specified in the range
1265 0-15. Given that the principle of Simple-V is to fit on top of
1266 byte-addressable register files and that GPR and FPR are 64-bit (8 bytes)
1267 it should be clear that the offset may, when `elwidth=8`, begin an
1268 element-level operation starting element zero at any arbitrary byte.
1269 On cursory examination attempting to go beyond the range 0-7 seems
1270 unnecessary given that the **next GPR or FPR** is an
1271 alias for an offset in the range 8-15. Thus by simply increasing
1272 the starting Vector point of the operation to the next register it
1273 can be seen that the offset of 0-7 would be sufficient. Unfortunately
1274 however some operations are EXTRA2-encoded it is **not possible**
1275 to increase the GPR/FPR register number by one, because EXTRA2-encoding
1276 of GPR/FPR Vector numbers are restricted to even numbering.
1277 For CR Fields the EXTRA2 encoding is even more sparse.
1278 The additional offset range (8-15) helps overcome these limitations.*
1280 *Hardware Implementor's note: with the offsets only being immediates
1281 and with register numbering being entirely immediate as well it is
1282 possible to correctly compute Register Hazards without requiring
1283 reading the contents of any SPRs. If however there are
1284 instructions that have directly written to the SVSTATE or SVSHAPE
1285 SPRs and those instructions are still in-flight then this position
1286 is clearly **invalid**.*
1298 Add the following to Book I, 1.6.1, SVI-Form
1301 |0 |6 |11 |16 |21 |23 |24|25|26 31|
1302 | PO | SVG|rmm | SVd |ew |SVyx|mm|sk| XO |
1305 Add the following to Book I, 1.6.1, SVM-Form
1308 |0 |6 |11 |16 |21 |25 |26 |31 |
1309 | PO | SVxd | SVyd | SVzd | SVrm |vf | XO |
1312 Add the following to Book I, 1.6.1, SVM2-Form
1315 |0 |6 |10 |11 |16 |21 |24|25 |26 |31 |
1316 | PO | SVo |SVyx| rmm | SVd |XO |mm|sk | XO |
1319 Add the following to Book I, 1.6.1, SVRM-Form
1322 |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 |
1323 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO |
1326 * Add `SVI, SVM, SVM2, SVRM` to `XO (26:31)` Field in Book I, 1.6.2
1328 Add the following to Book I, 1.6.2
1332 Field used in REMAP to select the SVSHAPE for 1st input register
1335 Field used in REMAP to select the SVSHAPE for 2nd input register
1338 Field used in REMAP to select the SVSHAPE for 3rd input register
1341 Field used to specify the meaning of the rmm field for SVI-Form
1345 Field used in REMAP to select the SVSHAPE for 1st output register
1348 Field used in REMAP to select the SVSHAPE for 2nd output register
1351 Field used in REMAP to indicate "persistence" mode (REMAP
1352 continues to apply to multiple instructions)
1355 REMAP Mode field for SVI-Form and SVM2-Form
1358 Field used to specify dimensional skipping in svindex
1361 Immediate field used to specify the size of the REMAP dimension
1362 in the svindex and svshape2 instructions
1365 Immediate field used to specify a 9-bit signed
1366 two's complement integer which is concatenated
1367 on the right with 0b00 and sign-extended to 64 bits.
1370 Field used to specify a GPR to be used as a
1371 source for indexing.
1374 Simple-V immediate field for setting VL or MVL
1377 Simple-V "REMAP" map-enable bits (0-4)
1380 Field used by the svshape2 instruction as an offset
1383 Simple-V "REMAP" Mode
1386 Simple-V "REMAP" x-dimension size
1389 Simple-V "REMAP" y-dimension size
1392 Simple-V "REMAP" z-dimension size
1398 Appendix E Power ISA sorted by opcode
1399 Appendix F Power ISA sorted by version
1400 Appendix G Power ISA sorted by Compliancy Subset
1401 Appendix H Power ISA sorted by mnemonic
1403 | Form | Book | Page | Version | mnemonic | Description |
1404 |------|------|------|---------|----------|-------------|
1405 | SVRM | I | # | 3.0B | svremap | REMAP enabling instruction |