1 # RFC ls009 SVP64 REMAP instructions
5 * <https://libre-soc.org/openpower/sv/>
6 * <https://libre-soc.org/openpower/sv/rfc/ls009/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1042>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
20 **Books and Section affected**:
23 Book I, new Zero-Overhead-Loop Chapter.
24 Appendix E Power ISA sorted by opcode
25 Appendix F Power ISA sorted by version
26 Appendix G Power ISA sorted by Compliancy Subset
27 Appendix H Power ISA sorted by mnemonic
33 svremap - Re-Mapping of Register Element Offsets
34 svindex - General-purpose setting of SHAPEs to be re-mapped
35 svshape - Hardware-level setting of SHAPEs for element re-mapping
36 svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
39 **Submitter**: Luke Leighton (Libre-SOC)
41 **Requester**: Libre-SOC
43 **Impact on processor**:
46 Addition of four new "Zero-Overhead-Loop-Control" DSP-style Vector-style
47 Management Instructions which provide advanced features such as Matrix
48 FFT DCT Hardware-Assist Schedules and general-purpose Index reordering.
51 **Impact on software**:
54 Requires support for new instructions in assembler, debuggers,
61 Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
62 Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
63 Digital Signal Processing (DSP)
68 These REMAP Management instructions provide state-of-the-art advanced capabilities
69 to dramatically decrease instruction count and power reduction whilst retaining
70 unprecedented general-purpose capability and a standard Sequential Execution Model.
72 **Notes and Observations**:
78 Add the following entries to:
80 * the Appendices of Book I
81 * Instructions of Book I as a new Section
82 * TODO-Form of Book I Section 1.6.1.6 and 1.6.2
91 # REMAP <a name="remap" />
93 REMAP is an advanced form of Vector "Structure Packing" that
94 provides hardware-level support for commonly-used *nested* loop patterns.
95 For more general reordering an Indexed REMAP mode is available.
97 REMAP allows the usual vector loop `0..VL-1` to be "reshaped" (re-mapped)
98 from a linear form to a 2D or 3D transposed form, or "offset" to permit
99 arbitrary access to elements (when elwidth overrides are used),
100 independently on each Vector src or dest
101 register. Aside from Indexed REMAP this is entirely Hardware-accelerated
102 reordering and consequently not costly in terms of register access. It
103 will however place a burden on Multi-Issue systems but no more than if -
104 exactly as if - the equivalent Scalar instructions were explicitly
105 loop-unrolled without SVP64.
107 The initial primary motivation of REMAP was for Matrix Multiplication, reordering of sequential
108 data in-place: in-place DCT and FFT were easily justified given the
109 high usage in Computer Science.
110 Four SPRs are provided which may be applied to any GPR, FPR or CR Field
111 so that for example a single FMAC may be
112 used in a single loop to perform 5x3 times 3x4 Matrix multiplication,
113 generating 60 FMACs *without needing explicit assembler unrolling*.
114 Additional uses include regular "Structure Packing"
115 such as RGB pixel data extraction and reforming.
117 REMAP, like all of SV, is abstracted out, meaning that unlike traditional
118 Vector ISAs which would typically only have a limited set of instructions
119 that can be structure-packed (LD/ST typically), REMAP may be applied to
120 literally any instruction: CRs, Arithmetic, Logical, LD/ST, anything.
122 Note that REMAP does not *directly* apply to sub-vector elements: that
123 is what swizzle is for. Swizzle *can* however be applied to the same
124 instruction as REMAP. As explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack EXTRA Mode bits
125 can extend down into Sub-vector elements to perform vec2/vec3/vec4
126 sequential reordering, but even here, REMAP is not extended down to
127 the actual sub-vector elements themselves.
129 In its general form, REMAP is quite expensive to set up, and on some
130 implementations may introduce
131 latency, so should realistically be used only where it is worthwhile.
132 Commonly-used patterns such as Matrix Multiply, DCT and FFT have
133 helper instruction options which make REMAP easier to use.
135 There are four types of REMAP:
137 * **Matrix**, also known as 2D and 3D reshaping, can perform in-place
138 Matrix transpose and rotate. The Shapes are set up for an "Outer Product"
140 * **FFT/DCT**, with full triple-loop in-place support: limited to
142 * **Indexing**, for any general-purpose reordering, also includes
143 limited 2D reshaping.
144 * **Parallel Reduction**, for scheduling a sequence of operations
145 in a Deterministic fashion, in a way that may be parallelised,
146 to reduce a Vector down to a single value.
148 Best implemented on top of a Multi-Issue Out-of-Order Micro-architecture,
149 REMAP Schedules are 100% Deterministic **including Indexing** and are
150 designed to be incorporated in between the Decode and Issue phases,
151 directly into Register Hazard Management.
153 Parallel Reduction is unusual in that it requires a full vector array
154 of results (not a scalar) and uses the rest of the result Vector for
155 the purposes of storing intermediary calculations. As these intermediary
156 results are Deterministically computed they may be useful.
157 Additionally, because the intermediate results are always written out
158 it is possible to service Precise Interrupts without affecting latency
159 (a common limitation of Vector ISAs implementing explicit
160 Parallel Reduction instructions).
164 * normal vector element read/write of operands would be sequential
166 * this is not appropriate for (e.g.) Matrix multiply which requires
167 accessing elements in alternative sequences (0 3 6 1 4 7 ...)
168 * normal Vector ISAs use either Indexed-MV or Indexed-LD/ST to "cope"
169 with this. both are expensive (copy large vectors, spill through memory)
170 and very few Packed SIMD ISAs cope with non-Power-2.
171 * REMAP **redefines** the order of access according to set
172 (Deterministic) "Schedules".
173 * The Schedules are not at all restricted to power-of-two boundaries
174 making it unnecessary to have for example specialised 3x4 transpose
175 instructions of other Vector ISAs.
177 Only the most commonly-used algorithms in computer science have REMAP
178 support, due to the high cost in both the ISA and in hardware. For
179 arbitrary remapping the `Indexed` REMAP may be used.
183 * `svshape` to set the type of reordering to be applied to an
184 otherwise usual `0..VL-1` hardware for-loop
185 * `svremap` to set which registers a given reordering is to apply to
187 * `sv.{instruction}` where any Vectorised register marked by `svremap`
188 will have its ordering REMAPPED according to the schedule set
191 The following illustrative example multiplies a 3x4 and a 5x3
196 svshape 5, 4, 3, 0, 0
197 svremap 15, 1, 2, 3, 0, 0, 0, 0
198 sv.fmadds *0, *8, *16, *0
201 * svshape sets up the four SVSHAPE SPRS for a Matrix Schedule
202 * svremap activates four out of five registers RA RB RC RT RS (15)
208 - RS Remapping to not be activated
209 * sv.fmadds has RT=0.v, RA=8.v, RB=16.v, RC=0.v
210 * With REMAP being active each register's element index is
211 *independently* transformed using the specified SHAPEs.
213 Thus the Vector Loop is arranged such that the use of
214 the multiply-and-accumulate instruction executes precisely the required
215 Schedule to perform an in-place in-registers Matrix Multiply with no
216 need to perform additional Transpose or register copy instructions.
217 The example above may be executed as a unit test and demo,
218 [here](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;h=c15479db9a36055166b6b023c7495f9ca3637333;hb=a17a252e474d5d5bf34026c25a19682e3f2015c3#l94)
222 This section summarises the motivation for each REMAP Schedule
223 and briefly goes over their characteristics and limitations.
224 Further details on the Deterministic Precise-Interruptible algorithms
225 used in these Schedules is found in the [[sv/remap/appendix]].
227 ## Matrix (1D/2D/3D shaping)
229 Matrix Multiplication is a huge part of High-Performance Compute,
231 In many PackedSIMD as well as Scalable Vector ISAs, non-power-of-two
232 Matrix sizes are a serious challenge. PackedSIMD ISAs, in order to
233 cope with for example 3x4 Matrices, recommend rolling data-repetition and loop-unrolling.
234 Aside from the cost of the load on the L1 I-Cache, the trick only
235 works if one of the dimensions X or Y are power-two. Prime Numbers
236 (5x7, 3x5) become deeply problematic to unroll.
238 Even traditional Scalable Vector ISAs have issues with Matrices, often
239 having to perform data Transpose by pushing out through Memory and back,
240 or computing Transposition Indices (costly) then copying to another
243 Matrix REMAP was thus designed to solve these issues by providing Hardware
245 "Schedules" that can view what would otherwise be limited to a strictly
246 linear Vector as instead being 2D (even 3D) *in-place* reordered.
247 With both Transposition and non-power-two being supported the issues
248 faced by other ISAs are mitigated.
250 Limitations of Matrix REMAP are that the Vector Length (VL) is currently
251 restricted to 127: up to 127 FMAs (or other operation)
252 may be performed in total.
253 Also given that it is in-registers only at present some care has to be
254 taken on regfile resource utilisation. However it is perfectly possible
255 to utilise Matrix REMAP to perform the three inner-most "kernel" loops of
256 the usual 6-level large Matrix Multiply, without the usual difficulties
257 associated with SIMD.
259 Also the `svshape` instruction only provides access to part of the
260 Matrix REMAP capability. Rotation and mirroring need to be done by
261 programming the SVSHAPE SPRs directly, which can take a lot more
264 ## FFT/DCT Triple Loop
266 DCT and FFT are some of the most astonishingly used algorithms in
267 Computer Science. Radar, Audio, Video, R.F. Baseband and dozens more. At least
268 two DSPs, TMS320 and Hexagon, have VLIW instructions specially tailored
271 An in-depth analysis showed that it is possible to do in-place in-register
272 DCT and FFT as long as twin-result "butterfly" instructions are provided.
273 These can be found in the [[openpower/isa/svfparith]] page if performing
274 IEEE754 FP transforms. *(For fixed-point transforms, equivalent 3-in 2-out
275 integer operations would be required)*. These "butterfly" instructions
276 avoid the need for a temporary register because the two array positions
277 being overwritten will be "in-flight" in any In-Order or Out-of-Order
280 DCT and FFT Schedules are currently limited to RADIX2 sizes and do not
281 accept predicate masks. Given that it is common to perform recursive
282 convolutions combining smaller Power-2 DCT/FFT to create larger DCT/FFTs
283 in practice the RADIX2 limit is not a problem. A Bluestein convolution
284 to compute arbitrary length is demonstrated by
285 [Project Nayuki](https://www.nayuki.io/res/free-small-fft-in-multiple-languages/fft.py)
289 The purpose of Indexing is to provide a generalised version of
290 Vector ISA "Permute" instructions, such as VSX `vperm`. The
291 Indexing is abstracted out and may be applied to much more
292 than an element move/copy, and is not limited for example
293 to the number of bytes that can fit into a VSX register.
294 Indexing may be applied to LD/ST (even on Indexed LD/ST
295 instructions such as `sv.lbzx`), arithmetic operations,
296 extsw: there is no artificial limit.
298 The only major caveat is that the registers to be used as
299 Indices must not be modified by any instruction after Indexed Mode
300 is established, and neither must MAXVL be altered. Additionally,
301 no register used as an Index may exceed MAXVL-1.
304 these conditions results in `UNDEFINED` behaviour.
305 These conditions allow a Read-After-Write (RAW) Hazard to be created on
306 the entire range of Indices to be subsequently used, but a corresponding
307 Write-After-Read Hazard by any instruction that modifies the Indices
308 **does not have to be created**. Given the large number of registers
309 involved in Indexing this is a huge resource saving and reduction
310 in micro-architectural complexity. MAXVL is likewise
311 included in the RAW Hazards because it is involved in calculating
312 how many registers are to be considered Indices.
314 With these Hazard Mitigations in place, high-performance implementations
315 may read-cache the Indices from the point where a given `svindex` instruction
316 is called (or SVSHAPE SPRs - and MAXVL- directly altered).
318 The original motivation for Indexed REMAP was to mitigate the need to add
319 an expensive `mv.x` to the Scalar ISA, which was likely to be rejected as
320 a stand-alone instruction. Usually a Vector ISA would add a non-conflicting
321 variant (as in VSX `vperm`) but it is common to need to permute by source,
322 with the risk of conflict, that has to be resolved, for example, in AVX-512
325 Indexed REMAP on the other hand **does not prevent conflicts** (overlapping
326 destinations), which on a superficial analysis may be perceived to be a
327 problem, until it is recalled that, firstly, Simple-V is designed specifically
328 to require Program Order to be respected, and that Matrix, DCT and FFT
329 all *already* critically depend on overlapping Reads/Writes: Matrix
330 uses overlapping registers as accumulators. Thus the Register Hazard
331 Management needed by Indexed REMAP *has* to be in place anyway.
333 The cost compared to Matrix and other REMAPs (and Pack/Unpack) is
334 clearly that of the additional reading of the GPRs to be used as Indices,
335 plus the setup cost associated with creating those same Indices.
336 If any Deterministic REMAP can cover the required task, clearly it
337 is adviseable to use it instead.
339 *Programmer's note: some algorithms may require skipping of Indices exceeding
340 VL-1, not MAXVL-1. This may be achieved programmatically by performing
341 an `sv.cmp *BF,*RA,RB` where RA is the same GPRs used in the Indexed REMAP,
342 and RB contains the value of VL returned from `setvl`. The resultant
343 CR Fields may then be used as Predicate Masks to exclude those operations
344 with an Index exceeding VL-1.*
346 ## Parallel Reduction
348 Vector Reduce Mode issues a deterministic tree-reduction schedule to the underlying micro-architecture. Like Scalar reduction, the "Scalar Base"
349 (Power ISA v3.0B) operation is leveraged, unmodified, to give the
350 *appearance* and *effect* of Reduction.
352 In Horizontal-First Mode, Vector-result reduction **requires**
353 the destination to be a Vector, which will be used to store
354 intermediary results.
356 Given that the tree-reduction schedule is deterministic,
357 Interrupts and exceptions
358 can therefore also be precise. The final result will be in the first
359 non-predicate-masked-out destination element, but due again to
360 the deterministic schedule programmers may find uses for the intermediate
363 When Rc=1 a corresponding Vector of co-resultant CRs is also
364 created. No special action is taken: the result and its CR Field
365 are stored "as usual" exactly as all other SVP64 Rc=1 operations.
367 Note that the Schedule only makes sense on top of certain instructions:
368 X-Form with a Register Profile of `RT,RA,RB` is fine because two sources
369 and the destination are all the same type. Like Scalar
370 Reduction, nothing is prohibited:
371 the results of execution on an unsuitable instruction may simply
372 not make sense. With care, even 3-input instructions (madd, fmadd, ternlogi)
375 Critical to note regarding use of Parallel-Reduction REMAP is that,
376 exactly as with all REMAP Modes, the `svshape` instruction *requests*
377 a certain Vector Length (number of elements to reduce) and then
378 sets VL and MAXVL at the number of **operations** needed to be
379 carried out. Thus, equally as importantly, like Matrix REMAP
380 the total number of operations
381 is restricted to 127. Any Parallel-Reduction requiring more operations
382 will need to be done manually in batches (hierarchical
383 recursive Reduction).
385 Also important to note is that the Deterministic Schedule is arranged
386 so that some implementations *may* parallelise it (as long as doing so
387 respects Program Order and Register Hazards). Performance (speed)
389 implementation is neither strictly defined or guaranteed. As with
390 the Vulkan(tm) Specification, strict compliance is paramount whilst
391 performance is at the discretion of Implementors.
393 **Parallel-Reduction with Predication**
395 To avoid breaking the strict RISC-paradigm, keeping the Issue-Schedule
396 completely separate from the actual element-level (scalar) operations,
397 Move operations are **not** included in the Schedule. This means that
398 the Schedule leaves the final (scalar) result in the first-non-masked
399 element of the Vector used. With the predicate mask being dynamic
400 (but deterministic) this result could be anywhere.
402 If that result is needed to be moved to a (single) scalar register
403 then a follow-up `sv.mv/sm=predicate rt, *ra` instruction will be
404 needed to get it, where the predicate is the exact same predicate used
405 in the prior Parallel-Reduction instruction.
407 * If there was only a single
408 bit in the predicate then the result will not have moved or been altered
409 from the source vector prior to the Reduction
410 * If there was more than one bit the result will be in the
411 first element with a predicate bit set.
413 In either case the result is in the element with the first bit set in
416 For *some* implementations
417 the vector-to-scalar copy may be a slow operation, as may the Predicated
418 Parallel Reduction itself.
419 It may be better to perform a pre-copy
420 of the values, compressing them (VREDUCE-style) into a contiguous block,
421 which will guarantee that the result goes into the very first element
422 of the destination vector, in which case clearly no follow-up
423 vector-to-scalar MV operation is needed.
427 The simplest usage is to perform an overwrite, specifying all three
428 register operands the same.
430 svshape parallelreduce, 6
433 The Reduction Schedule will issue the Parallel Tree Reduction spanning
434 registers 8 through 13, by adjusting the offsets to RT, RA and RB as
435 necessary (see "Parallel Reduction algorithm" in a later section).
437 A non-overwrite is possible as well but just as with the overwrite
438 version, only those destination elements necessary for storing
439 intermediary computations will be written to: the remaining elements
440 will **not** be overwritten and will **not** be zero'd.
442 svshape parallelreduce, 6
445 However it is critical to note that if the source and destination are
446 not the same then the trick of using a follow-up vector-scalar MV will
449 ## Sub-Vector Horizontal Reduction
451 Note that when SVM is clear and SUBVL!=1 a Parallel Reduction is performed
452 on all first Subvector elements, followed by another separate independent
453 Parallel Reduction on all the second Subvector elements and so on.
455 for selectsubelement in (x,y,z,w):
456 parallelreduce(0..VL-1, selectsubelement)
458 By contrast, when SVM is set and SUBVL!=1, a Horizontal
459 Subvector mode is enabled, applying the Parallel Reduction
460 Algorithm to the Subvector Elements. The Parallel Reduction
461 is independently applied VL times, to each group of Subvector
462 elements. Bear in mind that predication is never applied down
463 into individual Subvector elements, but will be applied
464 to select whether the *entire* Parallel Reduction on each
465 group is performed or not.
467 Â for (i = 0; i < VL; i++)
468 if (predval & 1<<i) # predication
470 parallelreduction([el.x, el.y, el.z, el.w])
472 Note that as this is a Parallel Reduction, for best results
473 it should be an overwrite operation, where the result for
474 the Horizontal Reduction of each Subvector will be in the
475 first Subvector element.
476 Also note that use of Rc=1 is `UNDEFINED` behaviour.
478 In essence what is happening here is that Structure Packing is being
479 combined with Parallel Reduction. If the Subvector elements may be
480 laid out as a 2D matrix, with the Subvector elements on rows,
481 and Parallel Reduction is applied per row, then if `SVM` is **clear**
482 the Matrix is transposed (like Pack/Unpack)
483 before still applying the Parallel Reduction to the **row**.
485 # Determining Register Hazards
487 For high-performance (Multi-Issue, Out-of-Order) systems it is critical
488 to be able to statically determine the extent of Vectors in order to
489 allocate pre-emptive Hazard protection. The next task is to eliminate
490 masked-out elements using predicate bits, freeing up the associated
493 For non-REMAP situations `VL` is sufficient to ascertain early
494 Hazard coverage, and with SVSTATE being a high priority cached
495 quantity at the same level of MSR and PC this is not a problem.
497 The problems come when REMAP is enabled. Indexed REMAP must instead
498 use `MAXVL` as the earliest (simplest)
499 batch-level Hazard Reservation indicator,
500 but Matrix, FFT and Parallel Reduction must all use completely different
501 schemes. The reason is that VL is used to step through the total
502 number of *operations*, not the number of registers. The "Saving Grace"
503 is that all of the REMAP Schedules are Deterministic.
505 Advance-notice Parallel computation and subsequent cacheing
506 of all of these complex Deterministic REMAP Schedules is
507 *strongly recommended*, thus allowing clear and precise multi-issue
508 batched Hazard coverage to be deployed, *even for Indexed Mode*.
509 This is only possible for Indexed due to the strict guidelines
510 given to Programmers.
512 In short, there exists solutions to the problem of Hazard Management,
513 with varying degrees of refinement possible at correspondingly
514 increasing levels of complexity in hardware.
516 # REMAP area of SVSTATE
518 The following bits of the SVSTATE SPR are used for REMAP:
520 |32.33|34.35|36.37|38.39|40.41| 42.46 | 62 |
521 | -- | -- | -- | -- | -- | ----- | ------ |
522 |mi0 |mi1 |mi2 |mo0 |mo1 | SVme | RMpst |
524 mi0-2 and mo0-1 each select SVSHAPE0-3 to apply to a given register.
525 mi0-2 apply to RA, RB, RC respectively, as input registers, and
526 likewise mo0-1 apply to output registers (RT/FRT, RS/FRS) respectively.
527 SVme is 5 bits (one for each of mi0-2/mo0-1) and indicates whether the
528 SVSHAPE is actively applied or not.
530 * bit 0 of SVme indicates if mi0 is applied to RA / FRA
531 * bit 1 of SVme indicates if mi1 is applied to RB / FRB
532 * bit 2 of SVme indicates if mi2 is applied to RC / FRC
533 * bit 3 of SVme indicates if mo0 is applied to RT / FRT
534 * bit 4 of SVme indicates if mo1 is applied to Effective Address / FRS / RS
535 (LD/ST-with-update has an implicit 2nd write register, RA)
537 # svremap instruction <a name="svremap"> </a>
541 svremap SVme,mi0,mi1,mi2,mo0,mo2,pst
543 |0 |6 |11 |13 |15 |17 |19 |21 | 22.25 |26..31 |
544 | -- | -- | -- | -- | -- | -- | -- | -- | ---- | ----- |
545 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | pst | rsvd | XO |
549 * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
553 # registers RA RB RC RT EA/FRS SVSHAPE0-3 indices
554 SVSTATE[32:33] <- mi0
555 SVSTATE[34:35] <- mi1
556 SVSTATE[36:37] <- mi2
557 SVSTATE[38:39] <- mo0
558 SVSTATE[40:41] <- mo1
559 # enable bit for RA RB RC RT EA/FRS
560 SVSTATE[42:46] <- SVme
561 # persistence bit (applies to more than one instruction)
564 Special Registers Altered:
568 # SHAPE Remapping SPRs
570 There are four "shape" SPRs, SHAPE0-3, 32-bits in each,
571 which have the same format.
573 Shape is 32-bits. When SHAPE is set entirely to zeros, remapping is
574 disabled: the register's elements are a linear (1D) vector.
576 |31.30|29..28 |27..24| 23..21 | 20..18 | 17..12 |11..6 |5..0 | Mode |
577 |---- |------ |------| ------ | ------- | ------- |----- |----- | ----- |
578 |0b00 |skip |offset| invxyz | permute | zdimsz |ydimsz|xdimsz|Matrix |
579 |0b00 |elwidth|offset|sk1/invxy|0b110/0b111|SVGPR|ydimsz|xdimsz|Indexed|
580 |0b01 |submode|offset| invxyz | submode2| zdimsz |mode |xdimsz|DCT/FFT|
581 |0b10 |submode|offset| invxyz | rsvd | rsvd |rsvd |xdimsz|Preduce|
582 |0b11 | | | | | | | |rsvd |
584 mode sets different behaviours (straight matrix multiply, FFT, DCT).
586 * **mode=0b00** sets straight Matrix Mode
587 * **mode=0b00** with permute=0b110 or 0b111 sets Indexed Mode
588 * **mode=0b01** sets "FFT/DCT" mode and activates submodes
589 * **mode=0b10** sets "Parallel Reduction" Schedules.
591 ## Parallel Reduction Mode
593 Creates the Schedules for Parallel Tree Reduction.
595 * **submode=0b00** selects the left operand index
596 * **submode=0b01** selects the right operand index
598 * When bit 0 of `invxyz` is set, the order of the indices
599 in the inner for-loop are reversed. This has the side-effect
600 of placing the final reduced result in the last-predicated element.
601 It also has the indirect side-effect of swapping the source
602 registers: Left-operand index numbers will always exceed
603 Right-operand indices.
604 When clear, the reduced result will be in the first-predicated
605 element, and Left-operand indices will always be *less* than
607 * When bit 1 of `invxyz` is set, the order of the outer loop
608 step is inverted: stepping begins at the nearest power-of two
609 to half of the vector length and reduces by half each time.
610 When clear the step will begin at 2 and double on each
615 submode2=0 is for FFT. For FFT submode the following schedules may be
618 * **submode=0b00** selects the ``j`` offset of the innermost for-loop
620 * **submode=0b10** selects the ``j+halfsize`` offset of the innermost for-loop
622 * **submode=0b11** selects the ``k`` of exptable (which coefficient)
624 When submode2 is 1 or 2, for DCT inner butterfly submode the following
625 schedules may be selected. When submode2 is 1, additional bit-reversing
628 * **submode=0b00** selects the ``j`` offset of the innermost for-loop,
630 * **submode=0b010** selects the ``j+halfsize`` offset of the innermost for-loop,
631 in reverse-order, in-place
632 * **submode=0b10** selects the ``ci`` count of the innermost for-loop,
633 useful for calculating the cosine coefficient
634 * **submode=0b11** selects the ``size`` offset of the outermost for-loop,
635 useful for the cosine coefficient ``cos(ci + 0.5) * pi / size``
637 When submode2 is 3 or 4, for DCT outer butterfly submode the following
638 schedules may be selected. When submode is 3, additional bit-reversing
641 * **submode=0b00** selects the ``j`` offset of the innermost for-loop,
642 * **submode=0b01** selects the ``j+1`` offset of the innermost for-loop,
644 `zdimsz` is used as an in-place "Stride", particularly useful for
645 column-based in-place DCT/FFT.
649 In Matrix Mode, skip allows dimensions to be skipped from being included
650 in the resultant output index. this allows sequences to be repeated:
651 ```0 0 0 1 1 1 2 2 2 ...``` or in the case of skip=0b11 this results in
652 modulo ```0 1 2 0 1 2 ...```
654 * **skip=0b00** indicates no dimensions to be skipped
655 * **skip=0b01** sets "skip 1st dimension"
656 * **skip=0b10** sets "skip 2nd dimension"
657 * **skip=0b11** sets "skip 3rd dimension"
659 invxyz will invert the start index of each of x, y or z. If invxyz[0] is
660 zero then x-dimensional counting begins from 0 and increments, otherwise
661 it begins from xdimsz-1 and iterates down to zero. Likewise for y and z.
663 offset will have the effect of offsetting the result by ```offset``` elements:
666 GPR(RT + remap(i) + SVSHAPE.offset) = ....
668 this appears redundant because the register RT could simply be changed by a compiler, until element width overrides are introduced. also
669 bear in mind that unlike a static compiler SVSHAPE.offset may
670 be set dynamically at runtime.
672 xdimsz, ydimsz and zdimsz are offset by 1, such that a value of 0 indicates
673 that the array dimensionality for that dimension is 1. any dimension
674 not intended to be used must have its value set to 0 (dimensionality
675 of 1). A value of xdimsz=2 would indicate that in the first dimension
676 there are 3 elements in the array. For example, to create a 2D array
677 X,Y of dimensionality X=3 and Y=2, set xdimsz=2, ydimsz=1 and zdimsz=0
679 The format of the array is therefore as follows:
681 array[xdimsz+1][ydimsz+1][zdimsz+1]
683 However whilst illustrative of the dimensionality, that does not take the
684 "permute" setting into account. "permute" may be any one of six values
685 (0-5, with values of 6 and 7 indicating "Indexed" Mode). The table
686 below shows how the permutation dimensionality order works:
688 | permute | order | array format |
689 | ------- | ----- | ------------------------ |
690 | 000 | 0,1,2 | (xdim+1)(ydim+1)(zdim+1) |
691 | 001 | 0,2,1 | (xdim+1)(zdim+1)(ydim+1) |
692 | 010 | 1,0,2 | (ydim+1)(xdim+1)(zdim+1) |
693 | 011 | 1,2,0 | (ydim+1)(zdim+1)(xdim+1) |
694 | 100 | 2,0,1 | (zdim+1)(xdim+1)(ydim+1) |
695 | 101 | 2,1,0 | (zdim+1)(ydim+1)(xdim+1) |
696 | 110 | 0,1 | Indexed (xdim+1)(ydim+1) |
697 | 111 | 1,0 | Indexed (ydim+1)(xdim+1) |
699 In other words, the "permute" option changes the order in which
700 nested for-loops over the array would be done. See executable
701 python reference code for further details.
703 *Note: permute=0b110 and permute=0b111 enable Indexed REMAP Mode,
706 With all these options it is possible to support in-place transpose,
707 in-place rotate, Matrix Multiply and Convolutions, without being
708 limited to Power-of-Two dimension sizes.
712 Indexed Mode activates reading of the element indices from the GPR
713 and includes optional limited 2D reordering.
714 In its simplest form (without elwidth overrides or other modes):
718 return GPR((SVSHAPE.SVGPR<<1)+i) + SVSHAPE.offset
721 element_result = ....
722 GPR(RT + indexed_remap(i)) = element_result
725 With element-width overrides included, and using the pseudocode
726 from the SVP64 [[sv/svp64/appendix#elwidth]] elwidth section
731 svreg = SVSHAPE.SVGPR << 1
732 srcwid = elwid_to_bitwidth(SVSHAPE.elwid)
733 offs = SVSHAPE.offset
734 return get_polymorphed_reg(svreg, srcwid, i) + offs
737 element_result = ....
738 rt_idx = indexed_remap(i)
739 set_polymorphed_reg(RT, destwid, rt_idx, element_result)
742 Matrix-style reordering still applies to the indices, except limited
743 to up to 2 Dimensions (X,Y). Ordering is therefore limited to (X,Y) or
744 (Y,X). Only one dimension may optionally be skipped. Inversion of either
745 X or Y or both is possible. Pseudocode for Indexed Mode (including elwidth
746 overrides) may be written in terms of Matrix Mode, specifically
747 purposed to ensure that the 3rd dimension (Z) has no effect:
750 def index_remap(ISHAPE, i):
751 MSHAPE.skip = 0b0 || ISHAPE.sk1
752 MSHAPE.invxyz = 0b0 || ISHAPE.invxy
753 MSHAPE.xdimsz = ISHAPE.xdimsz
754 MSHAPE.ydimsz = ISHAPE.ydimsz
755 MSHAPE.zdimsz = 0 # disabled
756 if ISHAPE.permute = 0b110 # 0,1
757 MSHAPE.permute = 0b000 # 0,1,2
758 if ISHAPE.permute = 0b111 # 1,0
759 MSHAPE.permute = 0b010 # 1,0,2
760 el_idx = remap_matrix(MSHAPE, i)
761 svreg = ISHAPE.SVGPR << 1
762 srcwid = elwid_to_bitwidth(ISHAPE.elwid)
764 return get_polymorphed_reg(svreg, srcwid, el_idx) + offs
767 The most important observation above is that the Matrix-style
768 remapping occurs first and the Index lookup second. Thus it
769 becomes possible to perform in-place Transpose of Indices which
770 may have been costly to set up or costly to duplicate
771 (waste register file space).
773 # svshape instruction <a name="svshape"> </a>
775 `svshape` is a convenience instruction that reduces instruction
776 count for common usage patterns, particularly Matrix, DCT and FFT. It sets up
777 (overwrites) all required SVSHAPE SPRs and also modifies SVSTATE
778 including VL and MAXVL. Using `svshape` therefore does not also
781 Form: SVM-Form SV "Matrix" Form (see [[isatables/fields.text]])
783 svshape SVxd,SVyd,SVzd,SVRM,vf
785 | 0.5|6.10 |11.15 |16..20 | 21..24 | 25 | 26..31| name |
786 | -- | -- | --- | ----- | ------ | -- | ------| -------- |
787 |OPCD| SVxd | SVyd | SVzd | SVRM | vf | XO | svshape |
791 * **SVxd** - SV REMAP "xdim"
792 * **SVyd** - SV REMAP "ydim"
793 * **SVzd** - SV REMAP "zdim"
794 * **SVRM** - SV REMAP Mode (0b00000 for Matrix, 0b00001 for FFT etc.)
795 * **vf** - sets "Vertical-First" mode
796 * **XO** - standard 6-bit XO field
798 *Note: SVxd, SVyz and SVzd are all stored "off-by-one". In the assembler
799 mnemonic the values `1-32` are stored in binary as `0b00000..0b11111`*
801 | SVRM | Remap Mode description |
803 | 0b0000 | Matrix 1/2/3D |
804 | 0b0001 | FFT Butterfly |
805 | 0b0010 | DCT Inner butterfly, pre-calculated coefficients |
806 | 0b0011 | DCT Outer butterfly |
807 | 0b0100 | DCT Inner butterfly, on-the-fly (Vertical-First Mode) |
808 | 0b0101 | DCT COS table index generation |
809 | 0b0110 | DCT half-swap |
810 | 0b0111 | Parallel Reduction |
811 | 0b1000 | reserved for svshape2 |
812 | 0b1001 | reserved for svshape2 |
813 | 0b1010 | iDCT Inner butterfly, pre-calculated coefficients |
814 | 0b1011 | iDCT Outer butterfly |
815 | 0b1100 | iDCT Inner butterfly, on-the-fly (Vertical-First Mode) |
816 | 0b1101 | iDCT COS table index generation |
817 | 0b1110 | iDCT half-swap |
818 | 0b1111 | FFT half-swap |
820 Examples showing how all of these Modes operate exists in the online
821 [SVP64 unit tests](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD)
822 and the full pseudocode setting up all SPRs
823 is in the [[openpower/isa/simplev]] page.
825 In Indexed Mode, there are only 5 bits available to specify the GPR
826 to use, out of 128 GPRs (7 bit numbering). Therefore, only the top
827 5 bits are given in the `SVxd` field: the bottom two implicit bits
828 will be zero (`SVxd || 0b00`).
830 `svshape` has *limited applicability* due to being a 32-bit instruction.
831 The full capability of SVSHAPE SPRs may be accessed by directly writing
832 to SVSHAPE0-3 with `mtspr`. Circumstances include Matrices with dimensions
833 larger than 32, and in-place Transpose. Potentially a future v3.1 Prefixed
834 instruction, `psvshape`, may extend the capability here.
836 # svindex instruction <a name="svindex"> </a>
838 `svindex` is a convenience instruction that reduces instruction
839 count for Indexed REMAP Mode. It sets up
840 (overwrites) all required SVSHAPE SPRs and can modify the REMAP
841 SPR as well. The relevant SPRs *may* be directly programmed with
842 `mtspr` however it is laborious to do so: svindex saves instructions
843 covering much of Indexed REMAP capability.
845 Form: SVI-Form SV "Indexed" Form (see [[isatables/fields.text]])
847 svindex SVG,rmm,SVd,ew,yx,mr,sk
849 | 0.5|6.10 |11.15 |16.20 | 21..25 | 26..31| name | Form |
850 | -- | -- | --- | ---- | ----------- | ------| -------- | ---- |
851 |OPCD| SVG | rmm | SVd | ew/yx/mm/sk | XO | svindex | SVI-Form |
855 * **SVd** - SV REMAP x/y dim
856 * **rmm** - REMAP mask: sets remap mi0-2/mo0-1 and SVSHAPEs,
858 * **ew** - sets element width override on the Indices
859 * **SVG** - GPR SVG<<2 to be used for Indexing
860 * **yx** - 2D reordering to be used if yx=1
861 * **mm** - mask mode. determines how `rmm` is interpreted.
862 * **sk** - Dimension skipping enabled
863 * **XO** - standard 6-bit XO field
865 *Note: SVd, like SVxd, SVyz and SVzd of `svshape`, are all stored
866 "off-by-one". In the assembler
867 mnemonic the values `1-32` are stored in binary as `0b00000..0b11111`*.
869 *Note: when `yx=1,sk=0` the second dimension is calculated as
874 * `rmm`, like REMAP.SVme, has bit 0
875 correspond to mi0, bit 1 to mi1, bit 2 to mi2,
876 bit 3 to mo0 and bit 4 to mi1
877 * all SVSHAPEs and the REMAP parts of SVSHAPE are first reset (initialised to zero)
878 * for each bit set in the 5-bit `rmm`, in order, the first
879 as-yet-unset SVSHAPE will be updated
880 with the other operands in the instruction, and the REMAP
882 * If all 5 bits of `rmm` are set then both mi0 and mo1 use SVSHAPE0.
883 * SVSTATE persistence bit is cleared
884 * No other alterations to SVSTATE are carried out
886 Example 1: if rmm=0b00110 then SVSHAPE0 and SVSHAPE1 are set up,
887 and the REMAP SPR set so that mi1 uses SVSHAPE0 and mi2
888 uses mi2. REMAP.SVme is also set to 0b00110, REMAP.mi1=0
889 (SVSHAPE0) and REMAP.mi2=1 (SVSHAPE1)
891 Example 2: if rmm=0b10001 then again SVSHAPE0 and SVSHAPE1
892 are set up, but the REMAP SPR is set so that mi0 uses SVSHAPE0
893 and mo1 uses SVSHAPE1. REMAP.SVme=0b10001, REMAP.mi0=0, REMAP.mo1=1
895 Rough algorithmic form:
897 marray = [mi0, mi1, mi2, mo0, mo1]
900 if not rmm[bit]: continue
902 SVSTATE{marray[bit]} = idx
903 idx = (idx+1) modulo 4
907 * bits 0-2 (MSB0 numbering) of `rmm` indicate an index selecting mi0-mo1
908 * bits 3-4 (MSB0 numbering) of `rmm` indicate which SVSHAPE 0-3 shall
910 * only the selected SVSHAPE is overwritten
911 * only the relevant bits in the REMAP area of SVSTATE are updated
912 * REMAP persistence bit is set.
914 Example 1: if `rmm`=0b01110 then bits 0-2 (MSB0) are 0b011 and
915 bits 3-4 are 0b10. thus, mo0 is selected and SVSHAPE2
916 to be updated. REMAP.SVme[3] will be set high and REMAP.mo0
919 Example 2: if `rmm`=0b10011 then bits 0-2 (MSB0) are 0b100 and
920 bits 3-4 are 0b11. thus, mo1 is selected and SVSHAPE3
921 to be updated. REMAP.SVme[4] will be set high and REMAP.mo1
924 Rough algorithmic form:
926 marray = [mi0, mi1, mi2, mo0, mo1]
930 SVSTATE{marray[bit]} = idx
933 In essence, `mm=0` is intended for use to set as much of the
934 REMAP State SPRs as practical with a single instruction,
935 whilst `mm=1` is intended to be a little more refined.
939 * **Disable 2D mapping**: to only perform Indexing without
940 reordering use `SVd=1,sk=0,yx=0` (or set SVd to a value larger
942 * **Modulo 1D mapping**: to perform Indexing cycling through the
943 first N Indices use `SVd=N,sk=0,yx=0` where `VL>N`. There is
944 no requirement to set VL equal to a multiple of N.
945 * **Modulo 2D transposed**: `SVd=M,sk=0,yx=1`, sets
946 `xdim=M,ydim=CEIL(MAXVL/M)`.
948 Beyond these mappings it becomes necessary to write directly to
949 the SVSTATE SPRs manually.
951 # svshape2 (offset) <a name="svshape2"> </a>
953 `svshape2` is an additional convenience instruction that prioritises
954 setting `SVSHAPE.offset`. Its primary purpose is for use when
955 element-width overrides are used. It has identical capabilities to `svindex` and
956 in terms of both options (skip, etc.) and ability to activate REMAP
957 (rmm, mask mode) but unlike `svindex` it does not set GPR REMAP,
958 only a 1D or 2D `svshape`, and
959 unlike `svshape` it can set an arbirrary `SVSHAPE.offset` immediate.
961 One of the limitations of Simple-V is that Vector elements start on the boundary
962 of the Scalar regfile, which is fine when element-width overrides are not
963 needed. If the starting point of a Vector with smaller elwidths must begin
964 in the middle of a register, normally there would be no way to do so except
965 through LD/ST. `SVSHAPE.offset` caters for this scenario and `svshape2`is
968 svshape2 offs,yx,rmm,SVd,sk,mm
970 | 0.5|6..9|10|11.15 |16..20 | 21..25 | 25 | 26..31| name |
971 | -- |----|--| --- | ----- | ------ | -- | ------| -------- |
972 |OPCD|offs|yx| rmm | SVd | 100/mm | sk | XO | svshape |
974 * **offs** (4 bits) - unsigned offset
975 * **yx** (1 bit) - swap XY to YX
976 * **SVd** dimension size
979 * **sk** (1 bit) skips 1st dimension if set
981 Dimensions are calculated exactly as `svindex`. `rmm` and
982 `mm` are as per `svindex`.
984 *Programmer's Note: offsets for `svshape2` may be specified in the range
985 0-15. Given that the principle of Simple-V is to fit on top of
986 byte-addressable register files and that GPR and FPR are 64-bit (8 bytes)
987 it should be clear that the offset may, when `elwidth=8`, begin an
988 element-level operation starting element zero at any arbitrary byte.
989 On cursory examination attempting to go beyond the range 0-7 seems
990 unnecessary given that the **next GPR or FPR** is an
991 alias for an offset in the range 8-15. Thus by simply increasing
992 the starting Vector point of the operation to the next register it
993 can be seen that the offset of 0-7 would be sufficient. Unfortunately
994 however some operations are EXTRA2-encoded it is **not possible**
995 to increase the GPR/FPR register number by one, because EXTRA2-encoding
996 of GPR/FPR Vector numbers are restricted to even numbering.
997 For CR Fields the EXTRA2 encoding is even more sparse.
998 The additional offset range (8-15) helps overcome these limitations.*
1000 *Hardware Implementor's note: with the offsets only being immediates
1001 and with register numbering being entirely immediate as well it is
1002 possible to correctly compute Register Hazards without requiring
1003 reading the contents of any SPRs. If however there are
1004 instructions that have directly written to the SVSTATE or SVSHAPE
1005 SPRs and those instructions are still in-flight then this position
1006 is clearly **invalid**.*
1014 # svstep: Vertical-First Stepping and status reporting
1018 * svstep RT,SVi,vf (Rc=0)
1019 * svstep. RT,SVi,vf (Rc=1)
1021 | 0-5|6-10|11.15|16..22| 23-25 | 26-30 |31| Form |
1022 |----|----|-----|------|----------|-------|--|--------- |
1023 |PO | RT | / | SVi | / / vf | XO |Rc| SVL-Form |
1028 if SVi[3:4] = 0b11 then
1029 # store pack and unpack in SVSTATE
1030 SVSTATE[53] <- SVi[5]
1031 SVSTATE[54] <- SVi[6]
1032 RT <- [0]*62 || SVSTATE[53:54]
1034 # Vertical-First explicit stepping.
1035 step <- SVSTATE_NEXT(SVi, vf)
1036 RT <- [0]*57 || step
1039 Special Registers Altered:
1057 Add the following to Book I, 1.6.1, SVI-Form
1060 |0 |6 |11 |16 |21 |23 |24|25|26 31|
1061 | PO | SVG|rmm | SVd |ew |SVyx|mm|sk| XO |
1064 Add the following to Book I, 1.6.1, SVM-Form
1067 |0 |6 |11 |16 |21 |25 |26 |31 |
1068 | PO | SVxd | SVyd | SVzd | SVrm |vf | XO |
1071 Add the following to Book I, 1.6.1, SVM2-Form
1074 # 1.6.35.1 SVM2-FORM
1075 |0 |6 |10 |11 |16 |21 |24|25 |26 |31 |
1076 | PO | SVo |SVyx| rmm | SVd |XO |mm|sk | XO |
1079 Add the following to Book I, 1.6.1, SVRM-Form
1083 |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 |
1084 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO |
1087 * Add `SVI, SVM, SVM2, SVRM` to `XO (26:31)` Field in Book I, 1.6.2
1089 Add the following to Book I, 1.6.2
1093 Field used in REMAP to select the SVSHAPE for 1st input register
1096 Field used in REMAP to select the SVSHAPE for 2nd input register
1099 Field used in REMAP to select the SVSHAPE for 3rd input register
1102 Field used to specify the meaning of the rmm field for SVI-Form
1106 Field used in REMAP to select the SVSHAPE for 1st output register
1109 Field used in REMAP to select the SVSHAPE for 2nd output register
1112 Field used in REMAP to indicate "persistence" mode (REMAP
1113 continues to apply to multiple instructions)
1116 REMAP Mode field for SVI-Form and SVM2-Form
1119 Field used to specify dimensional skipping in svindex
1122 Immediate field used to specify the size of the REMAP dimension
1123 in the svindex and svshape2 instructions
1126 Immediate field used to specify a 9-bit signed
1127 two's complement integer which is concatenated
1128 on the right with 0b00 and sign-extended to 64 bits.
1131 Field used to specify a GPR to be used as a
1132 source for indexing.
1135 Simple-V immediate field for setting VL or MVL
1138 Simple-V "REMAP" map-enable bits (0-4)
1141 Field used by the svshape2 instruction as an offset
1144 Simple-V "REMAP" Mode
1147 Simple-V "REMAP" x-dimension size
1150 Simple-V "REMAP" y-dimension size
1153 Simple-V "REMAP" z-dimension size
1159 Appendix E Power ISA sorted by opcode
1160 Appendix F Power ISA sorted by version
1161 Appendix G Power ISA sorted by Compliancy Subset
1162 Appendix H Power ISA sorted by mnemonic
1164 | Form | Book | Page | Version | mnemonic | Description |
1165 |------|------|------|---------|----------|-------------|
1166 | SVRM | I | # | 3.0B | svremap | REMAP enabling instruction |