openpower/sv/rfc/ls010.mdwn

   1 # RFC ls010 SVP64 Zero-Overhead Loop Prefix Subsystem
   2 **URLs**:
   3
   4 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
   5 * <https://libre-soc.org/openpower/sv/>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls010/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/64>
   9
  10 **Severity**: Major
  11
  12 **Status**: New
  13
  14 **Date**: 04 Apr 2023 v1
  15
  16 **Target**: v3.2B
  17
  18 **Source**: v3.0B
  19
  20 **Books and Section affected**:
  21
  22 ```
  23     New Book: new Zero-Overhead-Loop
  24     New Appendix, Zero-Overhead-Loop
  25 ```
  26
  27 **Summary**
  28
  29 ```
  30     Adds a Zero-Overhead-Loop Subsystem based on the Cray True-Scalable Vector concept
  31     in a RISC-paradigm fashion.  Total instructions added is six, plus Prefix format.
  32 ```
  33
  34 **Submitter**: Luke Leighton (Libre-SOC)
  35
  36 **Requester**: Libre-SOC
  37
  38 **Impact on processor**:
  39
  40 ```
  41     Addition of new "Zero-Overhead-Loop-Control" DSP-style Vector-style
  42     subsystem that in simple low-end (Embedded) systems may be minimalistically
  43     and easily be implemented by inserting a new fully-independent Pipeline Stage
  44     in between Decode and Issue, with very little disruption, and in higher
  45     performance pre-existing Multi-Issue Out-of-Order systems seamlessly fits likewise
  46     to significantly boost performance.
  47 ```
  48
  49 **Impact on software**:
  50
  51 ```
  52     Requires support for new instructions in assembler, debuggers, and related tools.
  53     Dramatically reduces instructions. Requires introduction of term "High-Level Assembler"
  54 ```
  55
  56 **Keywords**:
  57
  58 ```
  59     Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
  60     True-Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
  61     Digital Signal Processing (DSP), High-level Assembler
  62 ```
  63
  64 **Motivation**
  65
  66 Just at the time when customers are asking for higher performance,
  67 the seductive lure of SIMD, as outlined in the sigarch "SIMD Considered
  68 Harmful" article is getting out of control and damaging the reputation
  69 of mainstream general-purpose ISAs that offer it.  A solution from
  70 50 years ago exists in the form of Cray-Style True-Scalable Vectors.
  71 However the usual way that True-Scalable Vector ISAs are done *also*
  72 adds more instructions and complexifies the ISA.  Simple-V takes a step
  73 back to a simpler era in computing from half a century ago: the Zilog
  74 Z80 CPIR and LDIR instructions, and the 8086 REP instruction, and brings
  75 them forward to Modern-day Computing.  The result is a huge reduction in
  76 programming complexity, and a strong base to project the Power ISA back
  77 to the world's most powerful Supercomputing ISA for at least the next two
  78 decades.
  79
  80 **Notes and Observations**:
  81
  82 1. TODO
  83
  84 **Changes**
  85
  86 Add the following entries to:
  87
  88 * A new "Vector Looping" Book
  89 * New Vector-Looping Chapters
  90 * New Vector-Looping Appendices
  91
  92 [[!tag opf_rfc]]
  93
  94 --------
  95
  96 \newpage{}
  97
  98 [[!inline pages="openpower/sv/svp64" raw=yes ]]
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 103 [[!inline pages="openpower/sv/svp64/appendix" raw=yes ]]
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