openpower/sv/sprs.mdwn

   1 [[!tag standards]]
   2
   3 # SPRs <a name="sprs"></a>
   4
   5 Note Power ISA v3.1 p12:
   6
   7      The designated SPR sandbox consists of non-privileged SPRs
   8      704-719 and privileged SPRs 720-735.
   9
  10 There are eight SPRs, available in any privilege level:
  11
  12 * SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
  13 * SVLR, a mirror of LR, used by Vectorised Branch
  14 * SVSHAPE0-3 for REMAP purposes, re-shaping Vector loops
  15 * SVREMAP for applying specific shapes to specific registers
  16
  17 # SVSTATE
  18
  19 This is a standard SPR that (REMAP aside) contains sufficient information for a
  20 full context save/restore. It contains (and permits setting of):
  21
  22 * MVL (the Maximum Vector Length) - declares (statically) how
  23   much of a regfile is to be reserved for Vector elements
  24 * VL - Vector Length
  25 * dststep - the destination element offset of the current parallel
  26   instruction being executed
  27 * srcstep - for twin-predication, the source element offset as well.
  28 * ssubstep - the source subvector element offset of the current
  29   parallel instruction being executed
  30 * dsubstep - the destination subvector element offset of the current
  31   parallel instruction being executed
  32 * vfirst - Vertical First mode.  srcstep, dststep and substep
  33     **do not advance** unless explicitly requested to do so with
  34     pseudo-op svstep (a mode of setvl)
  35 * RMpst - REMAP persistence.  REMAP will apply only to the following
  36   instruction unless this bit is set, in which case REMAP "persists".
  37   Reset (cleared) on use of the `setvl` instruction if used to
  38   alter VL or MVL.
  39 * Pack - if set then srcstep/substep VL/SUBVL loop-ordering is inverted.
  40 * UnPack - if set then dststep/substep VL/SUBVL loop-ordering is inverted.
  41 * hphint - Horizontal Parallelism Hint. Indicates that
  42   no Hazards exist between this number of sequentially-accessed
  43    elements (including after REMAP). In Vertical First Mode
  44    hardware **MUST** perform this many elements in parallel
  45    per instruction. Set to zero to indicate "no hint".
  46 * SVme - REMAP enable bits, indicating which register is to be
  47  REMAPed.  RA, RB, RC, RT or EA.
  48 * mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4
  49   indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
  50   should use.
  51
  52 **MAXVECTORLENGTH (MVL)** <a name="mvl" />
  53
  54 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
  55 is variable length and may be dynamically set.  MVL is
  56 however limited to the regfile bitwidth, 64.
  57
  58 **Vector Length (VL)** <a name="vl" />
  59
  60 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
  61 the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
  62
  63     VL = rd = MIN(vlen, MVL)
  64
  65 where 1 <= MVL <= XLEN
  66
  67 **SUBVL - Sub Vector Length**
  68
  69 This is a "group by quantity" that effectively asks each iteration
  70 of the hardware loop to load SUBVL elements of width elwidth at a
  71 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
  72 operation issued, SUBVL operations are issued.
  73
  74 The main effect of SUBVL is that predication bits are applied per
  75 **group**, rather than by individual element.  Legal values are 1 to 4.
  76 Illegal values raise an exception.
  77
  78 **Horizontal Parallelism**
  79
  80 A problem exists for hardware where it may not be able to detect
  81 that a programmer (or compiler) knows of opportunities for parallelism
  82 and lack of overlap between loops.
  83
  84 For hphint, the number chosen must be consistently
  85 executed **every time**. Hardware is not permitted to execute five
  86 computations for one instruction then three on the next.
  87 hphint is a hint from the compiler to hardware that exactly this
  88 many elements may be safely executed in parallel, without hazards
  89 (including Memory accesses).
  90 Interestingly, when hphint is set equal to VL, it is in effect
  91 as if Vertical First mode were not set, because the hardware is
  92 given the option to run through all elements in an instruction.
  93 This is exactly what Horizontal-First is: a for-loop from 0 to VL-1
  94 except that the hardware may *choose* the number of elements.
  95
  96 *Note to programmers: changing VL during the middle of such modes
  97 should be done only with due care and respect for the fact that SVSTATE
  98 has exactly the same peer-level status as a Program Counter.*
  99
 100 **SVSTATE SPR**
 101
 102 The format of the SVSTATE SPR is as follows:
 103
 104 | Field | Name     | Description           |
 105 | ----- | -------- | --------------------- |
 106 | 0:6   | maxvl    | Max Vector Length     |
 107 | 7:13  |    vl    | Vector Length         |
 108 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
 109 | 21:27 | dststep  | for dststep = 0..VL-1 |
 110 | 28:29 | dsubstep | for substep = 0..SUBVL-1  |
 111 | 30:31 | ssubstep | for substep = 0..SUBVL-1  |
 112 | 32:33 | mi0      | REMAP RA SVSHAPE0-3    |
 113 | 34:35 | mi1      | REMAP RB SVSHAPE0-3    |
 114 | 36:37 | mi2      | REMAP RC SVSHAPE0-3    |
 115 | 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
 116 | 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
 117 | 42:46 | SVme     | REMAP enable (RA-RT)  |
 118 | 47:52 | rsvd     | reserved              |
 119 | 53    | pack     | PACK (srcstrp reorder)  |
 120 | 54    | unpack   | UNPACK (dststep order)  |
 121 | 55:61 | hphint   | Horizontal Hint       |
 122 | 62    | RMpst    | REMAP persistence     |
 123 | 63    | vfirst   | Vertical First mode   |
 124
 125 Notes:
 126
 127 * The entries are truncated to be within range.  Attempts to set VL to
 128   greater than MAXVL will truncate VL.
 129 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
 130   than 64 is reserved and will cause an illegal instruction trap.
 131
 132 # SVLR
 133
 134 SV Link Register, exactly analogous to LR (Link Register) may
 135 be used for temporary storage of SVSTATE, and, in particular,
 136 Vectorised Branch-Conditional instructions may interchange
 137 SVLR and SVSTATE whenever LR and NIA are.
 138
 139 Note that there is no equivalent Link variant of SVREMAP or
 140 SVSHAPE0-3 (it would be too costly), so SVLR has limited applicability:
 141 REMAP SPRs must be saved and restored explicitly.