openpower/sv/sprs.mdwn

   1 [[!tag standards]]
   2
   3 # SPRs <a name="sprs"></a>
   4
   5 Note OpenPOWER v3.1B p12:
   6
   7      The designated SPR sandbox consists of non-privileged SPRs
   8      704-719 and privileged SPRs 720-735.
   9
  10 There are five SPRs, available in any privilege level:
  11
  12 * MVL (the Maximum Vector Length)
  13 * VL (which has different characteristics from standard SPRs)
  14 * SUBVL (effectively a kind of SIMD)
  15 * SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
  16 * SVSRR0 which is used for exceptions and traps to store SVSTATE.
  17
  18 MVL, VL and SUBVL are only provided for convenience: normally [[sv/setvl]] would be used to obtain a copy of VL, for example.
  19
  20 For Privilege Levels (trap handling) there are the following SPRs,
  21 where x may be u, s or h for User, Supervisor or Hypervisor
  22 Modes respectively:
  23
  24 * (x)eSTATE (useful for saving and restoring during context switch,
  25   and for providing fast transitions)
  26
  27 The u/s SPRs are treated and handled exactly like their (x)epc
  28 equivalents.  On entry to or exit from a privilege level, the contents
  29 of its (x)eSTATE are swapped with SVSTATE.
  30
  31 # MAXVECTORLENGTH (MVL) <a name="mvl" />
  32
  33 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
  34 is variable length and may be dynamically set.  MVL is
  35 however limited to the regfile bitwidth, 64.
  36
  37 # Vector Length (VL) <a name="vl" />
  38
  39 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
  40 the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
  41
  42     VL = rd = MIN(vlen, MVL)
  43
  44 where 1 <= MVL <= XLEN
  45
  46 # SUBVL - Sub Vector Length
  47
  48 This is a "group by quantity" that effectively asks each iteration
  49 of the hardware loop to load SUBVL elements of width elwidth at a
  50 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
  51 operation issued, SUBVL operations are issued.
  52
  53 The main effect of SUBVL is that predication bits are applied per
  54 **group**, rather than by individual element.  Legal values are 1 to 4.
  55 Illegal values raise an exception.
  56
  57 # SVSTATE
  58
  59 This is a standard SPR that contains sufficient information for a
  60 full context save/restore (see SVSRR0).  It contains (and permits setting of):
  61
  62 * MVL
  63 * VL
  64 * dststep - the destination element offset of the current parallel
  65   instruction being executed
  66 * srcstep - for twin-predication, the source element offset as well.
  67 * SUBVL
  68 * svstep - the subvector element offset of the current
  69   parallel instruction being executed
  70 * vfirst - Vertical First mode.  srcstep, dststep and substep
  71     **do not advance** unless explicitly requested to do so with
  72     pseudo-op svstep (a mode of setvl)
  73 * RMpst - REMAP persistence.  REMAP will apply only to the following
  74   instruction unless this bit is set, in which case REMAP "persists".
  75   Reset (cleared) on use of the `setvl` instruction if used to
  76   alter VL or MVL.
  77 * hphint - Horizontal Parallelism Hint. In Vertical First Mode
  78    hardware **MAY** perform up to this many elements in parallel
  79    per instruction. Set to zero to indicate "no hint".
  80 * SVme - REMAP enable bits, indicating which register is to be
  81  REMAPed.  RA, RB, RC, RT or EA.
  82 * mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4
  83   indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
  84   should use.
  85
  86 For hphint, the number chosen must be consistently
  87 executed **every time**. Hardware is not permitted to execute five
  88 computations for one instruction then three on the next.
  89 hphint is a hint from the compiler to hardware that up to this
  90 many elements may be safely executed in parallel.
  91 Interestingly, when hphint is set equal to VL, it is in effect
  92 as if Vertical First mode were not set, because the hardware is
  93 given the option to run through all elements in an instruction.
  94 This is exactly what Horizontal-First is: a for-loop from 0 to VL-1
  95 except that the hardware may *choose* the number of elements.
  96
  97 *Note to programmers: changing VL during the middle of such modes
  98 should be done only with due care and respect for the fact that SVSTATE
  99 has exactly the same peer-level status as a Program Counter.*
 100
 101 The format of the SVSTATE SPR is as follows:
 102
 103 | Field | Name     | Description           |
 104 | ----- | -------- | --------------------- |
 105 | 0:6   | maxvl    | Max Vector Length     |
 106 | 7:13  |    vl    | Vector Length         |
 107 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
 108 | 21:27 | dststep  | for dststep = 0..VL-1 |
 109 | 28:29 | subvl    | Sub-vector length     |
 110 | 30:31 | svstep   | for svstep = 0..SUBVL-1  |
 111 | 32:33 | mi0      | REMAP RA SVSHAPE0-3    |
 112 | 34:35 | mi1      | REMAP RB SVSHAPE0-3    |
 113 | 36:37 | mi2      | REMAP RC SVSHAPE0-3    |
 114 | 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
 115 | 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
 116 | 42:46 | SVme     | REMAP enable (RA-RT)  |
 117 | 47:54 | rsvd     | reserved              |
 118 | 55:61 | hphint   | horizontal parallelism hint  |
 119 | 62    | RMpst    | REMAP persistence     |
 120 | 63    | vfirst   | Vertical First mode   |
 121
 122 The relationship between SUBVL and the subvl field is:
 123
 124 | SUBVL | (29..28) |
 125 | ----- | -------- |
 126 | 1     | 0b00     |
 127 | 2     | 0b01     |
 128 | 3     | 0b10     |
 129 | 4     | 0b11     |
 130
 131 Notes:
 132
 133 * The entries are truncated to be within range.  Attempts to set VL to
 134   greater than MAXVL will truncate VL.
 135 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
 136   than 64 is reserved and will cause an illegal instruction trap.
 137
 138 # SVSRR0
 139
 140 In scalar v3.0B traps, exceptions and interrupts, two SRRs are saved/restored:
 141
 142 * SRR0 to store the PC (CIA/NIA)
 143 * SRR1 to store a copy of the MSR
 144
 145 Given that SVSTATE is effectively a Sub-PC it is critically important to add saving/restoring of SVSTATE as a full peer equal in status to PC, in every way.  At any time PC is saved or restored, so is SVSTATE in **exactly** the same way for **exactly** the same reasons.  Thus, at an exception point,
 146 hardware **must** save/restore SVSTATE in SVSRR0 at exactly the same
 147 time that SRR0 is saved/restored in PC and SRR1 in MSR.
 148
 149 The SPR name given for the purposes of saving/restoring
 150 SVSTATE is SVSRR0.