[libreriscv.git] / openpower / sv / svp64 / appendix.mdwn

# Appendix

* <https://bugs.libre-soc.org/show_bug.cgi?id=574>
* <https://bugs.libre-soc.org/show_bug.cgi?id=558#c47>
* <https://bugs.libre-soc.org/show_bug.cgi?id=697>

This is the appendix to [[sv/svp64]], providing explanations of modes
etc. leaving the main svp64 page's primary purpose as outlining the
instruction format.

Table of contents:

[[!toc]]

# XER, SO and other global flags

Vector systems are expected to be high performance.  This is achieved
through parallelism, which requires that elements in the vector be
independent.  XER SO and other global "accumulation" flags (CR.OV) cause
Read-Write Hazards on single-bit global resources, having a significant
detrimental effect.

Consequently in SV, XER.SO and CR.OV behaviour is disregarded (including
in `cmp` instructions).  XER is simply neither read nor written.
This includes when `scalar identity behaviour` occurs.  If precise
OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1
instructions should be used without an SV Prefix.

An interesting side-effect of this decision is that the OE flag is now
free for other uses when SV Prefixing is used.

Regarding XER.CA: this does not fit either: it was designed for a scalar
ISA. Instead, both carry-in and carry-out go into the CR.so bit of a given
Vector element.  This provides a means to perform large parallel batches
of Vectorised carry-capable additions.  crweird instructions can be used
to transfer the CRs in and out of an integer, where bitmanipulation
may be performed to analyse the carry bits (including carry lookahead
propagation) before continuing with further parallel additions.

# v3.0B/v3.1 relevant instructions

SV is primarily designed for use as an efficient hybrid 3D GPU / VPU /
CPU ISA.

As mentioned above, OE=1 is not applicable in SV, freeing this bit for
alternative uses.  Additionally, Vectorisation of the VSX SIMD system
likewise makes no sense whatsoever. SV *replaces* VSX and provides,
at the very minimum, predication (which VSX was designed without).
Thus all VSX Major Opcodes - all of them - are "unused" and must raise
illegal instruction exceptions in SV Prefix Mode.

Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to
have because they are not only provided by SV, the SV alternatives may
be predicated as well, making them far better suited to use in function
calls and context-switching.

Additionally, some v3.0/1 instructions simply make no sense at all in a
Vector context: `rfid` falls into this category,
as well as `sc` and `scv`.  Here there is simply no point
trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions
should be called instead.

Fortuitously this leaves several Major Opcodes free for use by SV
to fit alternative future instructions.  In a 3D context this means
Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST
operations, and others critical to an efficient, effective 3D GPU and
VPU ISA. With such instructions being included as standard in other
commercially-successful GPU ISAs it is likewise critical that a 3D
GPU/VPU based on svp64 also have such instructions.

Note however that svp64 is stand-alone and is in no way
critically dependent on the existence or provision of 3D GPU or VPU
instructions. These should be considered extensions, and their discussion
and specification is out of scope for this document.

Note, again: this is *only* under svp64 prefixing.  Standard v3.0B /
v3.1B is *not* altered by svp64 in any way.

## Major opcode map (v3.0B)

This table is taken from v3.0B.
Table 9: Primary Opcode Map (opcode bits 0:5)

        |  000   |   001 |  010  | 011   |  100  |    101 |  110  |  111
    000 |        |       |  tdi  | twi   | EXT04 |        |       | mulli | 000
    001 | subfic |       | cmpli | cmpi  | addic | addic. | addi  | addis | 001
    010 | bc/l/a | EXT17 | b/l/a | EXT19 | rlwimi| rlwinm |       | rlwnm | 010
    011 |  ori   | oris  | xori  | xoris | andi. | andis. | EXT30 | EXT31 | 011
    100 |  lwz   | lwzu  | lbz   | lbzu  | stw   | stwu   | stb   | stbu  | 100
    101 |  lhz   | lhzu  | lha   | lhau  | sth   | sthu   | lmw   | stmw  | 101
    110 |  lfs   | lfsu  | lfd   | lfdu  | stfs  | stfsu  | stfd  | stfdu | 110
    111 |  lq    | EXT57 | EXT58 | EXT59 | EXT60 | EXT61  | EXT62 | EXT63 | 111
        |  000   |   001 |   010 |  011  |   100 |   101  | 110   |  111

## Suitable for svp64-only

This is the same table containing v3.0B Primary Opcodes except those that
make no sense in a Vectorisation Context have been removed.  These removed
POs can, *in the SV Vector Context only*, be assigned to alternative
(Vectorised-only) instructions, including future extensions.

Note, again, to emphasise: outside of svp64 these opcodes **do not**
change.  When not prefixed with svp64 these opcodes **specifically**
retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning.

        |  000   |   001 |  010  | 011   |  100  |    101 |  110  |  111
    000 |        |       |       |       |       |        |       | mulli | 000
    001 | subfic |       | cmpli | cmpi  | addic | addic. | addi  | addis | 001
    010 |        |       |       | EXT19 | rlwimi| rlwinm |       | rlwnm | 010
    011 |  ori   | oris  | xori  | xoris | andi. | andis. | EXT30 | EXT31 | 011
    100 |  lwz   | lwzu  | lbz   | lbzu  | stw   | stwu   | stb   | stbu  | 100
    101 |  lhz   | lhzu  | lha   | lhau  | sth   | sthu   |       |       | 101
    110 |  lfs   | lfsu  | lfd   | lfdu  | stfs  | stfsu  | stfd  | stfdu | 110
    111 |        |       | EXT58 | EXT59 |       | EXT61  |       | EXT63 | 111
        |  000   |   001 |   010 |  011  |   100 |   101  | 110   |  111

It is important to note that having a different v3.0B Scalar opcode
that is different from an SVP64 one is highly undesirable: the complexity
in the decoder is greatly increased.

# Single Predication

This is a standard mode normally found in Vector ISAs.  every element in every source Vector and in the destination uses the same bit of one single predicate mask.

In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep: unlike Twin-Predication the two must be equal at all times.

# Twin Predication

This is a novel concept that allows predication to be applied to a single
source and a single dest register.  The following types of traditional
Vector operations may be encoded with it, *without requiring explicit
opcodes to do so*

* VSPLAT (a single scalar distributed across a vector)
* VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction))
* VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction))
* VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics))
* VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics))

Those patterns (and more) may be applied to:

* mv (the usual way that V\* ISA operations are created)
* exts\* sign-extension
* rwlinm and other RS-RA shift operations (**note**: excluding
  those that take RA as both a src and dest. These are not
  1-src 1-dest, they are 2-src, 1-dest)
* LD and ST (treating AGEN as one source)
* FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc.
* Condition Register ops mfcr, mtcr and other similar

This is a huge list that creates extremely powerful combinations,
particularly given that one of the predicate options is `(1<<r3)`

Additional unusual capabilities of Twin Predication include a back-to-back
version of VCOMPRESS-VEXPAND which is effectively the ability to do
sequentially ordered multiple VINSERTs.  The source predicate selects a
sequentially ordered subset of elements to be inserted; the destination
predicate specifies the sequentially ordered recipient locations.
This is equivalent to
`llvm.masked.compressstore.*`
followed by
`llvm.masked.expandload.*`

# Reduce modes

Reduction in SVP64 is deterministic and somewhat of a misnomer.  A normal
Vector ISA would have explicit Reduce opcodes with defined characteristics
per operation: in SX Aurora there is even an additional scalar argument
containing the initial reduction value, and the default is either 0
or 1 depending on the specifics of the explicit opcode.
SVP64 fundamentally has to
utilise *existing* Scalar Power ISA v3.0B operations, which presents some
unique challenges.

The solution turns out to be to simply define reduction as permitting
deterministic element-based schedules to be issued using the base Scalar
operations, and to rely on the underlying microarchitecture to resolve
Register Hazards at the element level.  This goes back to
the fundamental principle that SV is nothing more than a Sub-Program-Counter
sitting between Decode and Issue phases.

Microarchitectures *may* take opportunities to parallelise the reduction
but only if in doing so they preserve Program Order at the Element Level.
Opportunities where this is possible include an `OR` operation
or a MIN/MAX operation: it may be possible to parallelise the reduction,
but for Floating Point it is not permitted due to different results
being obtained if the reduction is not executed in strict sequential
order.

In essence it becomes the programmer's responsibility to leverage the
pre-determined schedules to desired effect.

## Scalar result reduction and iteration

Scalar Reduction per se does not exist, instead is implemented in SVP64
as a simple and natural relaxation of the usual restriction on the Vector
Looping which would terminate if the destination was marked as a Scalar.
Scalar Reduction by contrast *keeps issuing Vector Element Operations*
even though the destination register is marked as scalar.
Thus it is up to the programmer to be aware of this and observe some
conventions.

It is also important to appreciate that there is no
actual imposition or restriction on how this mode is utilised: there
will therefore be several valuable uses (including Vector Iteration
and "Reverse-Gear")
and it is up to the programmer to make best use of the
(strictly deterministic) capability
provided.

In this mode, which is suited to operations involving carry or overflow,
one register must be assigned, by convention by the programmer to be the
"accumulator".  Scalar reduction is thus categorised by:

* One of the sources is a Vector
* the destination is a scalar
* optionally but most usefully when one source scalar register is
  also the scalar destination (which may be informally termed
  the "accumulator")
* That the source register type is the same as the destination register
  type identified as the "accumulator".  Scalar reduction on `cmp`,
  `setb` or `isel` makes no sense for example because of the mixture
  between CRs and GPRs.

*Note that issuing instructions in Scalar reduce mode such as `setb`
are neither `UNDEFINED` nor prohibited, despite them not making much
sense at first glance.
Scalar reduce is strictly defined behaviour, and the cost in
hardware terms of prohibition of seemingly non-sensical operations is too great.
Therefore it is permitted and required to be executed successfully.
Implementors **MAY** choose to optimise such instructions in instances
where their use results in "extraneous execution", i.e. where it is clear
that the sequence of operations, comprising multiple overwrites to
a scalar destination **without** cumulative, iterative, or reductive
behaviour (no "accumulator"), may discard all but the last element
operation.  Identification
of such is trivial to do for `setb` and `cmp`: the source register type is
a completely different register file from the destination*

Typical applications include simple operations such as `ADD r3, r10.v,
r3` where, clearly, r3 is being used to accumulate the addition of all
elements is the vector starting at r10.

     # add RT, RA,RB but when RT==RA
     for i in range(VL):
          iregs[RA] += iregs[RB+i] # RT==RA

However, *unless* the operation is marked as "mapreduce" (`sv.add/mr`)
SV ordinarily
**terminates** at the first scalar operation.  Only by marking the
operation as "mapreduce" will it continue to issue multiple sub-looped
(element) instructions in `Program Order`.

To perform the loop in reverse order, the ```RG``` (reverse gear) bit must be set.  This may be useful in situations where the results may be different
(floating-point) if executed in a different order.  Given that there is
no actual prohibition on Reduce Mode being applied when the destination
is a Vector, the "Reverse Gear" bit turns out to be a way to apply Iterative
or Cumulative Vector operations in reverse. `sv.add/rg r3.v, r4.v, r4.v`
for example will start at the opposite end of the Vector and push
a cumulative series of overlapping add operations into the Execution units of
the underlying hardware.

Other examples include shift-mask operations where a Vector of inserts
into a single destination register is required, as a way to construct
a value quickly from multiple arbitrary bit-ranges and bit-offsets.
Using the same register as both the source and destination, with Vectors
of different offsets masks and values to be inserted has multiple
applications including Video, cryptography and JIT compilation.

Subtract and Divide are still permitted to be executed in this mode,
although from an algorithmic perspective it is strongly discouraged.
It would be better to use addition followed by one final subtract,
or in the case of divide, to get better accuracy, to perform a multiply
cascade followed by a final divide.

Note that single-operand or three-operand scalar-dest reduce is perfectly
well permitted: the programmer may still declare one register, used as
both a Vector source and Scalar destination, to be utilised as 
the "accumulator".  In the case of `sv.fmadds` and `sv.maddhw` etc
this naturally fits well with the normal expected usage of these
operations.

If an interrupt or exception occurs in the middle of the scalar mapreduce,
the scalar destination register **MUST** be updated with the current
(intermediate) result, because this is how ```Program Order``` is
preserved (Vector Loops are to be considered to be just another way of issuing instructions
in Program Order).  In this way, after return from interrupt,
the scalar mapreduce may continue where it left off.  This provides
"precise" exception behaviour.

Note that hardware is perfectly permitted to perform multi-issue
parallel optimisation of the scalar reduce operation: it's just that
as far as the user is concerned, all exceptions and interrupts **MUST**
be precise.

## Vector result reduce mode

Vector Reduce Mode issues a deterministic tree-reduction schedule to the underlying micro-architecture.  Like Scalar reduction, the "Scalar Base"
(Power ISA v3.0B) operation is leveraged, unmodified, to give the
*appearance* and *effect* of Reduction.

Given that the tree-reduction schedule is deterministic,
Interrupts and exceptions
can therefore also be precise.  The final result will be in the first
non-predicate-masked-out destination element, but due again to
the deterministic schedule programmers may find uses for the intermediate
results.

When Rc=1 a corresponding Vector of co-resultant CRs is also
created.  No special action is taken: the result and its CR Field
are stored "as usual" exactly as all other SVP64 Rc=1 operations.

## Sub-Vector Horizontal Reduction

Note that when SVM is clear and SUBVL!=1 the sub-elements are
*independent*, i.e. they are mapreduced per *sub-element* as a result.
illustration with a vec2, assuming RA==RT, e.g `sv.add/mr/vec2 r4, r4, r16`

    for i in range(0, VL):
        # RA==RT in the instruction. does not have to be
        iregs[RT].x = op(iregs[RT].x, iregs[RB+i].x)
        iregs[RT].y = op(iregs[RT].y, iregs[RB+i].y)

Thus logically there is nothing special or unanticipated about
`SVM=0`: it is expected behaviour according to standard SVP64
Sub-Vector rules.

By contrast, when SVM is set and SUBVL!=1, a Horizontal
Subvector mode is enabled, which behaves very much more
like a traditional Vector Processor Reduction instruction.
Example for a vec3:

    for i in range(VL):
        result = iregs[RA+i].x
        result = op(result, iregs[RA+i].y)
        result = op(result, iregs[RA+i].z)
        iregs[RT+i] = result

In this mode, when Rc=1 the Vector of CRs is as normal: each result
element creates a corresponding CR element (for the final, reduced, result).

# Fail-on-first

Data-dependent fail-on-first has two distinct variants: one for LD/ST,
the other for arithmetic operations (actually, CR-driven).  Note in each
case the assumption is that vector elements are required appear to be
executed in sequential Program Order, element 0 being the first.

* LD/ST ffirst treats the first LD/ST in a vector (element 0) as an
  ordinary one.  Exceptions occur "as normal".  However for elements 1
  and above, if an exception would occur, then VL is **truncated** to the
  previous element.
* Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
  CR-creating operation produces a result (including cmp).  Similar to
  branch, an analysis of the CR is performed and if the test fails, the
  vector operation terminates and discards all element operations at and
  above the current one, and VL is truncated to either
  the *previous* element or the current one, depending on whether
  VLi (VL "inclusive") is set.

Thus the new VL comprises a contiguous vector of results, 
all of which pass the testing criteria (equal to zero, less than zero).

The CR-based data-driven fail-on-first is new and not found in ARM
SVE or RVV. It is extremely useful for reducing instruction count,
however requires speculative execution involving modifications of VL
to get high performance implementations.  An additional mode (RC1=1)
effectively turns what would otherwise be an arithmetic operation
into a type of `cmp`.  The CR is stored (and the CR.eq bit tested
against the `inv` field).
If the CR.eq bit is equal to `inv` then the Vector is truncated and
the loop ends.
Note that when RC1=1 the result elements are never stored, only the CRs.

VLi is only available as an option when `Rc=0` (or for instructions
which do not have Rc). When set, the current element is always
also included in the count (the new length that VL will be set to).
This may be useful in combination with "inv" to truncate the Vector
to `exclude` elements that fail a test, or, in the case of implementations
of strncpy, to include the terminating zero.

In CR-based data-driven fail-on-first there is only the option to select
and test one bit of each CR (just as with branch BO).  For more complex
tests this may be insufficient.  If that is the case, a vectorised crops
(crand, cror) may be used, and ffirst applied to the crop instead of to
the arithmetic vector.

One extremely important aspect of ffirst is:

* LDST ffirst may never set VL equal to zero.  This because on the first
  element an exception must be raised "as normal".
* CR-based data-dependent ffirst on the other hand **can** set VL equal
  to zero. This is the only means in the entirety of SV that VL may be set
  to zero (with the exception of via the SV.STATE SPR).  When VL is set
  zero due to the first element failing the CR bit-test, all subsequent
  vectorised operations are effectively `nops` which is
  *precisely the desired and intended behaviour*.

Another aspect is that for ffirst LD/STs, VL may be truncated arbitrarily
to a nonzero value for any implementation-specific reason.  For example:
it is perfectly reasonable for implementations to alter VL when ffirst
LD or ST operations are initiated on a nonaligned boundary, such that
within a loop the subsequent iteration of that loop begins subsequent
ffirst LD/ST operations on an aligned boundary.  Likewise, to reduce
workloads or balance resources.

CR-based data-dependent first on the other hand MUST not truncate VL
arbitrarily to a length decided by the hardware: VL MUST only be
truncated based explicitly on whether a test fails.
This because it is a precise test on which algorithms
will rely.

## Data-dependent fail-first on CR operations (crand etc)

Operations that actually produce or alter CR Field as a result
do not also in turn have an Rc=1 mode.  However it makes no
sense to try to test the 4 bits of a CR Field for being equal
or not equal to zero. Moreover, the result is already in the
form that is desired: it is a CR field.  Therefore,
CR-based operations have their own SVP64 Mode, described
in [[sv/cr_ops]]

There are two primary different types of CR operations:

* Those which have a 3-bit operand field (referring to a CR Field)
* Those which have a 5-bit operand (referring to a bit within the
   whole 32-bit CR)

More details can be found in [[sv/cr_ops]].

# pred-result mode

Predicate-result merges common CR testing with predication, saving on
instruction count.  In essence, a Condition Register Field test
is performed, and if it fails it is considered to have been
*as if* the destination predicate bit was zero.
Arithmetic and Logical Pred-result is covered in [[sv/normal]]

## pred-result mode on CR ops

CR operations (mtcr, crand, cror) may be Vectorised,
predicated, and also pred-result mode applied to it.  
Vectorisation applies to 4-bit CR Fields which are treated as
elements, not the individual bits of the 32-bit CR.
CR ops and how to identify them is described in [[sv/cr_ops]]

# CR Operations

CRs are slightly more involved than INT or FP registers due to the
possibility for indexing individual bits (crops BA/BB/BT).  Again however
the access pattern needs to be understandable in relation to v3.0B / v3.1B
numbering, with a clear linear relationship and mapping existing when
SV is applied.

## CR EXTRA mapping table and algorithm

Numbering relationships for CR fields are already complex due to being
in BE format (*the relationship is not clearly explained in the v3.0B
or v3.1B specification*).  However with some care and consideration
the exact same mapping used for INT and FP regfiles may be applied,
just to the upper bits, as explained below.  The notation
`CR{field number}` is used to indicate access to a particular
Condition Register Field (as opposed to the notation `CR[bit]`
which accesses one bit of the 32 bit Power ISA v3.0B
Condition Register)

In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits.  The top 3 bits (0:2)
select one of the 8 CRs; the bottom 2 bits (3:4) select one of 4 bits
*in* that CR.  The numbering was determined (after 4 months of
analysis and research) to be as follows:

    CR_index = 7-(BA>>2)      # top 3 bits but BE
    bit_index = 3-(BA & 0b11) # low 2 bits but BE
    CR_reg = CR{CR_index}     # get the CR
    # finally get the bit from the CR.
    CR_bit = (CR_reg & (1<<bit_index)) != 0

When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
applies, **not** the CR\_bit portion (bits 3:4):

    if extra3_mode:
        spec = EXTRA3
    else:
        spec = EXTRA2<<1 | 0b0
    if spec[0]:
       # vector constructs "BA[0:2] spec[1:2] 00 BA[3:4]"
       return ((BA >> 2)<<6) | # hi 3 bits shifted up
              (spec[1:2]<<4) | # to make room for these
              (BA & 0b11)      # CR_bit on the end
    else:
       # scalar constructs "00 spec[1:2] BA[0:4]"
       return (spec[1:2] << 5) | BA

Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
algorithm to determin CR\_reg is modified to as follows:

    CR_index = 7-(BA>>2)      # top 3 bits but BE
    if spec[0]:
        # vector mode, 0-124 increments of 4
        CR_index = (CR_index<<4) | (spec[1:2] << 2)
    else:
        # scalar mode, 0-32 increments of 1
        CR_index = (spec[1:2]<<3) | CR_index
    # same as for v3.0/v3.1 from this point onwards
    bit_index = 3-(BA & 0b11) # low 2 bits but BE
    CR_reg = CR{CR_index}     # get the CR
    # finally get the bit from the CR.
    CR_bit = (CR_reg & (1<<bit_index)) != 0

Note here that the decoding pattern to determine CR\_bit does not change.

Note: high-performance implementations may read/write Vectors of CRs in
batches of aligned 32-bit chunks (CR0-7, CR7-15).  This is to greatly
simplify internal design.  If instructions are issued where CR Vectors
do not start on a 32-bit aligned boundary, performance may be affected.

## CR fields as inputs/outputs of vector operations

CRs (or, the arithmetic operations associated with them)
may be marked as Vectorised or Scalar.  When Rc=1 in arithmetic operations that have no explicit EXTRA to cover the CR, the CR is Vectorised if the destination is Vectorised.  Likewise if the destination is scalar then so is the CR.

When vectorized, the CR inputs/outputs are sequentially read/written
to 4-bit CR fields.  Vectorised Integer results, when Rc=1, will begin
writing to CR8 (TBD evaluate) and increase sequentially from there.
This is so that:

* implementations may rely on the Vector CRs being aligned to 8. This
  means that CRs may be read or written in aligned batches of 32 bits
  (8 CRs per batch), for high performance implementations.
* scalar Rc=1 operation (CR0, CR1) and callee-saved CRs (CR2-4) are not
  overwritten by vector Rc=1 operations except for very large VL
* CR-based predication, from CR32, is also not interfered with
  (except by large VL).

However when the SV result (destination) is marked as a scalar by the
EXTRA field the *standard* v3.0B behaviour applies: the accompanying
CR when Rc=1 is written to.  This is CR0 for integer operations and CR1
for FP operations.

Note that yes, the CR Fields are genuinely Vectorised.  Unlike in SIMD VSX which
has a single CR (CR6) for a given SIMD result, SV Vectorised OpenPOWER
v3.0B scalar operations produce a **tuple** of element results: the
result of the operation as one part of that element *and a corresponding
CR element*.  Greatly simplified pseudocode:

    for i in range(VL):
         # calculate the vector result of an add
         iregs[RT+i] = iregs[RA+i] + iregs[RB+i]
         # now calculate CR bits
         CRs{8+i}.eq = iregs[RT+i] == 0
         CRs{8+i}.gt = iregs[RT+i] > 0
         ... etc

If a "cumulated" CR based analysis of results is desired (a la VSX CR6)
then a followup instruction must be performed, setting "reduce" mode on
the Vector of CRs, using cr ops (crand, crnor) to do so.  This provides far
more flexibility in analysing vectors than standard Vector ISAs.  Normal
Vector ISAs are typically restricted to "were all results nonzero" and
"were some results nonzero". The application of mapreduce to Vectorised
cr operations allows far more sophisticated analysis, particularly in
conjunction with the new crweird operations see [[sv/cr_int_predication]].

Note in particular that the use of a separate instruction in this way
ensures that high performance multi-issue OoO inplementations do not
have the computation of the cumulative analysis CR as a bottleneck and
hindrance, regardless of the length of VL.

Additionally,
SVP64 [[sv/branches]] may be used, even when the branch itself is to
the following instruction.  The combined side-effects of CTR reduction
and VL truncation provide several benefits.

(see [[discussion]].  some alternative schemes are described there)

## Rc=1 when SUBVL!=1

sub-vectors are effectively a form of Packed SIMD (length 2 to 4). Only 1 bit of
predicate is allocated per subvector; likewise only one CR is allocated
per subvector.

This leaves a conundrum as to how to apply CR computation per subvector,
when normally Rc=1 is exclusively applied to scalar elements.  A solution
is to perform a bitwise OR or AND of the subvector tests.  Given that
OE is ignored in SVP64, this field may (when available) be used to select OR or
AND behavior.

### Table of CR fields

CR[i] is the notation used by the OpenPower spec to refer to CR field #i,
so FP instructions with Rc=1 write to CR[1] aka SVCR1_000.

CRs are not stored in SPRs: they are registers in their own right.
Therefore context-switching the full set of CRs involves a Vectorised
mfcr or mtcr, using VL=64, elwidth=8 to do so.  This is exactly as how
scalar OpenPOWER context-switches CRs: it is just that there are now
more of them.

The 64 SV CRs are arranged similarly to the way the 128 integer registers
are arranged.  TODO a python program that auto-generates a CSV file
which can be included in a table, which is in a new page (so as not to
overwhelm this one). [[svp64/cr_names]]

# Register Profiles

**NOTE THIS TABLE SHOULD NO LONGER BE HAND EDITED** see
<https://bugs.libre-soc.org/show_bug.cgi?id=548> for details.

Instructions are broken down by Register Profiles as listed in the
following auto-generated page: [[opcode_regs_deduped]].  "Non-SV"
indicates that the operations with this Register Profile cannot be
Vectorised (mtspr, bc, dcbz, twi)

TODO generate table which will be here [[svp64/reg_profiles]]

# SV pseudocode illilustration

## Single-predicated Instruction

illustration of normal mode add operation: zeroing not included, elwidth
overrides not included.  if there is no predicate, it is set to all 1s

    function op_add(rd, rs1, rs2) # add not VADD!
      int i, id=0, irs1=0, irs2=0; predval = get_pred_val(FALSE, rd);
      for (i = 0; i < VL; i++)
        STATE.srcoffs = i # save context if (predval & 1<<i) # predication
        uses intregs
           ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2]; if (!int_vec[rd
           ].isvec) break;
        if (rd.isvec)  { id += 1; } if (rs1.isvec)  { irs1 += 1; } if
        (rs2.isvec)  { irs2 += 1; } if (id == VL or irs1 == VL or irs2 ==
        VL) {
          # end VL hardware loop STATE.srcoffs = 0; # reset return;
        }

This has several modes:

* RT.v = RA.v RB.v * RT.v = RA.v RB.s (and RA.s RB.v) * RT.v = RA.s RB.s *
RT.s = RA.v RB.v * RT.s = RA.v RB.s (and RA.s RB.v) * RT.s = RA.s RB.s

All of these may be predicated.  Vector-Vector is straightfoward.
When one of source is a Vector and the other a Scalar, it is clear that
each element of the Vector source should be added to the Scalar source,
each result placed into the Vector (or, if the destination is a scalar,
only the first nonpredicated result).

The one that is not obvious is RT=vector but both RA/RB=scalar.
Here this acts as a "splat scalar result", copying the same result into
all nonpredicated result elements.  If a fixed destination scalar was
intended, then an all-Scalar operation should be used.

See <https://bugs.libre-soc.org/show_bug.cgi?id=552>

# Assembly Annotation

Assembly code annotation is required for SV to be able to successfully
mark instructions as "prefixed".

A reasonable (prototype) starting point:

    svp64 [field=value]*

Fields:

* ew=8/16/32 - element width
* sew=8/16/32 - source element width
* vec=2/3/4 - SUBVL
* mode=reduce/satu/sats/crpred
* pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne
* spred={reg spec}

similar to x86 "rex" prefix.

For actual assembler:

    sv.asmcode/mode.vec{N}.ew=8,sw=16,m={pred},sm={pred} reg.v, src.s

Qualifiers:

* m={pred}: predicate mask mode
* sm={pred}: source-predicate mask mode (only allowed in Twin-predication)
* vec{N}: vec2 OR vec3 OR vec4 - sets SUBVL=2/3/4
* ew={N}: ew=8/16/32 - sets elwidth override
* sw={N}: sw=8/16/32 - sets source elwidth override
* ff={xx}: see fail-first mode
* pr={xx}: see predicate-result mode
* sat{x}: satu / sats - see saturation mode
* mr: see map-reduce mode
* mr.svm see map-reduce with sub-vector mode
* crm: see map-reduce CR mode
* crm.svm see map-reduce CR with sub-vector mode
* sz: predication with source-zeroing
* dz: predication with dest-zeroing

For modes:

* pred-result:
  - pm=lt/gt/le/ge/eq/ne/so/ns OR
  - pm=RC1 OR pm=~RC1
* fail-first
  - ff=lt/gt/le/ge/eq/ne/so/ns OR
  - ff=RC1 OR ff=~RC1
* saturation:
  - sats
  - satu
* map-reduce:
  - mr OR crm: "normal" map-reduce mode or CR-mode.
  - mr.svm OR crm.svm: when vec2/3/4 set, sub-vector mapreduce is enabled

# Proposed Parallel-reduction algorithm

```
/// reference implementation of proposed SimpleV reduction semantics.
///
                // reduction operation -- we still use this algorithm even
                // if the reduction operation isn't associative or
                // commutative.
/// `temp_pred` is a user-visible Vector Condition register 
///
/// all input arrays have length `vl`
def reduce(  vl,  vec, pred, pred,):
    step = 1;
    while step < vl
        step *= 2;
        for i in (0..vl).step_by(step)
            other = i + step / 2;
            other_pred = other < vl && pred[other];
            if pred[i] && other_pred
                vec[i] += vec[other];
            else if other_pred
                vec[i] = vec[other];
            pred[i] |= other_pred;

def reduce(  vl,  vec, pred, pred,):
    j = 0
    vi = [] # array of lookup indices to skip nonpredicated
    for i, pbit in enumerate(pred):
       if pbit:
           vi[j] = i
           j += 1
    step = 2
    while step <= vl
        halfstep = step // 2
        for i in (0..vl).step_by(step)
            other = vi[i + halfstep]
            i = vi[i]
            other_pred = other < vl && pred[other]
            if pred[i] && other_pred
                vec[i] += vec[other]
            pred[i] |= other_pred
         step *= 2

```