f4b7f14b694afa8fd81496480de5e4303cc450d1
[libreriscv.git] / openpower / transcendentals.mdwn
1 # DRAFT Scalar Transcendentals
2
3 Summary:
4
5 *This proposal extends Power ISA scalar floating point operations to
6 add IEEE754 transcendental functions (pow, log etc) and trigonometric
7 functions (sin, cos etc). These functions are also 98% shared with the
8 Khronos Group OpenCL Extended Instruction Set.*
9
10 Authors/Contributors:
11
12 * Luke Kenneth Casson Leighton
13 * Jacob Lifshay
14 * Dan Petroski
15 * Mitch Alsup
16 * Allen Baum
17 * Andrew Waterman
18 * Luis Vitorio Cargnini
19
20 [[!toc levels=2]]
21
22 See:
23
24 * <http://bugs.libre-soc.org/show_bug.cgi?id=127>
25 * <https://bugs.libre-soc.org/show_bug.cgi?id=899> transcendentals in simulator
26 * <https://bugs.libre-soc.org/show_bug.cgi?id=923> under review
27 * <https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html>
28 * [[power_trans_ops]] for opcode listing.
29
30 Extension subsets:
31
32 TODO: rename extension subsets -- we're not on RISC-V anymore.
33
34 * **Zftrans**: standard transcendentals (best suited to 3D)
35 * **ZftransExt**: extra functions (useful, not generally needed for 3D,
36 can be synthesised using Ztrans)
37 * **Ztrigpi**: trig. xxx-pi sinpi cospi tanpi
38 * **Ztrignpi**: trig non-xxx-pi sin cos tan
39 * **Zarctrigpi**: arc-trig. a-xxx-pi: atan2pi asinpi acospi
40 * **Zarctrignpi**: arc-trig. non-a-xxx-pi: atan2, asin, acos
41 * **Zfhyp**: hyperbolic/inverse-hyperbolic. sinh, cosh, tanh, asinh,
42 acosh, atanh (can be synthesised - see below)
43 * **ZftransAdv**: much more complex to implement in hardware
44 * **Zfrsqrt**: Reciprocal square-root.
45
46 Minimum recommended requirements for 3D: Zftrans, Ztrignpi,
47 Zarctrignpi, with Ztrigpi and Zarctrigpi as augmentations.
48
49 Minimum recommended requirements for Mobile-Embedded 3D:
50 Ztrignpi, Zftrans, with Ztrigpi as an augmentation.
51
52 The Platform Requirements for 3D are driven by cost competitive
53 factors and it is the Trademarked Vulkan Specification that provides
54 clear direction for 3D GPU markets, but nothing else (IEEE754).
55 Implementors must note that minimum
56 Compliance with the Third Party Vulkan Specification (for power-area competitive
57 reasons with other 3D GPU manufacturers) will not qualify for strict IEEE754 accuracy Compliance or vice-versa.
58
59 Implementors **must** make it clear which accuracy level is implemented and provide a switching mechanism and throw Illegal Instruction traps if fully compliant accuracy cannot be achieved.
60 It is also the Implementor's responsibility to comply with all Third Party Certification Marks and Trademarks (Vulkan, OpenCL). Nothing in this specification in any way implies that any Third Party Certification Mark Compliance is granted, nullified, altered or overridden by this document.
61
62
63 # TODO:
64
65 * Decision on accuracy, moved to [[zfpacc_proposal]]
66 <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002355.html>
67 * Errors **MUST** be repeatable.
68 * How about four Platform Specifications? 3DUNIX, UNIX, 3DEmbedded and Embedded?
69 <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002361.html>
70 Accuracy requirements for dual (triple) purpose implementations must
71 meet the higher standard.
72 * Reciprocal Square-root is in its own separate extension (Zfrsqrt) as
73 it is desirable on its own by other implementors. This to be evaluated.
74
75 # Requirements <a name="requirements"></a>
76
77 This proposal is designed to meet a wide range of extremely diverse
78 needs, allowing implementors from all of them to benefit from the tools
79 and hardware cost reductions associated with common standards adoption
80 in Power ISA (primarily IEEE754 and Vulkan).
81
82 **The use-cases are**:
83
84 * 3D GPUs
85 * Numerical Computation
86 * (Potentially) A.I. / Machine-learning (1)
87
88 (1) although approximations suffice in this field, making it more likely
89 to use a custom extension. High-end ML would inherently definitely
90 be excluded.
91
92 **The power and die-area requirements vary from**:
93
94 * Ultra-low-power (smartwatches where GPU power budgets are in milliwatts)
95 * Mobile-Embedded (good performance with high efficiency for battery life)
96 * Desktop Computing
97 * Server / HPC / Supercomputing
98
99 **The software requirements are**:
100
101 * Full public integration into GNU math libraries (libm)
102 * Full public integration into well-known Numerical Computation systems (numpy)
103 * Full public integration into upstream GNU and LLVM Compiler toolchains
104 * Full public integration into Khronos OpenCL SPIR-V compatible Compilers
105 seeking public Certification and Endorsement from the Khronos Group
106 under their Trademarked Certification Programme.
107
108 # Proposed Opcodes vs Khronos OpenCL vs IEEE754-2019<a name="khronos_equiv"></a>
109
110 This list shows the (direct) equivalence between proposed opcodes,
111 their Khronos OpenCL equivalents, and their IEEE754-2019 equivalents.
112 98% of the opcodes in this proposal that are in the IEEE754-2019 standard
113 are present in the Khronos Extended Instruction Set.
114
115 See
116 <https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html>
117 and <https://ieeexplore.ieee.org/document/8766229>
118
119 * Special FP16 opcodes are *not* being proposed, except by indirect / inherent
120 use of elwidth overrides that is already present in the SVP64 Specification.
121 * "Native" opcodes are *not* being proposed: implementors will be expected
122 to use the (equivalent) proposed opcode covering the same function.
123 * "Fast" opcodes are *not* being proposed, because the Khronos Specification
124 fast\_length, fast\_normalise and fast\_distance OpenCL opcodes require
125 vectors (or can be done as scalar operations using other Power ISA
126 instructions).
127
128 The OpenCL FP32 opcodes are **direct** equivalents to the proposed opcodes.
129 Deviation from conformance with the Khronos Specification - including the
130 Khronos Specification accuracy requirements - is not an option, as it
131 results in non-compliance, and the vendor may not use the Trademarked words
132 "Vulkan" etc. in conjunction with their product.
133
134 IEEE754-2019 Table 9.1 lists "additional mathematical operations".
135 Interestingly the only functions missing when compared to OpenCL are
136 compound, exp2m1, exp10m1, log2p1, log10p1, pown (integer power) and powr.
137
138 |opcode |OpenCL FP32|OpenCL FP16|OpenCL native|IEEE754 |Power ISA |My 66000 ISA |
139 |------------|-----------|-----------|-------------|-------------- |------------------------|-------------|
140 |fsin |sin |half\_sin |native\_sin |sin |NONE |sin |
141 |fcos |cos |half\_cos |native\_cos |cos |NONE |cos |
142 |ftan |tan |half\_tan |native\_tan |tan |NONE |tan |
143 |NONE (1) |sincos |NONE |NONE |NONE |NONE | |
144 |fasin |asin |NONE |NONE |asin |NONE |asin |
145 |facos |acos |NONE |NONE |acos |NONE |acos |
146 |fatan |atan |NONE |NONE |atan |NONE |atan |
147 |fsinpi |sinpi |NONE |NONE |sinPi |NONE |sinpi |
148 |fcospi |cospi |NONE |NONE |cosPi |NONE |cospi |
149 |ftanpi |tanpi |NONE |NONE |tanPi |NONE |tanpi |
150 |fasinpi |asinpi |NONE |NONE |asinPi |NONE |asinpi |
151 |facospi |acospi |NONE |NONE |acosPi |NONE |acospi |
152 |fatanpi |atanpi |NONE |NONE |atanPi |NONE |atanpi |
153 |fsinh |sinh |NONE |NONE |sinh |NONE | |
154 |fcosh |cosh |NONE |NONE |cosh |NONE | |
155 |ftanh |tanh |NONE |NONE |tanh |NONE | |
156 |fasinh |asinh |NONE |NONE |asinh |NONE | |
157 |facosh |acosh |NONE |NONE |acosh |NONE | |
158 |fatanh |atanh |NONE |NONE |atanh |NONE | |
159 |fatan2 |atan2 |NONE |NONE |atan2 |NONE |atan2 |
160 |fatan2pi |atan2pi |NONE |NONE |atan2pi |NONE |atan2pi |
161 |frsqrt |rsqrt |half\_rsqrt|native\_rsqrt|rSqrt |fsqrte, fsqrtes (4) |rsqrt |
162 |fcbrt |cbrt |NONE |NONE |NONE (2) |NONE | |
163 |fexp2 |exp2 |half\_exp2 |native\_exp2 |exp2 |NONE |exp2 |
164 |flog2 |log2 |half\_log2 |native\_log2 |log2 |NONE |ln2 |
165 |fexpm1 |expm1 |NONE |NONE |expm1 |NONE |expm1 |
166 |flog1p |log1p |NONE |NONE |logp1 |NONE |logp1 |
167 |fexp |exp |half\_exp |native\_exp |exp |NONE |exp |
168 |flog |log |half\_log |native\_log |log |NONE |ln |
169 |fexp10 |exp10 |half\_exp10|native\_exp10|exp10 |NONE |exp10 |
170 |flog10 |log10 |half\_log10|native\_log10|log10 |NONE |log |
171 |fpow |pow |NONE |NONE |pow |NONE |pow |
172 |fpown |pown |NONE |NONE |pown |NONE | |
173 |fpowr |powr |half\_powr |native\_powr |powr |NONE | |
174 |frootn |rootn |NONE |NONE |rootn |NONE | |
175 |fhypot |hypot |NONE |NONE |hypot |NONE | |
176 |frecip |NONE |half\_recip|native\_recip|NONE (3) |fre, fres (4) |rcp |
177 |NONE |NONE |NONE |NONE |compound |NONE | |
178 |fexp2m1 |NONE |NONE |NONE |exp2m1 |NONE |exp2m1 |
179 |fexp10m1 |NONE |NONE |NONE |exp10m1 |NONE |exp10m1 |
180 |flog2p1 |NONE |NONE |NONE |log2p1 |NONE |ln2p1 |
181 |flog10p1 |NONE |NONE |NONE |log10p1 |NONE |logp1 |
182 |fminnum08 |fmin |fmin |NONE |minNum |xsmindp (5) | |
183 |fmaxnum08 |fmax |fmax |NONE |maxNum |xsmaxdp (5) | |
184 |fmin19 |fmin |fmin |NONE |minimum |NONE |fmin |
185 |fmax19 |fmax |fmax |NONE |maximum |NONE |fmax |
186 |fminnum19 |fmin |fmin |NONE |minimumNumber |vminfp (6), xsminjdp (5)| |
187 |fmaxnum19 |fmax |fmax |NONE |maximumNumber |vmaxfp (6), xsmaxjdp (5)| |
188 |fminc |fmin |fmin |NONE |NONE |xsmincdp (5) |fmin* |
189 |fmaxc |fmax |fmax |NONE |NONE |xsmaxcdp (5) |fmax* |
190 |fminmagnum08|minmag |minmag |NONE |minNumMag |NONE | |
191 |fmaxmagnum08|maxmag |maxmag |NONE |maxNumMag |NONE | |
192 |fminmag19 |minmag |minmag |NONE |minimumMagnitude |NONE | |
193 |fmaxmag19 |maxmag |maxmag |NONE |maximumMagnitude |NONE | |
194 |fminmagnum19|minmag |minmag |NONE |minimumMagnitudeNumber|NONE | |
195 |fmaxmagnum19|maxmag |maxmag |NONE |maximumMagnitudeNumber|NONE | |
196 |fminmagc |minmag |minmag |NONE |NONE |NONE | |
197 |fmaxmagc |maxmag |maxmag |NONE |NONE |NONE | |
198 |fmod |fmod |fmod | |NONE |NONE | |
199 |fremainder |remainder |remainder | |remainder |NONE | |
200
201 from Mitch Alsup:
202
203 * Brian's LLVM compiler converts fminc and fmaxc into fmin and fmax instructions
204 These are all IEEE 754-2019 compliant
205 These are native instructions not extensions
206 All listed functions are available in both F32 and F64 formats.
207 THere is some confusion (in my head) abouot fmin and fmax. I intend both instruction to perform 754-2019 semantics--
208 but I don know if this is minimum/maximum or minimumNumber/maximumNumber.
209 fmad and remainder are a 2-instruction sequence--don't know how to "edit it in"
210
211
212 Note (1) fsincos is macro-op fused (see below).
213
214 Note (2) synthesised in IEEE754-2019 as "rootn(x, 3)"
215
216 Note (3) synthesised in IEEE754-2019 using "1.0 / x"
217
218 Note (4) these are estimate opcodes that help accelerate
219 software emulation
220
221 Note (5) f64-only (though can be used on f32 stored in f64 format), requires VSX.
222
223 Note (6) 4xf32-only, requires VMX.
224
225 ## List of 2-arg opcodes
226
227 | opcode | Description | pseudocode | Extension |
228 | ------ | ---------------- | ---------------- | ----------- |
229 | fatan2 | atan2 arc tangent | FRT = atan2(FRB, FRA) | Zarctrignpi |
230 | fatan2pi | atan2 arc tangent / pi | FRT = atan2(FRB, FRA) / pi | Zarctrigpi |
231 | fpow | x power of y | FRT = pow(FRA, FRB) | ZftransAdv |
232 | fpown | x power of n (n int) | FRT = pow(FRA, RB) | ZftransAdv |
233 | fpowr | x power of y (x +ve) | FRT = exp(FRA log(FRB)) | ZftransAdv |
234 | frootn | x power 1/n (n integer) | FRT = pow(FRA, 1/RB) | ZftransAdv |
235 | fhypot | hypotenuse | FRT = sqrt(FRA^2 + FRB^2) | ZftransAdv |
236 | fminnum08 | IEEE 754-2008 minNum | FRT = minNum(FRA, FRB) (1) | TBD |
237 | fmaxnum08 | IEEE 754-2008 maxNum | FRT = maxNum(FRA, FRB) (1) | TBD |
238 | fmin19 | IEEE 754-2019 minimum | FRT = minimum(FRA, FRB) | TBD |
239 | fmax19 | IEEE 754-2019 maximum | FRT = maximum(FRA, FRB) | TBD |
240 | fminnum19 | IEEE 754-2019 minimumNumber | FRT = minimumNumber(FRA, FRB) | TBD |
241 | fmaxnum19 | IEEE 754-2019 maximumNumber | FRT = maximumNumber(FRA, FRB) | TBD |
242 | fminc | C ternary-op minimum | FRT = FRA \< FRB ? FRA : FRB | TBD |
243 | fmaxc | C ternary-op maximum | FRT = FRA > FRB ? FRA : FRB | TBD |
244 | fminmagnum08 | IEEE 754-2008 minNumMag | FRT = minmaxmag(FRA, FRB, False, fminnum08) (2)| TBD |
245 | fmaxmagnum08 | IEEE 754-2008 maxNumMag | FRT = minmaxmag(FRA, FRB, True, fmaxnum08) (2) | TBD |
246 | fminmag19 | IEEE 754-2019 minimumMagnitude | FRT = minmaxmag(FRA, FRB, False, fmin19) (2) | TBD |
247 | fmaxmag19 | IEEE 754-2019 maximumMagnitude | FRT = minmaxmag(FRA, FRB, True, fmax19) (2) | TBD |
248 | fminmagnum19 | IEEE 754-2019 minimumMagnitudeNumber | FRT = minmaxmag(FRA, FRB, False, fminnum19) (2)| TBD |
249 | fmaxmagnum19 | IEEE 754-2019 maximumMagnitudeNumber | FRT = minmaxmag(FRA, FRB, True, fmaxnum19) (2) | TBD |
250 | fminmagc | C ternary-op minimum magnitude | FRT = minmaxmag(FRA, FRB, False, fminc) (2) | TBD |
251 | fmaxmagc | C ternary-op maximum magnitude | FRT = minmaxmag(FRA, FRB, True, fmaxc) (2) | TBD |
252 | fmod | modulus | FRT = fmod(FRA, FRB) | TBD |
253 | fremainder | IEEE 754 remainder | FRT = remainder(FRA, FRB) | TBD |
254
255 Note (1): for the purposes of minNum/maxNum, -0.0 is defined to be less than +0.0. This is left unspecified in IEEE 754-2008.
256
257 Note (2): minmaxmag(x, y, cmp, fallback) is defined as:
258
259 ```python
260 def minmaxmag(x, y, is_max, fallback):
261 a = abs(x) < abs(y)
262 b = abs(x) > abs(y)
263 if is_max:
264 a, b = b, a # swap
265 if a:
266 return x
267 if b:
268 return y
269 # equal magnitudes, or NaN input(s)
270 return fallback(x, y)
271 ```
272
273 ## List of 1-arg transcendental opcodes
274
275 | opcode | Description | pseudocode | Extension |
276 | ------ | ---------------- | ---------------- | ---------- |
277 | frsqrt | Reciprocal Square-root | FRT = sqrt(FRA) | Zfrsqrt |
278 | fcbrt | Cube Root | FRT = pow(FRA, 1.0 / 3) | ZftransAdv |
279 | frecip | Reciprocal | FRT = 1.0 / FRA | Zftrans |
280 | fexp2m1 | power-2 minus 1 | FRT = pow(2, FRA) - 1.0 | ZftransExt |
281 | flog2p1 | log2 plus 1 | FRT = log(2, 1 + FRA) | ZftransExt |
282 | fexp2 | power-of-2 | FRT = pow(2, FRA) | Zftrans |
283 | flog2 | log2 | FRT = log(2. FRA) | Zftrans |
284 | fexpm1 | exponential minus 1 | FRT = pow(e, FRA) - 1.0 | ZftransExt |
285 | flog1p | log plus 1 | FRT = log(e, 1 + FRA) | ZftransExt |
286 | fexp | exponential | FRT = pow(e, FRA) | ZftransExt |
287 | flog | natural log (base e) | FRT = log(e, FRA) | ZftransExt |
288 | fexp10m1 | power-10 minus 1 | FRT = pow(10, FRA) - 1.0 | ZftransExt |
289 | flog10p1 | log10 plus 1 | FRT = log(10, 1 + FRA) | ZftransExt |
290 | fexp10 | power-of-10 | FRT = pow(10, FRA) | ZftransExt |
291 | flog10 | log base 10 | FRT = log(10, FRA) | ZftransExt |
292
293 ## List of 1-arg trigonometric opcodes
294
295 | opcode | Description | pseudocode | Extension |
296 | -------- | ------------------------ | ------------------------ | ----------- |
297 | fsin | sin (radians) | FRT = sin(FRA) | Ztrignpi |
298 | fcos | cos (radians) | FRT = cos(FRA) | Ztrignpi |
299 | ftan | tan (radians) | FRT = tan(FRA) | Ztrignpi |
300 | fasin | arcsin (radians) | FRT = asin(FRA) | Zarctrignpi |
301 | facos | arccos (radians) | FRT = acos(FRA) | Zarctrignpi |
302 | fatan | arctan (radians) | FRT = atan(FRA) | Zarctrignpi |
303 | fsinpi | sin times pi | FRT = sin(pi * FRA) | Ztrigpi |
304 | fcospi | cos times pi | FRT = cos(pi * FRA) | Ztrigpi |
305 | ftanpi | tan times pi | FRT = tan(pi * FRA) | Ztrigpi |
306 | fasinpi | arcsin / pi | FRT = asin(FRA) / pi | Zarctrigpi |
307 | facospi | arccos / pi | FRT = acos(FRA) / pi | Zarctrigpi |
308 | fatanpi | arctan / pi | FRT = atan(FRA) / pi | Zarctrigpi |
309 | fsinh | hyperbolic sin (radians) | FRT = sinh(FRA) | Zfhyp |
310 | fcosh | hyperbolic cos (radians) | FRT = cosh(FRA) | Zfhyp |
311 | ftanh | hyperbolic tan (radians) | FRT = tanh(FRA) | Zfhyp |
312 | fasinh | inverse hyperbolic sin | FRT = asinh(FRA) | Zfhyp |
313 | facosh | inverse hyperbolic cos | FRT = acosh(FRA) | Zfhyp |
314 | fatanh | inverse hyperbolic tan | FRT = atanh(FRA) | Zfhyp |
315
316 [[!inline pages="openpower/power_trans_ops" raw=yes ]]
317
318 # Subsets
319
320 The full set is based on the Khronos OpenCL opcodes. If implemented
321 entirely it would be too much for both Embedded and also 3D.
322
323 The subsets are organised by hardware complexity, need (3D, HPC), however
324 due to synthesis producing inaccurate results at the range limits,
325 the less common subsets are still required for IEEE754 HPC.
326
327 MALI Midgard, an embedded / mobile 3D GPU, for example only has the
328 following opcodes:
329
330 E8 - fatan_pt2
331 F0 - frcp (reciprocal)
332 F2 - frsqrt (inverse square root, 1/sqrt(x))
333 F3 - fsqrt (square root)
334 F4 - fexp2 (2^x)
335 F5 - flog2
336 F6 - fsin1pi
337 F7 - fcos1pi
338 F9 - fatan_pt1
339
340 These in FP32 and FP16 only: no FP64 hardware, at all.
341
342 Vivante Embedded/Mobile 3D (etnaviv
343 <https://github.com/laanwj/etna_viv/blob/master/rnndb/isa.xml>)
344 only has the following:
345
346 sin, cos2pi
347 cos, sin2pi
348 log2, exp
349 sqrt and rsqrt
350 recip.
351
352 It also has fast variants of some of these, as a CSR Mode.
353
354 AMD's R600 GPU (R600\_Instruction\_Set\_Architecture.pdf) and the
355 RDNA ISA (RDNA\_Shader\_ISA\_5August2019.pdf, Table 22, Section 6.3) have:
356
357 COS2PI (appx)
358 EXP2
359 LOG (IEEE754)
360 RECIP
361 RSQRT
362 SQRT
363 SIN2PI (appx)
364
365 AMD RDNA has F16 and F32 variants of all the above, and also has F64
366 variants of SQRT, RSQRT and RECIP. It is interesting that even the
367 modern high-end AMD GPU does not have TAN or ATAN, where MALI Midgard
368 does.
369
370 Also a general point, that customised optimised hardware targetting
371 FP32 3D with less accuracy simply can neither be used for IEEE754 nor
372 for FP64 (except as a starting point for hardware or software driven
373 Newton Raphson or other iterative method).
374
375 Also in cost/area sensitive applications even the extra ROM lookup tables
376 for certain algorithms may be too costly.
377
378 These wildly differing and incompatible driving factors lead to the
379 subset subdivisions, below.
380
381 ## Transcendental Subsets
382
383 ### Zftrans
384
385 LOG2 EXP2 RECIP RSQRT
386
387 Zftrans contains the minimum standard transcendentals best suited to
388 3D. They are also the minimum subset for synthesising log10, exp10,
389 exp1m, log1p, the hyperbolic trigonometric functions sinh and so on.
390
391 They are therefore considered "base" (essential) transcendentals.
392
393 ### ZftransExt
394
395 LOG, EXP, EXP10, LOG10, LOGP1, EXP1M
396
397 These are extra transcendental functions that are useful, not generally
398 needed for 3D, however for Numerical Computation they may be useful.
399
400 Although they can be synthesised using Ztrans (LOG2 multiplied
401 by a constant), there is both a performance penalty as well as an
402 accuracy penalty towards the limits, which for IEEE754 compliance is
403 unacceptable. In particular, LOG(1+FRA) in hardware may give much better
404 accuracy at the lower end (very small FRA) than LOG(FRA).
405
406 Their forced inclusion would be inappropriate as it would penalise
407 embedded systems with tight power and area budgets. However if they
408 were completely excluded the HPC applications would be penalised on
409 performance and accuracy.
410
411 Therefore they are their own subset extension.
412
413 ### Zfhyp
414
415 SINH, COSH, TANH, ASINH, ACOSH, ATANH
416
417 These are the hyperbolic/inverse-hyperbolic functions. Their use in 3D
418 is limited.
419
420 They can all be synthesised using LOG, SQRT and so on, so depend
421 on Zftrans. However, once again, at the limits of the range, IEEE754
422 compliance becomes impossible, and thus a hardware implementation may
423 be required.
424
425 HPC and high-end GPUs are likely markets for these.
426
427 ### ZftransAdv
428
429 CBRT, POW, POWN, POWR, ROOTN
430
431 These are simply much more complex to implement in hardware, and typically
432 will only be put into HPC applications.
433
434 * **Zfrsqrt**: Reciprocal square-root.
435
436 ## Trigonometric subsets
437
438 ### Ztrigpi vs Ztrignpi
439
440 * **Ztrigpi**: SINPI COSPI TANPI
441 * **Ztrignpi**: SIN COS TAN
442
443 Ztrignpi are the basic trigonometric functions through which all others
444 could be synthesised, and they are typically the base trigonometrics
445 provided by GPUs for 3D, warranting their own subset.
446
447 (programmerjake: actually, all other GPU ISAs mentioned in this document have sinpi/cospi or equivalent, and often not sin/cos, because sinpi/cospi are actually *waay* easier to implement because range reduction is simply a bitwise mask, whereas for sin/cos range reduction is a full division by pi)
448
449 (Mitch: My patent USPTO 10,761,806 shows that the above statement is no longer true.)
450
451
452 In the case of the Ztrigpi subset, these are commonly used in for loops
453 with a power of two number of subdivisions, and the cost of multiplying
454 by PI inside each loop (or cumulative addition, resulting in cumulative
455 errors) is not acceptable.
456
457 In for example CORDIC the multiplication by PI may be moved outside of
458 the hardware algorithm as a loop invariant, with no power or area penalty.
459
460 Again, therefore, if SINPI (etc.) were excluded, programmers would be
461 penalised by being forced to divide by PI in some circumstances. Likewise
462 if SIN were excluded, programmers would be penaslised by being forced
463 to *multiply* by PI in some circumstances.
464
465 Thus again, a slightly different application of the same general argument
466 applies to give Ztrignpi and Ztrigpi as subsets. 3D GPUs will almost
467 certainly provide both.
468
469 ### Zarctrigpi and Zarctrignpi
470
471 * **Zarctrigpi**: ATAN2PI ASINPI ACOSPI
472 * **Zarctrignpi**: ATAN2 ACOS ASIN
473
474 These are extra trigonometric functions that are useful in some
475 applications, but even for 3D GPUs, particularly embedded and mobile class
476 GPUs, they are not so common and so are typically synthesised, there.
477
478 Although they can be synthesised using Ztrigpi and Ztrignpi, there is,
479 once again, both a performance penalty as well as an accuracy penalty
480 towards the limits, which for IEEE754 compliance is unacceptable, yet
481 is acceptable for 3D.
482
483 Therefore they are their own subset extensions.
484
485 # Synthesis, Pseudo-code ops and macro-ops
486
487 The pseudo-ops are best left up to the compiler rather than being actual
488 pseudo-ops, by allocating one scalar FP register for use as a constant
489 (loop invariant) set to "1.0" at the beginning of a function or other
490 suitable code block.
491
492 * fsincos - fused macro-op between fsin and fcos (issued in that order).
493 * fsincospi - fused macro-op between fsinpi and fcospi (issued in that order).
494
495 fatanpi example pseudo-code:
496
497 fmvis ft0, 0x3F80 // upper bits of f32 1.0 (BF16)
498 fatan2pis FRT, FRA, ft0
499
500 Hyperbolic function example (obviates need for Zfhyp except for
501 high-performance or correctly-rounding):
502
503 ASINH( x ) = ln( x + SQRT(x**2+1))
504
505 # Evaluation and commentary
506
507 Moved to [[discussion]]
508