plru_tb.vhdl

   1 library vunit_lib;
   2 context vunit_lib.vunit_context;
   3
   4 library ieee;
   5 use ieee.std_logic_1164.all;
   6 use ieee.numeric_std.all;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12 entity plru_tb is
  13     generic (runner_cfg : string := runner_cfg_default);
  14 end plru_tb;
  15
  16 architecture behave of plru_tb is
  17     signal clk          : std_ulogic;
  18     signal rst          : std_ulogic;
  19
  20     constant clk_period : time := 10 ns;
  21     constant plru_bits  : integer := 3;
  22
  23     subtype plru_val_t  is std_ulogic_vector(plru_bits - 1 downto 0);
  24     subtype plru_tree_t is std_ulogic_vector(2 ** plru_bits - 2 downto 0);
  25     signal do_update : std_ulogic := '0';
  26     signal acc : plru_val_t;
  27     signal lru : plru_val_t;
  28     signal state : plru_tree_t;
  29     signal state_upd : plru_tree_t;
  30
  31 begin
  32     plrufn0: entity work.plrufn
  33         generic map(
  34             BITS => plru_bits
  35             )
  36         port map(
  37             acc => acc,
  38             tree_in => state,
  39             tree_out => state_upd,
  40             lru => lru
  41             );
  42
  43     clk_process: process
  44     begin
  45         clk <= '0';
  46         wait for clk_period/2;
  47         clk <= '1';
  48         wait for clk_period/2;
  49     end process;
  50
  51     rst_process: process
  52     begin
  53         rst <= '1';
  54         wait for 2*clk_period;
  55         rst <= '0';
  56         wait;
  57     end process;
  58
  59     plru_process: process(clk)
  60     begin
  61         if rising_edge(clk) then
  62             if rst = '1' then
  63                 state <= (others => '0');
  64             elsif do_update = '1' then
  65                 state <= state_upd;
  66             end if;
  67         end if;
  68     end process;
  69
  70     stim_process: process
  71         procedure test_access(acc_val: integer; expected: integer) is
  72         begin
  73             acc <= std_ulogic_vector(to_unsigned(acc_val, acc'length));
  74             do_update <= '1';
  75             wait for clk_period;
  76             info("accessed " & integer'image(acc_val) & " LRU=" & to_hstring(lru));
  77             check_equal(lru, expected, result("LRU ACC=" & integer'image(acc_val)));
  78         end procedure;
  79     begin
  80         test_runner_setup(runner, runner_cfg);
  81
  82         wait for 8*clk_period;
  83
  84         info("reset state:" & to_hstring(lru));
  85         check_equal(lru, 0, result("LRU "));
  86
  87         test_access(1, 4);
  88         test_access(2, 4);
  89         test_access(7, 0);
  90         test_access(4, 0);
  91         test_access(3, 6);
  92         test_access(5, 0);
  93         test_access(3, 6);
  94         test_access(5, 0);
  95         test_access(6, 0);
  96         test_access(0, 4);
  97         test_access(1, 4);
  98         test_access(2, 4);
  99         test_access(3, 4);
 100         test_access(4, 0);
 101         test_access(5, 0);
 102         test_access(6, 0);
 103         test_access(7, 0);
 104         test_access(6, 0);
 105         test_access(5, 0);
 106         test_access(4, 0);
 107         test_access(3, 7);
 108         test_access(2, 7);
 109         test_access(1, 7);
 110         test_access(0, 7);
 111
 112
 113         wait for clk_period;
 114         wait for clk_period;
 115
 116         test_runner_cleanup(runner);
 117     end process;
 118 end;