7 A fixed number of additional (hidden) bits, conceptually a
\textbf{namespace
},
8 set by way of a
\gls{CSR
} or other out-of-band mechanism,
9 that go directly and non-optionally
10 into the instruction decode phase, extending (in each implementation) the
11 opcode length to
16+N,
32+N,
48+N, where N is a hard fixed quantity on
12 a per-implementor basis.
16 Where the opcode is normally loaded from the location at the PC, the extra
17 bits, set via a CSR, are mandatorially appended to every instruction: hence why
18 they are described as "hidden" opcode bits, and as a
\textbf{namespace
}.
22 The parallels with c++
\textbf{using namespace
} are direct and clear.
23 Alternative conceptual ways to understand this concept include
24 \textbf{escape-sequencing
}.
28 TODO: reserve some bits which permit the namespace
\textbf{escape-sequence
} to
29 be relevant for a fixed number of instructions at a time. Caveat:
30 allowing such a countdown to cross branch-points is unwise (illegal
35 An example of a pre-existing
\textbf{namespace
} switch that has been in
36 prevalent use for several decades (
\gls{SPARC
} and other architectures):
37 dynamic runtime selectability of little-endian / big-endian
\textbf{meaning
}
38 of instructions by way of a
\textbf{mode switch
} instruction (of some kind).
42 That
\textbf{switch
} is in effect a
33rd (hidden) bit that is part of the opcode,
43 going directly into the mux / decode phase of instruction decode, and
44 thus qualifies categorically as a
\textbf{namespace
}. This proposal both formalises
45 and generalises that concept.
47 \section{Hypothetical Format
} \label{hypotheticalformat
}
51 Note that this is a hypothetical format, yet to be decided, where particular
52 attention needs to be paid to the fact that there is an
\textbf{immediate
}
53 version of CSRRW (with
5 bits of immediate) that could save a lot of space in
58 |
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0|
59 |-------------------------------|-------|---------------------|-|
60 |
1 custom custom custom custom custom | foreignarch |
1|
61 |
0 reserved reserved reserved reserved reserved | foreignarch |
1|
62 |custom | reserved | official|B| rvcpage |
0|
75 when bit
0 is
0,
\textbf{RV
} mode is selected.
79 in RV mode, bits
1 thru
5 provide up to
16 possible alternative meanings
80 (namespaces) for
16 Bit opcodes.
\textbf{pages
} if you will. The top bit
81 indicates custom meanings. When set to
0, the top bit is for official usage.
85 Bits
15 thru
23 are reserved.
89 Bits
24 thru
31 are for custom usage.
93 bit
6 (
\textbf{B
}) is endian-selection: LE/BE
107 0b0000 STANDARD (
2019) RVC
127 0b1000 custom
16 bit opcode meanings
1
131 0b1001 custom
16 bit opcode meanings
2
149 when bit
0 is
1,
\textbf{Foreign arch
} mode is selected.
153 Bits
1 thru
7 are a table of foreign arches.
157 when the MSB is
1, this is for custom use.
161 when the MSB is
0, bits
1 thru
6 are reserved for
64 possible official foreign archs.
167 Foreign archs could be (examples):
195 0b0010000 Java Bytecode
199 0b0010001 N.E.Other Bytecode
207 0b1000000 custom foreign arch
1
211 0b1000001 custom foreign arch
2
221 Note that
\textbf{official
} foreign archs have a binary value where the MSB is zero,
222 and custom foreign archs have a binary value where the MSB is
1.
224 \section{Namespaces are permitted to swap to new state
} \label{stateswap
}
228 In each privilege level, on a change of ISANS (whether through manual setting
229 of ISANS or through trap entry or exit changing the ISANS CSR), an
230 implementation is permitted to completely and arbitrarily switch not only the
231 instruction set, it is permitted to switch to a new bank of CSRs (or a subset
232 of the same), and even to switch to a new PC.
236 This to occur immediately and atomically at the point at which the change in ISANS occurs.
240 The most obvious application of this is for Foreign Archs, which may have their
241 own completely separate PC. Thus, foreign assembly code and
\gls{RISCV
} assembly code
242 need not be mixed in the same binary.
246 Further use-cases may be envisaged however great care needs to be taken to not
247 cause massive complications for JIT emulation, as the RV ISANS is unary encoded
248 (
2\^
31 permutations).
252 In addition, the state information of
\textbf{all
} namespaces has to be saved
253 and restored on a context-switch (unless the SP is also switched as part of the
254 state!) which is quite severely burdensome and getting exceptionally complex.
258 Switching
\gls{CSR
}, PC (and potentially SP) and other state on a NS change in the
259 RISCV unary NS therefore needs to be done wisely and responsibly, i.e.
264 To be discussed. Context
265 href=https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/x-uFZDXiOxY/
27QDW5KvBQAJ
268 \section{Privileged Modes / Traps
} \label{privtraps
}
272 An additional WLRL CSR per priv-level named
\textbf{LAST-ISANS
} is required, and
273 another called
\textbf{TRAP-ISANS
}
274 These mirrors the ISANS CSR, and, on a trap, the current ISANS in
275 that privilege level is atomically
276 transferred into LAST-ISANS by the hardware, and ISANS in that trap
277 is set to TRAP-ISANS. Hardware is
\textbf{only then
} permitted to modify the PC to
278 begin execution of the trap.
282 On exit from the trap, LAST-ISANS is copied into the ISANS CSR, and
283 LAST-ISANS is set to TRAP-ISANS.
\textbf{Only then
} is the hardware permitted
284 to modify the PC to begin execution where the trap left off.
288 This is identical to how xepc is handled.
292 Note
1: in the case of
\gls{SupervisorMode
} (context switches in particular),
293 saving and changing of LAST-ISANS (to and from the stack) must be done
294 atomically and under the protection of the SIE bit. Failure to do so
295 could result in corruption of LAST-ISANS when multiple traps occur in
296 the same privilege level.
300 Note
2: question - should the trap due to illegal (unsupported) values
301 written into LAST-ISANS occur when the
\textbf{software
} writes to LAST-ISANS,
302 or when the
\textbf{trap
} (on exit) writes into LAST-ISANS? this latter seems
303 fraught: a trap, on exit, causing another trap??
307 Per-privilege-level pseudocode (there exists UISANS, UTRAPISANS, ULASTISANS,
308 MISANS, MTRAPISANS, MLASTISANS and so on):
313 LAST-ISANS = ISANS // record the old NS
314 ISANS = TRAP_ISANS // traps are executed in "trap" NS
322 LAST-ISANS = TRAP_ISANS
326 \section{Alternative RVC
16 Bit Opcode meanings
} \label{alternativervc16bitopcodemeanings
}
330 Here is appropriate to raise an idea how to cover RVC and future
331 variants, including RV16.
335 Just as with foreign archs, and you quite rightly highlight above, it
336 makes absolutely no sense to try to select both RVCv1, v2, v3 and so on,
337 all simultaneously. An unary bit vector for RVC modes, changing the
16
338 BIT opcode space meaning, is wasteful and again has us believe that WARL
339 is the
\textbf{solution
}.
343 The correct thing to do is, again, just like with foreign archs, to
344 treat RVCs as a
\textbf{binary
} namespace selector. Bits
1 thru
3 would give
345 8 possible completely new alternative meanings, just like how the
\gls{Z80
}
346 and the
286 and
386 used to do bank switching.
350 All zeros is clearly reserved for the present RVC.
0b001 for RVCv2.
0b010
351 for RV16 (look it up) and there should definitely be room reserved here
352 for custom reencodings of the
16 bit opcode space.
354 \section{FAQ
}\label{faq
}
356 \subsection{Why not have TRAP-ISANS as a vector table, matching mtvec?
} \label{trap-isans-vec
}
360 Use case to be determined. Rather than be a global per-priv-level value,
361 TRAP-ISANS is a table of length exactly equal to the mtvec/utvec/stvec table,
362 with corresponding entries that specify the assembly-code namespace in which
363 the trap handler routine is written.
367 Open question: see https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IAhyOqEZoWA/BM0G3J2zBgAJ
372 LAST-ISANS = ISANS // record the old NS
373 ISANS = TRAP_ISANS_VEC
[xcause
] // traps are executed in "trap" NS
381 LAST-ISANS = TRAP_ISANS_VEC
[x_cause
]
385 \subsection{Is this like MISA?
} \label{misa
}
397 MISA's space is entirely taken up (and running out).
401 There is no allocation (provision) for custom extensions.
405 MISA switches on and off entire extensions: ISAMUX/NS may be used to switch
406 multiple opcodes (present and future), to alternate meanings.
410 MISA is WARL and is inaccessible from everything but M-Mode (not even readable).
416 MISA is therefore wholly unsuited to U-Mode usage; ISANS is specifically
417 permitted to be called by userspace to switch (with no stalling) between
418 namespaces, repeatedly and in quick succession.
420 \subsection{What happens if this scheme is not adopted? Why is it better than leaving things well alone?
} \label{laissezfaire
}
424 At the first sign of an emergency non-backwards compatible and unavoidable
425 change to the
\textbf{frozen
} RISCV
\textbf{official
} Standards, the entire RISCV
426 community is fragmented and divided into two:
434 Those vendors that are hardware compatible with the legacy standard.
438 Those that are compatible with the new standard.
444 \textbf{These two communities would be mutually exclusively incompatible
}. If
445 a second emergency occurs,
\gls{RISCV
} becomes even less tenable.
449 Hardware that wished to be
\textbf{compatible
} with either flavour would require
450 \gls{JIT
} or offline static binary recompilation. No vendor would willingly
451 accept this as a condition of the standards divergence in the first place,
452 locking up decision making to the detriment of RISCV as a whole.
456 By providing a
\textbf{safety valve
} in the form of a hidden namespace, at least
457 newer hardware has the option to implement both (or more) variations,
458 \textbf{and still apply for Certification
}.
462 However to also allow
\textbf{legacy
} hardware to at least be JIT soft
463 compatible, some very strict rules
\textbf{must
} be adhered to, that appear at
464 first sight not to make any sense.
468 It's complicated in other words!
470 \subsection{Surely it's okay to just tell people to use
48-bit encodings?
} \label{use48bit
}
474 Short answer: it doesn't help resolve conflicts, and costs hardware and
475 redesigns to do so. Softcores in cost-sensitive embedded applications may
476 even not actually be able to fit the required
48 bit instruction decode engine
477 into a (small, ICE40)
\gls{FPGA
}.
48-bit instruction decoding is much more complex
478 than straight
32-bit decoding, requiring a queue.
482 Second answer: conflicts can still occur in the (unregulated, custom)
48-bit
483 space, which
\textbf{could
} be resolved by ISAMUX/ISANS as applied to the
\textbf{48} bit
484 space in exactly the same way. And the
64-bit space.
486 \subsection{Why not leave this to individual custom vendors to solve on a case by case basis?
} \label{case-by-case
}
490 The suggestion was raised that a custom extension vendor could create
491 their own CSR that selects between conflicting namespaces that resolve
492 the meaning of the exact same opcode. This to be done by all and any
493 vendors, as they see fit, with little to no collaboration or coordination
494 towards standardisation in any form.
498 The problems with this approach are numerous, when presented to a
499 worldwide context that the UNIX Platform, in particular, has to face
500 (where the embedded platform does not)
504 First: lack of coordination, in the proliferation of arbitrary solutions,
505 has to primarily be borne by
\gls{gcc
},
\gls{Binutils
},
\gls{LLVM
} and other compilers.
509 Secondly: CSR space is precious. With each vendor likely needing only one
510 or two bits to express the namespace collision avoidance, if they make
511 even a token effort to use worldwide unique CSRs (an effort that would
512 benefit compiler writers), the CSR register space is quickly exhausted.
516 Thirdly: JIT Emulation of such an unregulated space becomes just as
517 much hell as it is for compiler writers. In addition, if two vendors
518 use conflicting CSR addresses, the only sane way to tell the emulator
519 what to do is to give the emulator a runtime command line argument.
523 Fourthly: with each vendor coming up with their own way of handling
524 conflicts, not only are the chances of mistakes higher, it is against the
525 very principles of collaboration and cooperation that save vendors money
526 on development and ongoing maintenance. Each custom vendor will have
527 to maintain their own separate hard fork of the toolchain and software,
528 which is well known to result in security vulnerabilities.
532 By coordinating and managing the allocation of namespace bits (unary
533 or binary) the above issues are solved. CSR space is no longer wasted,
534 compiler and JIT software writers have an easier time, clashes are
535 avoided, and RISCV is stabilised and has a trustable long term future.
537 \subsection{ Why ISAMUX / ISANS has to be WLRL and mandatory trap on illegal writes
} \label{wlrlmandatorytrap
}
541 The namespaces, set by bits in the CSR, are functionally directly
542 equivalent to c++ namespaces, even down to the use of braces.
546 WARL, by allowing implementors to choose the value, prevents and prohibits
547 the critical and necessary raising of an exception that would begin the
548 JIT process in the case of ongoing standards evolution.
552 Without this opportunity, an implementation has no reliable guaranteed way of knowing
553 when to drop into full JIT mode,
554 which is the only guaranteed way to distinguish
555 any given conflicting opcode. It is as if the c++
556 standard was given a similar optional
557 opportunity to completely ignore the
558 \textbf{using namespace
} prefix!
566 Ok so I trust it's now clear why WLRL (thanks Allen) is needed.
570 When Dan raised the WARL concern initially a situation was masked by
571 the conflict, that if gone unnoticed would jeapordise ISAMUX/ISANS
572 entirely. Actually, two separate errors. So thank you for raising the
577 The situation arises when foreign archs are to be given their own NS
578 bit. MIPS is allocated bit
8, x86 bit
9, whilst LE/BE is given bit
0,
579 RVCv2 bit
1 andso on. All of this potential rather than actual, clearly.
583 Imagine then that software tries to write and set not just bit
8 and
584 bit
9, it also tries to set bit
0 and
1 as well.
588 This
\textbf{IS
} on the face of it a legitimate reason to make ISAMUX/ISANS WARL.
592 However it masks a fundamental flaw that has to be addressed, which
593 brings us back much closer to the original design of
18 months ago,
594 and it's highlighted thus:
598 x86 and simultaneous RVCv2 modes are total nonsense in the first place!
602 The solution instead is to have a NS bit (bit0) that SPECIFICALLY
603 determines if the arch is RV or not. If
0, the rest of the ISAMUX/ISANS
604 is very specifically RV
\textbf{only
}, and if
1, the ISAMUX/ISANS is a
\textbf{binary
}
605 table of foreign architectures and foreign architectures only.
609 Exactly how many bits are used for the foreign arch table, is to
610 be determined.
7 bits, one of which is reserved for custom usage,
611 leaving a whopping
64 possible
\textbf{official
} foreign instruction sets to
612 be hardware-supported/JIT-emulated seems to be sufficiently gratuitous,
617 One of those could even be Java Bytecode!
621 Now, it could
\textbf{hypothetically
} be argued that the permutation of setting
622 LE/BE and MIPS for example is desirable. A simple analysis shows this
623 not to be the case: once in the MIPS foreign NS, it is the MIPS hardware
624 implementation that should have its own way of setting and managing its
625 LE/BE mode, because to do otherwise drastically interferes with MIPS
626 binary compatibility.
630 Thus, it is officially Not Our Problem: only flipping into one foreign
631 arch at a time makes sense, thus this has to be reflected in the
632 ISAMUX/ISANS CSR itself, completely side-stepping the (apparent) need
633 to make the NS CSR WARL (which would not work anyway, as previously
638 So, thank you, again, Dan, for raising this. It would have completely
639 jeapordised ISAMUX/NS if not spotted.
643 The second issue is: how does any hardware system, whether it support
644 ISANS or not, and whether any future hardware supports some Namespaces
645 and, in a transitive fashion, has to support
\textbf{more
} future namespaces,
646 through JIT emulation, if this is not planned properly in advance?
650 Let us take the simple case first: a current
2019 RISCV fully compliant
651 RV64GC UNIX capable system (with mandatory traps on all unsupported CSRs).
655 Fast forward
20 years, there are now
5 ISAMUX/NS unary bits, and
3
656 foreign arch binary table entries.
660 Such a system is perfectly possible of software JIT emulating ALL of these
661 options because the write to the (illegal, for that system) ISAMUX/NS
662 CSR generates the trap that is needed for that system ti begin JIT mode.
666 (This again emphasises exactly why the trap is mandatory).
670 Now let us take the case of a hypothetical system from say
2021 that
671 implements RVCv2 at the hardware level.
675 Fast forward
20 years: if the CSR were made WARL, that system would be
676 absolutely screwed. The implementor would be under the false impression
677 that ignoring setting of
\textbf{illegal
} bits was acceptable, making the
678 transition to JIT mode flat-out impossible to detect.
682 When this is considered transitively, considering all future additions to
683 the NS, and all permutations, it can be logically deduced that there is
684 a need to reserve a
\textbf{full
} set of bits in the ISAMUX/NS CSR
\textbf{in advance
}.
688 i.e. that
\textbf{right now
}, in the year
2019, the entire ISAMUX/NS CSR cannot
689 be added to piecemeal, the full
32 (or
64) bits
\textbf{has
} to be reserved,
690 and reserved bits set at zero.
694 Furthermore, if any software attempts to write to those reserved bits,
695 it
\textbf{must
} be treated just as if those bits were distinct and nonexistent
696 CSRs, and a trap raised.
700 It makes more sense to consider each NS as having its own completely
701 separate CSR, which, if it does not exist, clearly it should be obvious
702 that, as an unsupported CSR, a trap should be raised (and JIT emulation
707 However given that only the one bit is needed (in RV NS Mode, not
708 Foreign NS Mode), it would be terribly wasteful of the CSRs to do this,
709 despite it being technically correct and much easier to understand why
710 trap raising is so essential (mandatory).
714 This again should emphasise how to mentally get one's head round this
715 mind-bendingly complex problem space: think of each NS bit as its own
716 totally separate CSR that every implementor is free and clear to implement
717 (or leave to JIT Emulation) as they see fit.
721 Only then does the mandatory need to trap on write really start to hit
722 home, as does the need to preallocate a full set of reserved zero values
727 Lastly, I
\textbf{think
} it's ok to only reserve say
32 bits, and, in
50 years
728 time if that genuinely is not enough, start the process all over again
729 with a new CSR. ISAMUX2/NS2.
733 Subdivision of the RV NS (support for RVCv3/
4/
5/RV16 without wasting
734 precious CSR bits) best left for discussion another time, the above is
735 a heck of a lot to absorb, already.
737 \subsection{Why WARL will not work and why WLRL is required
}
741 WARL requires a follow-up read of the CSR to ascertain what heuristic
742 the hardware
\textbf{might
} have applied, and if that procedure is followed in
743 this proposal, performance even on hardware would be severely compromised.
747 In addition when switching to foreign architectures, the switch has to
748 be done atomically and guaranteed to occur.
752 In the case of JIT emulation, the WARL
\textbf{detection
} code will be in an
753 assembly language that is alien to hardware.
757 Support for both assembly languages immediately after the CSR write
758 is clearly impossible, this leaves no other option but to have the CSR
759 be WLRL (on all platforms) and for traps to be mandatory (on the UNIX
762 \subsection{Is it strictly necessary for foreign archs to switch back?
} \label{foreignswitch
}
766 No, because LAST-ISANS handles the setting and unsetting of the ISANS CSR
767 in a completely transparent fashion as far as the foreign arch is concerned.
768 Supervisor or Hypervisor traps take care of the context switch in a way
769 that the user mode (or guest) need not be aware of, in any way.
773 Thus, in e.g. Hypervisor Mode, the foreign guest arch has no knowledge
774 or need to know that the hypervisor is flipping back to RV at the time of
779 Note however that this is
\textbf{not
} the same as the foreign arch executing
780 \textbf{foreign
} traps! Foreign architecture trap and interrupt handling mechanisms
781 are
\textbf{out of scope
} of this
document and MUST be handled by the foreign
782 architecture implementation in a completely transparent fashion that in
783 no way interacts or interferes with this proposal.
785 \subsection{Can we have dynamic declaration and runtime declaration of capabilities?
} \label{dynamic
}
789 Answer: don't know (yet). Quoted from Rogier:
792 "A
\gls{SoC
} may have several devices that one may want to directly control
793 with custom instructions. If independent vendors use the same opcodes you
794 either have to change the encodings for every different chip (not very
795 nice for software) or you can give the device an ID which is defined in
796 some device tree or something like that and use that."
801 Dynamic detection wasn't originally planned: static
802 compilation was envisaged to solve the need, with a table of
803 mvendorid-marchid-isamux/isans being maintained inside gcc / binutils /
804 llvm (or separate library?) that, like the Linux kernel ARCH table,
805 requires a world-wide atomic
\textbf{git commit
} to add globally-unique
806 registered entries that map functionality to actual namespaces.
810 where that goes wrong is if there is ever a pair (or more) of vendors
811 that use the exact same custom feature that maps to different opcodes,
812 a statically-compiled binary has no hope of executing natively on both
817 at that point: yes, something akin to device-tree would be needed.
819 \section{Open Questions
}\label{open-questions
}
823 This section from a post by Rogier Bruisse
824 \href{http://hands.com/~lkcl/gmail_re_isadev_isamux.html
}{http://hands.com/~lkcl/gmail
\_re\_isadev\_isamux.html
}
826 \subsection{is the ISANS CSR a
32 or XLEN bit value?
} \label{isans-
32-or-xlen
}
830 This is partly answered in another FAQ above: if
32 bits is not enough
831 for a full suite of official, custom-with-atomic-registration and custom-without
832 then a second CSR group (ISANS2) may be added at a future date (
10-
20 years
837 32 bits would not inconvenience RV32, and implementors wishing to
838 make significant altnernative modifications to opcodes in the RV32 ISA space
839 could do so without the burden of having to support a split
32/LO
32/HI
840 CSR across two locations.
842 \subsection{Is the ISANS a flat number space or should some bits be reserved for use as flags?
}
846 See
16-bit RV namespace "page" concept, above. Some bits have to be unary
847 (multiple simultaneous features such as LE/BE in one bit, and augmented
848 Floating-point rounding / clipping in another), whilst others definitely
849 need to be binary (the most obvious one being
\textbf{paging
} in the space currently
852 \subsection{Should the ISANS space be partitioned between reserved, custom with registration guaranteed non clashing, custom, very likely non clashing?
}
858 \subsection{Should only compiler visible/generated constant setting with CSRRWI and/or using a clearly recognisable LI/LUI be accommodated or should dynamic setting be accommodated as well?
}
862 This is almost certainly a software design issue, not so much a hardware
865 \subsection{How should the ISANS be (re)stored in a trap and in context switch?
}
869 See section above on privilege mode: LAST-ISANS has been introduced that
870 mirrors (x)CAUSE and (x)EPC pretty much exactly. Context switches change
871 uepc just before exit from the trap, in order to change the user-mode PC
872 to switch to a new process, and ulast-isans can - must - be treated in
873 exactly the same way. When the context switch sets ulast-isans (and uepc),
874 the hardware flips both ulast-isans into uisans and uepc into pc (atomically):
875 both the new NS and the new PC activate immediately, on return to usermode.
881 \subsection{Should the mechanism accommodate "foreign ISA's" and if so how does one restore the ISA.
}
885 See section above on LAST-ISANS. With the introduction of LAST-ISANS, the
886 change is entirely transparent, and handled by the Supervisor (or Hypervisor)
887 trap, in a fashion that the foreign ISA need not even know of the existence
890 \subsection{Where is the default ISA stored and what is responsible for what it is after
}
909 calling into a dynamically linked library
917 changing privilege levels
923 These first four are entirely at the discretion of (and the
924 responsibility of) the software. There is precedent for most of these
925 having been implemented, historically, at some point, in relation to
926 LE/BE mode CSRs in other hardware (MIPSEL vs MIPS distros for example).
930 Traps are responsible for saving LAST-ISANS on the stack, exactly as they
931 are also responsible for saving other context-sensitive information such
932 as the registers and xEPC.
936 The hardware is responsible for atomically switching out ISANS into the
937 relevant xLAST-ISANS (and back again on exit). See Privileged Traps,
940 \subsection{If the ISANS is just bits of an instruction that are to be prefixed by the cpu, can those bits contain immediates? Register numbers?
}
944 The concept of a CSR containing an immediate makes no sense. The concept
945 of a CSR containing a register number, the contents of which would, presumably,
946 be inserted into the NS, would immediately make that register a permanent
947 and irrevocably reserved register that could not be utilised for any other
952 This is what the CSRs are supposed to be for!
956 It would be better just to have a second CSR - ISANS2 - potentially even ISANS3
957 in
60+ years time, rather than try to use a GPR for the purposes for which CSRs
960 \subsection{How does the system indicate a namespace is not recognised? Does it trap or can/must a recoverable mechanism be provided?
}
964 It doesn't "indicate" that a namespace is not recognised. WLRL fields only
965 hold supported values. If the hardware cannot hold the value, a trap
966 \textbf{MUST
} be thrown (in the UNIX platform), and at that point it becomes the
967 responsibility of software to deal with it.
969 \subsection{What are the security implications? Can some ISA namespaces be set by user space?
}
973 Of course they can. It becomes the responsibility of the Supervisor Mode
974 (the kernel) to treat ISANS in a fashion orthogonal to the PC. If the OS
975 is not capable of properly context-switching securely by setting the right
976 PC, it's not going to be capable of properly looking after changes to ISANS.
978 \subsection{Does the validity of an ISA namespace depend on privilege level? If so how?
}
982 The question does not exactly make sense, and may need a re-reading of the
983 section on how Privilege Modes, above. In RISC-V, privilege modes do not
984 actually change very much state of the system: the absolute minimum changes
985 are made (swapped out) - xEPC, xSTATUS and so on - and the privilege mode
986 is expected to handle the context switching (or other actions) itself.
990 ISANS - through LAST-ISANS - is absolutely no different. The trap and the
991 kernel (Supervisor or Hypervisor) are provided the
\textbf{mechanism
} by which
992 ISA Namespace
\textbf{may
} be set: it is up to the software to use that mechanism
993 correctly, just as the software is expected to use the mechanisms provided
994 to correctly implement context-switching by saving and restoring register
995 files, the PC, and other state. The NS effectively becomes just another