register_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity register_file is
   9     generic (
  10         SIM : boolean := false
  11         );
  12     port(
  13         clk           : in std_logic;
  14
  15         d_in          : in Decode2ToRegisterFileType;
  16         d_out         : out RegisterFileToDecode2Type;
  17
  18         w_in          : in WritebackToRegisterFileType;
  19
  20         dbg_gpr_req   : in std_ulogic;
  21         dbg_gpr_ack   : out std_ulogic;
  22         dbg_gpr_addr  : in gspr_index_t;
  23         dbg_gpr_data  : out std_ulogic_vector(63 downto 0);
  24
  25         -- debug
  26         sim_dump      : in std_ulogic;
  27         sim_dump_done : out std_ulogic;
  28
  29         log_out       : out std_ulogic_vector(70 downto 0)
  30         );
  31 end entity register_file;
  32
  33 architecture behaviour of register_file is
  34     type regfile is array(0 to 63) of std_ulogic_vector(63 downto 0);
  35     signal registers : regfile := (others => (others => '0'));
  36     signal rd_port_b : std_ulogic_vector(63 downto 0);
  37     signal dbg_data : std_ulogic_vector(63 downto 0);
  38     signal dbg_ack : std_ulogic;
  39     signal log_data : std_ulogic_vector(70 downto 0);
  40 begin
  41     -- synchronous writes
  42     register_write_0: process(clk)
  43     begin
  44         if rising_edge(clk) then
  45             if w_in.write_enable = '1' then
  46                 if w_in.write_reg(5) = '0' then
  47                     report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  48                 else
  49                     report "Writing GSPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  50                 end if;
  51                 assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
  52                 registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
  53             end if;
  54         end if;
  55     end process register_write_0;
  56
  57     -- asynchronous reads
  58     register_read_0: process(all)
  59         variable b_addr : gspr_index_t;
  60     begin
  61         if d_in.read1_enable = '1' then
  62             report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
  63         end if;
  64         if d_in.read2_enable = '1' then
  65             report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
  66         end if;
  67         if d_in.read3_enable = '1' then
  68             report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
  69         end if;
  70         d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
  71         -- B read port is multiplexed with reads from the debug circuitry
  72         if d_in.read2_enable = '0' and dbg_gpr_req = '1' and dbg_ack = '0' then
  73             b_addr := dbg_gpr_addr;
  74         else
  75             b_addr := d_in.read2_reg;
  76         end if;
  77         rd_port_b <= registers(to_integer(unsigned(b_addr)));
  78         d_out.read2_data <= rd_port_b;
  79         d_out.read3_data <= registers(to_integer(unsigned(gpr_to_gspr(d_in.read3_reg))));
  80
  81         -- Forward any written data
  82         if w_in.write_enable = '1' then
  83             if d_in.read1_reg = w_in.write_reg then
  84                 d_out.read1_data <= w_in.write_data;
  85             end if;
  86             if d_in.read2_reg = w_in.write_reg then
  87                 d_out.read2_data <= w_in.write_data;
  88             end if;
  89             if gpr_to_gspr(d_in.read3_reg) = w_in.write_reg then
  90                 d_out.read3_data <= w_in.write_data;
  91             end if;
  92         end if;
  93     end process register_read_0;
  94
  95     -- Latch read data and ack if dbg read requested and B port not busy
  96     dbg_register_read: process(clk)
  97     begin
  98         if rising_edge(clk) then
  99             if dbg_gpr_req = '1' then
 100                 if d_in.read2_enable = '0' and dbg_ack = '0' then
 101                     dbg_data <= rd_port_b;
 102                     dbg_ack <= '1';
 103                 end if;
 104             else
 105                 dbg_ack <= '0';
 106             end if;
 107         end if;
 108     end process;
 109
 110     dbg_gpr_ack <= dbg_ack;
 111     dbg_gpr_data <= dbg_data;
 112
 113     -- Dump registers if core terminates
 114     sim_dump_test: if SIM generate
 115         dump_registers: process(all)
 116         begin
 117             if sim_dump = '1' then
 118                 loop_0: for i in 0 to 31 loop
 119                     report "GPR" & integer'image(i) & " " & to_hstring(registers(i));
 120                 end loop loop_0;
 121
 122                 report "LR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_LR)))));
 123                 report "CTR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_CTR)))));
 124                 report "XER " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_XER)))));
 125                 sim_dump_done <= '1';
 126             else
 127                 sim_dump_done <= '0';
 128             end if;
 129         end process;
 130     end generate;
 131
 132     -- Keep GHDL synthesis happy
 133     sim_dump_test_synth: if not SIM generate
 134         sim_dump_done <= '0';
 135     end generate;
 136
 137     reg_log: process(clk)
 138     begin
 139         if rising_edge(clk) then
 140             log_data <= w_in.write_data &
 141                         w_in.write_enable &
 142                         w_in.write_reg;
 143         end if;
 144     end process;
 145     log_out <= log_data;
 146 end architecture behaviour;