register_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity register_file is
   9         port(
  10                 clk           : in std_logic;
  11
  12                 d_in          : in Decode2ToRegisterFileType;
  13                 d_out         : out RegisterFileToDecode2Type;
  14
  15                 w_in          : in WritebackToRegisterFileType;
  16
  17                 -- debug
  18                 registers_out : out regfile
  19         );
  20 end entity register_file;
  21
  22 architecture behaviour of register_file is
  23         signal registers : regfile := (others => (others => '0'));
  24 begin
  25         -- synchronous writes
  26         register_write_0: process(clk)
  27         begin
  28                 if rising_edge(clk) then
  29                         if w_in.write_enable = '1' then
  30                                 assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
  31                                 report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  32                                 registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
  33                         end if;
  34                         if w_in.write_enable2 = '1' then
  35                                 assert not(is_x(w_in.write_data2)) and not(is_x(w_in.write_reg2)) severity failure;
  36                                 report "Writing GPR " & to_hstring(w_in.write_reg2) & " " & to_hstring(w_in.write_data2);
  37                                 registers(to_integer(unsigned(w_in.write_reg2))) <= w_in.write_data2;
  38                         end if;
  39                 end if;
  40         end process register_write_0;
  41
  42         -- asynchronous reads
  43         register_read_0: process(all)
  44         begin
  45                 if d_in.read1_enable = '1' then
  46                         report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
  47                 end if;
  48                 if d_in.read2_enable = '1' then
  49                         report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
  50                 end if;
  51                 if d_in.read3_enable = '1' then
  52                         report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
  53                 end if;
  54                 d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
  55                 d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
  56                 d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg)));
  57
  58                 -- Forward any written data
  59                 --if w_in.write_enable = '1' then
  60                         --if d_in.read1_reg = w_in.write_reg then
  61                                 --d_out.read1_data <= w_in.write_data;
  62                         --end if;
  63                         --if d_in.read2_reg = w_in.write_reg then
  64                                 --d_out.read2_data <= w_in.write_data;
  65                         --end if;
  66                         --if d_in.read3_reg = w_in.write_reg then
  67                                 --d_out.read3_data <= w_in.write_data;
  68                         --end if;
  69                 --end if;
  70         end process register_read_0;
  71
  72         -- debug
  73         registers_out <= registers;
  74 end architecture behaviour;