register_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity register_file is
   9     generic (
  10         SIM : boolean := false
  11         );
  12     port(
  13         clk           : in std_logic;
  14
  15         d_in          : in Decode2ToRegisterFileType;
  16         d_out         : out RegisterFileToDecode2Type;
  17
  18         w_in          : in WritebackToRegisterFileType;
  19
  20         -- debug
  21         sim_dump      : in std_ulogic;
  22         sim_dump_done : out std_ulogic
  23         );
  24 end entity register_file;
  25
  26 architecture behaviour of register_file is
  27     type regfile is array(0 to 63) of std_ulogic_vector(63 downto 0);
  28     signal registers : regfile := (others => (others => '0'));
  29 begin
  30     -- synchronous writes
  31     register_write_0: process(clk)
  32     begin
  33         if rising_edge(clk) then
  34             if w_in.write_enable = '1' then
  35                 assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
  36                 if w_in.write_reg(5) = '0' then
  37                     report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  38                 else
  39                     report "Writing GSPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  40                 end if;
  41                 registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
  42             end if;
  43         end if;
  44     end process register_write_0;
  45
  46     -- asynchronous reads
  47     register_read_0: process(all)
  48     begin
  49         if d_in.read1_enable = '1' then
  50             report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
  51         end if;
  52         if d_in.read2_enable = '1' then
  53             report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
  54         end if;
  55         if d_in.read3_enable = '1' then
  56             report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
  57         end if;
  58         d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
  59         d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
  60         d_out.read3_data <= registers(to_integer(unsigned(gpr_to_gspr(d_in.read3_reg))));
  61
  62         -- Forward any written data
  63         if w_in.write_enable = '1' then
  64             if d_in.read1_reg = w_in.write_reg then
  65                 d_out.read1_data <= w_in.write_data;
  66             end if;
  67             if d_in.read2_reg = w_in.write_reg then
  68                 d_out.read2_data <= w_in.write_data;
  69             end if;
  70             if gpr_to_gspr(d_in.read3_reg) = w_in.write_reg then
  71                 d_out.read3_data <= w_in.write_data;
  72             end if;
  73         end if;
  74     end process register_read_0;
  75
  76     -- Dump registers if core terminates
  77     sim_dump_test: if SIM generate
  78         dump_registers: process(all)
  79         begin
  80             if sim_dump = '1' then
  81                 loop_0: for i in 0 to 31 loop
  82                     report "GPR" & integer'image(i) & " " & to_hstring(registers(i));
  83                 end loop loop_0;
  84
  85                 report "LR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_LR)))));
  86                 report "CTR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_CTR)))));
  87                 report "XER " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_XER)))));
  88                 sim_dump_done <= '1';
  89             else
  90                 sim_dump_done <= '0';
  91             end if;
  92         end process;
  93     end generate;
  94
  95     -- Keep GHDL synthesis happy
  96     sim_dump_test_synth: if not SIM generate
  97         sim_dump_done <= '0';
  98     end generate;
  99
 100 end architecture behaviour;