register_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity register_file is
   9     port(
  10         clk           : in std_logic;
  11
  12         d_in          : in Decode2ToRegisterFileType;
  13         d_out         : out RegisterFileToDecode2Type;
  14
  15         w_in          : in WritebackToRegisterFileType;
  16
  17         -- debug
  18         registers_out : out regfile
  19         );
  20 end entity register_file;
  21
  22 architecture behaviour of register_file is
  23     signal registers : regfile := (others => (others => '0'));
  24 begin
  25     -- synchronous writes
  26     register_write_0: process(clk)
  27     begin
  28         if rising_edge(clk) then
  29             if w_in.write_enable = '1' then
  30                 assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
  31                 report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  32                 registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
  33             end if;
  34         end if;
  35     end process register_write_0;
  36
  37     -- asynchronous reads
  38     register_read_0: process(all)
  39     begin
  40         if d_in.read1_enable = '1' then
  41             report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
  42         end if;
  43         if d_in.read2_enable = '1' then
  44             report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
  45         end if;
  46         if d_in.read3_enable = '1' then
  47             report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
  48         end if;
  49         d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
  50         d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
  51         d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg)));
  52
  53         -- Forward any written data
  54         if w_in.write_enable = '1' then
  55             if d_in.read1_reg = w_in.write_reg then
  56                 d_out.read1_data <= w_in.write_data;
  57             end if;
  58             if d_in.read2_reg = w_in.write_reg then
  59                 d_out.read2_data <= w_in.write_data;
  60             end if;
  61             if d_in.read3_reg = w_in.write_reg then
  62                 d_out.read3_data <= w_in.write_data;
  63             end if;
  64         end if;
  65     end process register_read_0;
  66
  67     -- debug
  68     registers_out <= registers;
  69 end architecture behaviour;