2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
8 entity register_file is
10 SIM : boolean := false
15 d_in : in Decode2ToRegisterFileType;
16 d_out : out RegisterFileToDecode2Type;
18 w_in : in WritebackToRegisterFileType;
21 sim_dump : in std_ulogic
23 end entity register_file;
25 architecture behaviour of register_file is
26 type regfile is array(0 to 63) of std_ulogic_vector(63 downto 0);
27 signal registers : regfile := (others => (others => '0'));
30 register_write_0: process(clk)
32 if rising_edge(clk) then
33 if w_in.write_enable = '1' then
34 assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
35 if w_in.write_reg(5) = '0' then
36 report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
38 report "Writing GSPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
40 registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
43 end process register_write_0;
46 register_read_0: process(all)
48 if d_in.read1_enable = '1' then
49 report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
51 if d_in.read2_enable = '1' then
52 report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
54 if d_in.read3_enable = '1' then
55 report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
57 d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
58 d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
59 d_out.read3_data <= registers(to_integer(unsigned(gpr_to_gspr(d_in.read3_reg))));
61 -- Forward any written data
62 if w_in.write_enable = '1' then
63 if d_in.read1_reg = w_in.write_reg then
64 d_out.read1_data <= w_in.write_data;
66 if d_in.read2_reg = w_in.write_reg then
67 d_out.read2_data <= w_in.write_data;
69 if gpr_to_gspr(d_in.read3_reg) = w_in.write_reg then
70 d_out.read3_data <= w_in.write_data;
73 end process register_read_0;
75 -- Dump registers if core terminates
76 sim_dump_test: if SIM generate
77 dump_registers: process(all)
79 if sim_dump = '1' then
80 loop_0: for i in 0 to 31 loop
81 report "REG " & to_hstring(registers(i));
83 assert false report "end of test" severity failure;
88 end architecture behaviour;