register_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity register_file is
   9     generic (
  10         SIM : boolean := false
  11         );
  12     port(
  13         clk           : in std_logic;
  14
  15         d_in          : in Decode2ToRegisterFileType;
  16         d_out         : out RegisterFileToDecode2Type;
  17
  18         w_in          : in WritebackToRegisterFileType;
  19
  20         -- debug
  21         sim_dump      : in std_ulogic
  22         );
  23 end entity register_file;
  24
  25 architecture behaviour of register_file is
  26     type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
  27     signal registers : regfile := (others => (others => '0'));
  28 begin
  29     -- synchronous writes
  30     register_write_0: process(clk)
  31     begin
  32         if rising_edge(clk) then
  33             if w_in.write_enable = '1' then
  34                 assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
  35                 report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  36                 registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
  37             end if;
  38         end if;
  39     end process register_write_0;
  40
  41     -- asynchronous reads
  42     register_read_0: process(all)
  43     begin
  44         if d_in.read1_enable = '1' then
  45             report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
  46         end if;
  47         if d_in.read2_enable = '1' then
  48             report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
  49         end if;
  50         if d_in.read3_enable = '1' then
  51             report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
  52         end if;
  53         d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
  54         d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
  55         d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg)));
  56
  57         -- Forward any written data
  58         if w_in.write_enable = '1' then
  59             if d_in.read1_reg = w_in.write_reg then
  60                 d_out.read1_data <= w_in.write_data;
  61             end if;
  62             if d_in.read2_reg = w_in.write_reg then
  63                 d_out.read2_data <= w_in.write_data;
  64             end if;
  65             if d_in.read3_reg = w_in.write_reg then
  66                 d_out.read3_data <= w_in.write_data;
  67             end if;
  68         end if;
  69     end process register_read_0;
  70
  71     -- Dump registers if core terminates
  72     sim_dump_test: if SIM generate
  73         dump_registers: process(all)
  74         begin
  75             if sim_dump = '1' then
  76                 loop_0: for i in 0 to 31 loop
  77                     report "REG " & to_hstring(registers(i));
  78                 end loop loop_0;
  79                 assert false report "end of test" severity failure;
  80             end if;
  81         end process;
  82     end generate;
  83
  84 end architecture behaviour;