register_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity register_file is
   9     generic (
  10         SIM : boolean := false
  11         );
  12     port(
  13         clk           : in std_logic;
  14
  15         d_in          : in Decode2ToRegisterFileType;
  16         d_out         : out RegisterFileToDecode2Type;
  17
  18         w_in          : in WritebackToRegisterFileType;
  19
  20         dbg_gpr_req   : in std_ulogic;
  21         dbg_gpr_ack   : out std_ulogic;
  22         dbg_gpr_addr  : in gspr_index_t;
  23         dbg_gpr_data  : out std_ulogic_vector(63 downto 0);
  24
  25         -- debug
  26         sim_dump      : in std_ulogic;
  27         sim_dump_done : out std_ulogic
  28         );
  29 end entity register_file;
  30
  31 architecture behaviour of register_file is
  32     type regfile is array(0 to 63) of std_ulogic_vector(63 downto 0);
  33     signal registers : regfile := (others => (others => '0'));
  34     signal rd_port_b : std_ulogic_vector(63 downto 0);
  35     signal dbg_data : std_ulogic_vector(63 downto 0);
  36     signal dbg_ack : std_ulogic;
  37 begin
  38     -- synchronous writes
  39     register_write_0: process(clk)
  40     begin
  41         if rising_edge(clk) then
  42             if w_in.write_enable = '1' then
  43                 assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
  44                 if w_in.write_reg(5) = '0' then
  45                     report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  46                 else
  47                     report "Writing GSPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
  48                 end if;
  49                 registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
  50             end if;
  51         end if;
  52     end process register_write_0;
  53
  54     -- asynchronous reads
  55     register_read_0: process(all)
  56         variable b_addr : gspr_index_t;
  57     begin
  58         if d_in.read1_enable = '1' then
  59             report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
  60         end if;
  61         if d_in.read2_enable = '1' then
  62             report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
  63         end if;
  64         if d_in.read3_enable = '1' then
  65             report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
  66         end if;
  67         d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
  68         -- B read port is multiplexed with reads from the debug circuitry
  69         if d_in.read2_enable = '0' and dbg_gpr_req = '1' and dbg_ack = '0' then
  70             b_addr := dbg_gpr_addr;
  71         else
  72             b_addr := d_in.read2_reg;
  73         end if;
  74         rd_port_b <= registers(to_integer(unsigned(b_addr)));
  75         d_out.read2_data <= rd_port_b;
  76         d_out.read3_data <= registers(to_integer(unsigned(gpr_to_gspr(d_in.read3_reg))));
  77
  78         -- Forward any written data
  79         if w_in.write_enable = '1' then
  80             if d_in.read1_reg = w_in.write_reg then
  81                 d_out.read1_data <= w_in.write_data;
  82             end if;
  83             if d_in.read2_reg = w_in.write_reg then
  84                 d_out.read2_data <= w_in.write_data;
  85             end if;
  86             if gpr_to_gspr(d_in.read3_reg) = w_in.write_reg then
  87                 d_out.read3_data <= w_in.write_data;
  88             end if;
  89         end if;
  90     end process register_read_0;
  91
  92     -- Latch read data and ack if dbg read requested and B port not busy
  93     dbg_register_read: process(clk)
  94     begin
  95         if rising_edge(clk) then
  96             if dbg_gpr_req = '1' then
  97                 if d_in.read2_enable = '0' and dbg_ack = '0' then
  98                     dbg_data <= rd_port_b;
  99                     dbg_ack <= '1';
 100                 end if;
 101             else
 102                 dbg_ack <= '0';
 103             end if;
 104         end if;
 105     end process;
 106
 107     dbg_gpr_ack <= dbg_ack;
 108     dbg_gpr_data <= dbg_data;
 109
 110     -- Dump registers if core terminates
 111     sim_dump_test: if SIM generate
 112         dump_registers: process(all)
 113         begin
 114             if sim_dump = '1' then
 115                 loop_0: for i in 0 to 31 loop
 116                     report "GPR" & integer'image(i) & " " & to_hstring(registers(i));
 117                 end loop loop_0;
 118
 119                 report "LR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_LR)))));
 120                 report "CTR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_CTR)))));
 121                 report "XER " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_XER)))));
 122                 sim_dump_done <= '1';
 123             else
 124                 sim_dump_done <= '0';
 125             end if;
 126         end process;
 127     end generate;
 128
 129     -- Keep GHDL synthesis happy
 130     sim_dump_test_synth: if not SIM generate
 131         sim_dump_done <= '0';
 132     end generate;
 133
 134 end architecture behaviour;