rotator_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.glibc_random.all;
   8 use work.ppc_fx_insns.all;
   9 use work.insn_helpers.all;
  10
  11 entity rotator_tb is
  12 end rotator_tb;
  13
  14 architecture behave of rotator_tb is
  15     constant clk_period: time := 10 ns;
  16     signal ra, rs: std_ulogic_vector(63 downto 0);
  17     signal shift: std_ulogic_vector(6 downto 0) := (others => '0');
  18     signal insn: std_ulogic_vector(31 downto 0) := (others => '0');
  19     signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0';
  20     signal result: std_ulogic_vector(63 downto 0);
  21     signal carry_out: std_ulogic;
  22
  23 begin
  24     rotator_0: entity work.rotator
  25         port map (
  26             rs => rs,
  27             ra => ra,
  28             shift => shift,
  29             insn => insn,
  30             is_32bit => is_32bit,
  31             right_shift => right_shift,
  32             arith => arith,
  33             clear_left => clear_left,
  34             clear_right => clear_right,
  35             result => result,
  36             carry_out => carry_out
  37         );
  38
  39     stim_process: process
  40         variable behave_ra: std_ulogic_vector(63 downto 0);
  41         variable behave_ca_ra: std_ulogic_vector(64 downto 0);
  42     begin
  43         -- rlwinm, rlwnm
  44         report "test rlw[i]nm";
  45         ra <= (others => '0');
  46         is_32bit <= '1';
  47         right_shift <= '0';
  48         arith <= '0';
  49         clear_left <= '1';
  50         clear_right <= '1';
  51         rlwnm_loop : for i in 0 to 1000 loop
  52             rs <= pseudorand(64);
  53             shift <= pseudorand(7);
  54             insn <= x"00000" & '0' & pseudorand(10) & '0';
  55             wait for clk_period;
  56             behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
  57             assert behave_ra = result
  58                 report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
  59         end loop;
  60
  61         -- rlwimi
  62         report "test rlwimi";
  63         is_32bit <= '1';
  64         right_shift <= '0';
  65         arith <= '0';
  66         clear_left <= '1';
  67         clear_right <= '1';
  68         rlwimi_loop : for i in 0 to 1000 loop
  69             rs <= pseudorand(64);
  70             ra <= pseudorand(64);
  71             shift <= "00" & pseudorand(5);
  72             insn <= x"00000" & '0' & pseudorand(10) & '0';
  73             wait for clk_period;
  74             behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
  75             assert behave_ra = result
  76                 report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
  77         end loop;
  78
  79         -- rldicl, rldcl
  80         report "test rld[i]cl";
  81         ra <= (others => '0');
  82         is_32bit <= '0';
  83         right_shift <= '0';
  84         arith <= '0';
  85         clear_left <= '1';
  86         clear_right <= '0';
  87         rldicl_loop : for i in 0 to 1000 loop
  88             rs <= pseudorand(64);
  89             shift <= pseudorand(7);
  90             insn <= x"00000" & '0' & pseudorand(10) & '0';
  91             wait for clk_period;
  92             behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
  93             assert behave_ra = result
  94                 report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
  95         end loop;
  96
  97         -- rldicr, rldcr
  98         report "test rld[i]cr";
  99         ra <= (others => '0');
 100         is_32bit <= '0';
 101         right_shift <= '0';
 102         arith <= '0';
 103         clear_left <= '0';
 104         clear_right <= '1';
 105         rldicr_loop : for i in 0 to 1000 loop
 106             rs <= pseudorand(64);
 107             shift <= pseudorand(7);
 108             insn <= x"00000" & '0' & pseudorand(10) & '0';
 109             wait for clk_period;
 110             behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
 111             --report "rs = " & to_hstring(rs);
 112             --report "ra = " & to_hstring(ra);
 113             --report "shift = " & to_hstring(shift);
 114             --report "insn me = " & to_hstring(insn_me(insn));
 115             --report "result = " & to_hstring(result);
 116             assert behave_ra = result
 117                 report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 118         end loop;
 119
 120         -- rldic
 121         report "test rldic";
 122         ra <= (others => '0');
 123         is_32bit <= '0';
 124         right_shift <= '0';
 125         arith <= '0';
 126         clear_left <= '1';
 127         clear_right <= '1';
 128         rldic_loop : for i in 0 to 1000 loop
 129             rs <= pseudorand(64);
 130             shift <= '0' & pseudorand(6);
 131             insn <= x"00000" & '0' & pseudorand(10) & '0';
 132             wait for clk_period;
 133             behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
 134             assert behave_ra = result
 135                 report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 136         end loop;
 137
 138         -- rldimi
 139         report "test rldimi";
 140         is_32bit <= '0';
 141         right_shift <= '0';
 142         arith <= '0';
 143         clear_left <= '1';
 144         clear_right <= '1';
 145         rldimi_loop : for i in 0 to 1000 loop
 146             rs <= pseudorand(64);
 147             ra <= pseudorand(64);
 148             shift <= '0' & pseudorand(6);
 149             insn <= x"00000" & '0' & pseudorand(10) & '0';
 150             wait for clk_period;
 151             behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
 152             assert behave_ra = result
 153                 report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 154         end loop;
 155
 156         -- slw
 157         report "test slw";
 158         ra <= (others => '0');
 159         is_32bit <= '1';
 160         right_shift <= '0';
 161         arith <= '0';
 162         clear_left <= '0';
 163         clear_right <= '0';
 164         slw_loop : for i in 0 to 1000 loop
 165             rs <= pseudorand(64);
 166             shift <= pseudorand(7);
 167             wait for clk_period;
 168             behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 169             assert behave_ra = result
 170                 report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 171         end loop;
 172
 173         -- sld
 174         report "test sld";
 175         ra <= (others => '0');
 176         is_32bit <= '0';
 177         right_shift <= '0';
 178         arith <= '0';
 179         clear_left <= '0';
 180         clear_right <= '0';
 181         sld_loop : for i in 0 to 1000 loop
 182             rs <= pseudorand(64);
 183             shift <= pseudorand(7);
 184             wait for clk_period;
 185             behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 186             assert behave_ra = result
 187                 report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 188         end loop;
 189
 190         -- srw
 191         report "test srw";
 192         ra <= (others => '0');
 193         is_32bit <= '1';
 194         right_shift <= '1';
 195         arith <= '0';
 196         clear_left <= '0';
 197         clear_right <= '0';
 198         srw_loop : for i in 0 to 1000 loop
 199             rs <= pseudorand(64);
 200             shift <= pseudorand(7);
 201             wait for clk_period;
 202             behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 203             assert behave_ra = result
 204                 report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 205         end loop;
 206
 207         -- srd
 208         report "test srd";
 209         ra <= (others => '0');
 210         is_32bit <= '0';
 211         right_shift <= '1';
 212         arith <= '0';
 213         clear_left <= '0';
 214         clear_right <= '0';
 215         srd_loop : for i in 0 to 1000 loop
 216             rs <= pseudorand(64);
 217             shift <= pseudorand(7);
 218             wait for clk_period;
 219             behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 220             assert behave_ra = result
 221                 report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
 222         end loop;
 223
 224         -- sraw[i]
 225         report "test sraw[i]";
 226         ra <= (others => '0');
 227         is_32bit <= '1';
 228         right_shift <= '1';
 229         arith <= '1';
 230         clear_left <= '0';
 231         clear_right <= '0';
 232         sraw_loop : for i in 0 to 1000 loop
 233             rs <= pseudorand(64);
 234             shift <= '0' & pseudorand(6);
 235             wait for clk_period;
 236             behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 237             --report "rs = " & to_hstring(rs);
 238             --report "ra = " & to_hstring(ra);
 239             --report "shift = " & to_hstring(shift);
 240             --report "result = " & to_hstring(carry_out & result);
 241             assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
 242                 report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
 243         end loop;
 244
 245         -- srad[i]
 246         report "test srad[i]";
 247         ra <= (others => '0');
 248         is_32bit <= '0';
 249         right_shift <= '1';
 250         arith <= '1';
 251         clear_left <= '0';
 252         clear_right <= '0';
 253         srad_loop : for i in 0 to 1000 loop
 254             rs <= pseudorand(64);
 255             shift <= pseudorand(7);
 256             wait for clk_period;
 257             behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 258             --report "rs = " & to_hstring(rs);
 259             --report "ra = " & to_hstring(ra);
 260             --report "shift = " & to_hstring(shift);
 261             --report "result = " & to_hstring(carry_out & result);
 262             assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
 263                 report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
 264         end loop;
 265
 266         assert false report "end of test" severity failure;
 267         wait;
 268     end process;
 269 end behave;