run.py

   1 #!/usr/bin/env python3
   2
   3 import json
   4 from pathlib import Path
   5 from vunit import VUnit
   6
   7 ROOT = Path(__file__).parent
   8
   9 PRJ = VUnit.from_argv()
  10 PRJ.add_vhdl_builtins()
  11 PRJ.add_osvvm()
  12
  13 PRJ.add_library("lib").add_source_files([
  14     ROOT / "litedram" / "extras" / "*.vhdl",
  15     ROOT / "litedram" / "generated" / "sim" / "*.vhdl"
  16 ] + [
  17     src_file
  18     for src_file in ROOT.glob("*.vhdl")
  19     # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
  20     if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom", "dmi_dtm_ecp5", "dmi_dtm_xilinx"])
  21 ])
  22
  23 PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl")
  24
  25 PRJ.set_sim_option("disable_ieee_warnings", True)
  26
  27 def _gen_vhdl_ls(vu):
  28     """
  29     Generate the vhdl_ls.toml file required by VHDL-LS language server.
  30     """
  31     # Repo root
  32     parent = Path(__file__).parent
  33
  34     proj = vu._project
  35     libs = proj.get_libraries()
  36
  37     with open(parent / 'vhdl_ls.toml', "w") as f:
  38         for lib in libs:
  39             f.write(f"[libraries.{lib.name}]\n")
  40             files = [str(file).replace('\\', '/') for file in lib._source_files]
  41             f.write(f"files = {json.dumps(files, indent=4)}\n")
  42
  43 _gen_vhdl_ls(PRJ)
  44 PRJ.main()