f9d82cf98a20c5580e8e37e7b1290f9851bd0160
[libreriscv.git] / shakti / m_class / SPI.mdwn
1 # SPI
2
3 * <http://bugs.libre-riscv.org/show_bug.cgi?id=6>
4 * Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
5 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
6 includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM. Also included
7 is a Watchdog Timer and others.
8 * APB to SPI <https://opencores.org/project,apb2spi>
9 * ASIC-proven <https://opencores.org/project,spi_master_slave>
10 * Wishbone-compliant <https://opencores.org/project,simple_spi>
11