simple_v_extension/specification/sv.setvl.mdwn

   1 [[!tag oldstandards]]
   2
   3 **OBSOLETE**
   4
   5 # SV setvl
   6
   7 sv.setvl allows optional setting of both MVL and of indirectly marking
   8 one of the scalar registers as being VL.
   9
  10 Unlike the majority of other CSRs, which contain status bits that change
  11 behaviour, VL is closely interlinked with the instructions it affects
  12 and often requires arithmetic interaction.  Thus it makes more sense to
  13 actually *use* one of the scalar registers *as* VL.
  14
  15 Format for Vector Configuration Instructions under OP-V major opcode:
  16
  17 | 31|30...20|19....15|14..12|11.7|6.....0| name       |
  18 |---|-------|--------|------|----|-------|------------|
  19 | 0 | VLMAX | rs1    | 111  | rd |1010111| sv.setvl   |
  20 | 0 | VLMAX | 0 (x0) | 111  | rd |1010111| sv.setvl   |
  21 | 1 | --    | --     | 111  | -- |1010111| *reserved* |
  22
  23
  24 # pseudocode
  25
  26     regs = [0u64; 128];
  27     vlval = 0;
  28     vl = rd;
  29
  30     // instruction fields:
  31     rd = get_rd_field();
  32     rs1 = get_rs1_field();
  33     vlmax = get_immed_field();
  34
  35     // handle illegal instruction decoding
  36     if vlmax > XLEN {
  37         trap()
  38     }
  39
  40     // calculate VL
  41     if rs1 == 0 { // rs1 is x0
  42         vlval = vlmax
  43     } else {
  44         vlval = min(regs[rs1], vlmax)
  45     }
  46
  47     // write rd
  48     if rd != 0 {
  49         // rd is not x0
  50         regs[rd] = vlval;
  51     }
  52
  53 # questions <a name="questions"></>
  54
  55 Moved to [[discussion]]
  56