1 # rad the main peripheral fabric, then uart16550, and finally libresoc core
2 # we do not have to do include the micron ddr3 model or the lattice ecp5
3 # models because apparently they're good to go, already (icarus is a lot
4 # stricter than verilator, hence the munging below)
7 read_ilang build_simsoc/top.il
9 # main core (any core, it's all good)
10 read_verilog ./external_core_top.v
13 read_verilog ../uart16550/rtl/verilog/raminfr.v
14 read_verilog ../uart16550/rtl/verilog/uart_defines.v
15 read_verilog ../uart16550/rtl/verilog/uart_rfifo.v
16 read_verilog ../uart16550/rtl/verilog/uart_top.v
17 read_verilog ../uart16550/rtl/verilog/timescale.v
18 read_verilog ../uart16550/rtl/verilog/uart_sync_flops.v
19 read_verilog ../uart16550/rtl/verilog/uart_debug_if.v
20 read_verilog ../uart16550/rtl/verilog/uart_regs.v
21 read_verilog ../uart16550/rtl/verilog/uart_transmitter.v
22 read_verilog ../uart16550/rtl/verilog/uart_receiver.v
23 read_verilog ../uart16550/rtl/verilog/uart_tfifo.v
24 read_verilog ../uart16550/rtl/verilog/uart_wb.v
27 read_verilog ../tercel-qspi/tercel/phy.v
28 read_verilog ../tercel-qspi/tercel/wishbone_spi_master.v
31 read_verilog ../verilog-wishbone/rtl/wb_async_reg.v
33 # errors in the ethmac rtl, comment out for now
34 #read_verilog ../ethmac/rtl/verilog/eth_clockgen.v
35 #read_verilog ../ethmac/rtl/verilog/eth_cop.v
36 #read_verilog ../ethmac/rtl/verilog/eth_crc.v
37 #read_verilog ../ethmac/rtl/verilog/eth_fifo.v
38 #read_verilog ../ethmac/rtl/verilog/eth_maccontrol.v
39 #read_verilog ../ethmac/rtl/verilog/ethmac_defines.v
40 #read_verilog ../ethmac/rtl/verilog/eth_macstatus.v
41 #read_verilog ../ethmac/rtl/verilog/ethmac.v
42 #read_verilog ../ethmac/rtl/verilog/eth_miim.v
43 #read_verilog ../ethmac/rtl/verilog/eth_outputcontrol.v
44 #read_verilog ../ethmac/rtl/verilog/eth_random.v
45 #read_verilog ../ethmac/rtl/verilog/eth_receivecontrol.v
46 #read_verilog ../ethmac/rtl/verilog/eth_registers.v
47 #read_verilog ../ethmac/rtl/verilog/eth_register.v
48 #read_verilog ../ethmac/rtl/verilog/eth_rxaddrcheck.v
49 #read_verilog ../ethmac/rtl/verilog/eth_rxcounters.v
50 #read_verilog ../ethmac/rtl/verilog/eth_rxethmac.v
51 #read_verilog ../ethmac/rtl/verilog/eth_rxstatem.v
52 #read_verilog ../ethmac/rtl/verilog/eth_shiftreg.v
53 #read_verilog ../ethmac/rtl/verilog/eth_spram_256x32.v
54 #read_verilog ../ethmac/rtl/verilog/eth_top.v
55 #read_verilog ../ethmac/rtl/verilog/eth_transmitcontrol.v
56 #read_verilog ../ethmac/rtl/verilog/eth_txcounters.v
57 #read_verilog ../ethmac/rtl/verilog/eth_txethmac.v
58 #read_verilog ../ethmac/rtl/verilog/eth_txstatem.v
59 #read_verilog ../ethmac/rtl/verilog/eth_wishbone.v
60 #read_verilog ../ethmac/rtl/verilog/timescale.v
62 # stop yosys deleting stuff
63 setattr -mod -set keep 1 uart_transmitter
64 setattr -mod -set keep 1 uart_receiver
66 delete w:$verilog_initial_trigger
68 # these are most of "proc"
82 # these are important to do in this order
94 write_verilog -norename top.v