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add qcxxrtl compile
[soc-cxxrtl-sim.git]
/
small_jtag_test
/
Makefile
1
2
YOSYS
=
yosys
3
YOSYS_INCLUDE
= $(
shell
yosys-config
--
datdir
)/
include
4
5
all
:
tb
6
.
/
tb
7
8
tb
:
main.
cpp
add.
cpp
9
clang
++ -
g
-
O3
-
std
=
c
++
14
-
I
$(
YOSYS_INCLUDE
) $< -
o
$
@
10
11
add.
cpp
:
add.v
12
$(
YOSYS
) -
p
"read_verilog $<; write_cxxrtl $@"
13
14
# build verilog from nmigen
15
add.v
:
add.py
16
python3 add.py
17
18
clean
:
19
\r
m
-
f add.
cpp
tb add.v