small_jtag_test/Makefile

   1
   2 YOSYS                   = yosys
   3 YOSYS_INCLUDE   = $(shell yosys-config --datdir)/include
   4
   5 all: tb
   6         ./tb
   7
   8 tb_ghdl: main.cpp add_ghdl.cpp
   9         clang++ \
  10     -DDESIGN=cxxrtl_design::p_add \
  11     -DCXX_FILE=\"add_ghdl.cpp\" \
  12     -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
  13
  14 tb: main.cpp add.cpp
  15         clang++ \
  16     -DDESIGN=cxxrtl_design::p_add \
  17     -DCXX_FILE=\"add.cpp\" \
  18     -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
  19
  20 add.cpp: add.v
  21         $(YOSYS) -p "read_verilog $<; write_cxxrtl $@"
  22
  23 # build verilog from nmigen
  24 add.v: add.py
  25         python3 add.py
  26
  27 clean:
  28         \rm -f add.cpp tb add.v