small_jtag_test/freepdk_45/sff1r_x4.vhd

   1 --
   2 -- Generated by VASY
   3 --
   4 LIBRARY IEEE;
   5 USE IEEE.std_logic_1164.ALL;
   6 USE IEEE.numeric_std.ALL;
   7
   8 ENTITY sff1r_x4 IS
   9 PORT(
  10   ck    : IN BIT;
  11   i     : IN BIT;
  12   nrst  : IN BIT;
  13   q     : OUT BIT;
  14   vdd   : IN BIT;
  15   vss   : IN BIT
  16 );
  17 END sff1r_x4;
  18
  19 ARCHITECTURE RTL OF sff1r_x4 IS
  20   SIGNAL sff_m  : BIT;
  21 BEGIN
  22   q <= sff_m;
  23   PROCESS ( ck, nrst )
  24   BEGIN
  25     IF  ((ck = '1') AND ck'EVENT)
  26     THEN
  27         IF (nrst = '1')
  28         THEN sff_m <= i;
  29         END IF;
  30     END IF;
  31     IF  ((nrst = '0') AND nrst'EVENT)
  32     THEN sff_m <= '0';
  33     END IF;
  34   END PROCESS;
  35 END RTL;