soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
  14 --
  15 -- Main bus:
  16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
  17 -- 0x40000000: DRAM (when present)
  18 -- 0x80000000: Block RAM (aliased & repeated)
  19
  20 -- IO Bus:
  21 -- 0xc0000000: SYSCON
  22 -- 0xc0002000: UART0
  23 -- 0xc0003000: UART1 (if any)
  24 -- 0xc0004000: XICS ICP
  25 -- 0xc0005000: XICS ICS
  26 -- 0xc0006000: SPI Flash controller
  27 -- 0xc0007000: GPIO controller
  28 -- 0xc8nnnnnn: External IO bus
  29 -- 0xf0000000: Flash "ROM" mapping
  30 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
  31
  32 -- External IO bus:
  33 -- 0xc8000000: LiteDRAM control (CSRs)
  34 -- 0xc8020000: LiteEth CSRs (*)
  35 -- 0xc8030000: LiteEth MMIO (*)
  36 -- 0xc8040000: LiteSDCard CSRs
  37
  38 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
  39 --     are actually decoded as a single wishbone which LiteEth will
  40 --     internally split based on bit 16.
  41
  42 -- (**) DRAM init code is currently special and goes to the external
  43 --      IO bus, this will be fixed when it's moved out of litedram and
  44 --      into the main SoC once we have a common "firmware".
  45
  46 -- Interrupt numbers:
  47 --
  48 --   0  : UART0
  49 --   1  : Ethernet
  50 --   2  : UART1
  51 --   3  : SD card
  52 --   4  : GPIO
  53
  54 -- Resets:
  55 -- The soc can be reset externally by its parent top- entity (via rst port),
  56 -- or can be reset by software via syscon. In the software reset case
  57 -- the reset signal will also be exposed via sw_soc_reset port - toplevels
  58 -- can use that to reset other peripherals if required.
  59 --
  60 -- When using DRAM the alt_reset signal will be high after soc reset, to
  61 -- run sdram init routines. After startup software will switch alt_reset to
  62 -- low, so a core reset will use the non-alt reset address.
  63
  64 entity soc is
  65     generic (
  66         MEMORY_SIZE        : natural;
  67         RAM_INIT_FILE      : string;
  68         CLK_FREQ           : positive;
  69         SIM                : boolean;
  70         HAS_FPU            : boolean := true;
  71         HAS_BTC            : boolean := true;
  72         DISABLE_FLATTEN_CORE : boolean := false;
  73         ALT_RESET_ADDRESS  : std_logic_vector(63 downto 0) := (23 downto 0 => '0', others => '1');
  74         HAS_DRAM           : boolean  := false;
  75         DRAM_SIZE          : integer := 0;
  76         DRAM_INIT_SIZE     : integer := 0;
  77         HAS_SPI_FLASH      : boolean := false;
  78         SPI_FLASH_DLINES   : positive := 1;
  79         SPI_FLASH_OFFSET   : integer := 0;
  80         SPI_FLASH_DEF_CKDV : natural := 2;
  81         SPI_FLASH_DEF_QUAD : boolean := false;
  82         SPI_BOOT_CLOCKS    : boolean := true;
  83         LOG_LENGTH         : natural := 512;
  84         HAS_LITEETH        : boolean := false;
  85         UART0_IS_16550     : boolean := true;
  86         HAS_UART1          : boolean := false;
  87         ICACHE_NUM_LINES   : natural := 64;
  88         ICACHE_NUM_WAYS    : natural := 2;
  89         ICACHE_TLB_SIZE    : natural := 64;
  90         DCACHE_NUM_LINES   : natural := 64;
  91         DCACHE_NUM_WAYS    : natural := 2;
  92         DCACHE_TLB_SET_SIZE : natural := 64;
  93         DCACHE_TLB_NUM_WAYS : natural := 2;
  94         HAS_SD_CARD        : boolean := false;
  95         HAS_GPIO           : boolean := false;
  96         NGPIO              : natural := 32
  97         );
  98     port(
  99         rst          : in  std_ulogic;
 100         system_clk   : in  std_ulogic;
 101
 102         -- "Large" (64-bit) DRAM wishbone
 103         wb_dram_in       : out wishbone_master_out;
 104         wb_dram_out      : in wishbone_slave_out := wishbone_slave_out_init;
 105
 106         -- "Small" (32-bit) external IO wishbone
 107         wb_ext_io_in         : out wb_io_master_out;
 108         wb_ext_io_out        : in wb_io_slave_out := wb_io_slave_out_init;
 109         wb_ext_is_dram_csr   : out std_ulogic;
 110         wb_ext_is_dram_init  : out std_ulogic;
 111         wb_ext_is_eth        : out std_ulogic;
 112         wb_ext_is_sdcard     : out std_ulogic;
 113
 114         -- external DMA wishbone with 32-bit data/address
 115         wishbone_dma_in      : out wb_io_slave_out := wb_io_slave_out_init;
 116         wishbone_dma_out     : in wb_io_master_out := wb_io_master_out_init;
 117
 118         -- External interrupts
 119         ext_irq_eth          : in std_ulogic := '0';
 120         ext_irq_sdcard       : in std_ulogic := '0';
 121
 122         -- UART0 signals:
 123         uart0_txd    : out std_ulogic;
 124         uart0_rxd    : in  std_ulogic := '0';
 125
 126         -- UART1 signals:
 127         uart1_txd    : out std_ulogic;
 128         uart1_rxd    : in  std_ulogic := '0';
 129
 130         -- SPI Flash signals
 131         spi_flash_sck     : out std_ulogic;
 132         spi_flash_cs_n    : out std_ulogic;
 133         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 134         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 135         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
 136
 137         -- GPIO signals
 138         gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);
 139         gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);
 140         gpio_in  : in  std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
 141
 142         -- SOC reset trigger from syscon
 143         sw_soc_reset : out std_ulogic
 144         );
 145 end entity soc;
 146
 147 architecture behaviour of soc is
 148
 149     -- internal reset
 150     signal soc_reset : std_ulogic;
 151
 152     -- Wishbone master signals:
 153     signal wishbone_dcore_in  : wishbone_slave_out;
 154     signal wishbone_dcore_out : wishbone_master_out;
 155     signal wishbone_icore_in  : wishbone_slave_out;
 156     signal wishbone_icore_out : wishbone_master_out;
 157     signal wishbone_debug_in  : wishbone_slave_out;
 158     signal wishbone_debug_out : wishbone_master_out;
 159
 160     -- Arbiter array (ghdl doesnt' support assigning the array
 161     -- elements in the entity instantiation)
 162     constant NUM_WB_MASTERS : positive := 4;
 163     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
 164     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
 165
 166     -- Wishbone master (output of arbiter):
 167     signal wb_master_in       : wishbone_slave_out;
 168     signal wb_master_out      : wishbone_master_out;
 169     signal wb_snoop           : wishbone_master_out;
 170
 171     -- Main "IO" bus, from main slave decoder to the latch
 172     signal wb_io_in     : wishbone_master_out;
 173     signal wb_io_out    : wishbone_slave_out;
 174
 175     -- Secondary (smaller) IO bus after the IO bus latch
 176     signal wb_sio_out    : wb_io_master_out;
 177     signal wb_sio_in     : wb_io_slave_out;
 178
 179     -- Syscon signals
 180     signal dram_at_0     : std_ulogic;
 181     signal do_core_reset    : std_ulogic;
 182     signal alt_reset     : std_ulogic;
 183     signal wb_syscon_in  : wb_io_master_out;
 184     signal wb_syscon_out : wb_io_slave_out;
 185
 186     -- UART0 signals:
 187     signal wb_uart0_in   : wb_io_master_out;
 188     signal wb_uart0_out  : wb_io_slave_out;
 189     signal uart0_dat8    : std_ulogic_vector(7 downto 0);
 190     signal uart0_irq     : std_ulogic;
 191
 192     -- UART1 signals:
 193     signal wb_uart1_in   : wb_io_master_out;
 194     signal wb_uart1_out  : wb_io_slave_out;
 195     signal uart1_dat8    : std_ulogic_vector(7 downto 0);
 196     signal uart1_irq     : std_ulogic;
 197
 198     -- SPI Flash controller signals:
 199     signal wb_spiflash_in     : wb_io_master_out;
 200     signal wb_spiflash_out    : wb_io_slave_out;
 201     signal wb_spiflash_is_reg : std_ulogic;
 202     signal wb_spiflash_is_map : std_ulogic;
 203
 204     -- XICS signals:
 205     signal wb_xics_icp_in   : wb_io_master_out;
 206     signal wb_xics_icp_out  : wb_io_slave_out;
 207     signal wb_xics_ics_in   : wb_io_master_out;
 208     signal wb_xics_ics_out  : wb_io_slave_out;
 209     signal int_level_in     : std_ulogic_vector(15 downto 0);
 210     signal ics_to_icp       : ics_to_icp_t;
 211     signal core_ext_irq     : std_ulogic;
 212
 213     -- GPIO signals:
 214     signal wb_gpio_in    : wb_io_master_out;
 215     signal wb_gpio_out   : wb_io_slave_out;
 216     signal gpio_intr     : std_ulogic := '0';
 217
 218     -- Main memory signals:
 219     signal wb_bram_in     : wishbone_master_out;
 220     signal wb_bram_out    : wishbone_slave_out;
 221
 222     -- DMI debug bus signals
 223     signal dmi_addr     : std_ulogic_vector(7 downto 0);
 224     signal dmi_din      : std_ulogic_vector(63 downto 0);
 225     signal dmi_dout     : std_ulogic_vector(63 downto 0);
 226     signal dmi_req      : std_ulogic;
 227     signal dmi_wr       : std_ulogic;
 228     signal dmi_ack      : std_ulogic;
 229
 230     -- Per slave DMI signals
 231     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
 232     signal dmi_wb_req   : std_ulogic;
 233     signal dmi_wb_ack   : std_ulogic;
 234     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
 235     signal dmi_core_req   : std_ulogic;
 236     signal dmi_core_ack   : std_ulogic;
 237
 238     -- Delayed/latched resets and alt_reset
 239     signal rst_core    : std_ulogic;
 240     signal rst_uart    : std_ulogic;
 241     signal rst_xics    : std_ulogic;
 242     signal rst_spi     : std_ulogic;
 243     signal rst_gpio    : std_ulogic;
 244     signal rst_bram    : std_ulogic;
 245     signal rst_dtm     : std_ulogic;
 246     signal rst_wbar    : std_ulogic;
 247     signal rst_wbdb    : std_ulogic;
 248     signal alt_reset_d : std_ulogic;
 249
 250     -- IO branch split:
 251     type slave_io_type is (SLAVE_IO_SYSCON,
 252                            SLAVE_IO_UART,
 253                            SLAVE_IO_ICP,
 254                            SLAVE_IO_ICS,
 255                            SLAVE_IO_UART1,
 256                            SLAVE_IO_SPI_FLASH,
 257                            SLAVE_IO_GPIO,
 258                            SLAVE_IO_EXTERNAL);
 259     signal current_io_decode : slave_io_type;
 260
 261     signal io_cycle_none      : std_ulogic;
 262     signal io_cycle_syscon    : std_ulogic;
 263     signal io_cycle_uart      : std_ulogic;
 264     signal io_cycle_uart1     : std_ulogic;
 265     signal io_cycle_icp       : std_ulogic;
 266     signal io_cycle_ics       : std_ulogic;
 267     signal io_cycle_spi_flash : std_ulogic;
 268     signal io_cycle_gpio      : std_ulogic;
 269     signal io_cycle_external  : std_ulogic;
 270
 271     function wishbone_widen_data(wb : wb_io_master_out) return wishbone_master_out is
 272         variable wwb : wishbone_master_out;
 273     begin
 274         wwb.adr := wb.adr(wb.adr'left downto 1);
 275         wwb.dat := wb.dat & wb.dat;
 276         wwb.sel := x"00";
 277         if wb.adr(0) = '0' then
 278             wwb.sel(3 downto 0) := wb.sel;
 279         else
 280             wwb.sel(7 downto 4) := wb.sel;
 281         end if;
 282         wwb.cyc := wb.cyc;
 283         wwb.stb := wb.stb;
 284         wwb.we := wb.we;
 285         return wwb;
 286     end;
 287
 288     function wishbone_narrow_data(wwbs : wishbone_slave_out; adr : std_ulogic_vector(29 downto 0))
 289         return wb_io_slave_out is
 290         variable wbs : wb_io_slave_out;
 291     begin
 292         wbs.ack := wwbs.ack;
 293         wbs.stall := wwbs.stall;
 294         if adr(0) = '0' then
 295             wbs.dat := wwbs.dat(31 downto 0);
 296         else
 297             wbs.dat := wwbs.dat(63 downto 32);
 298         end if;
 299         return wbs;
 300     end;
 301
 302     -- This is the component exported by the 16550 compatible
 303     -- UART from FuseSoC.
 304     --
 305     component uart_top port (
 306         wb_clk_i    : in std_ulogic;
 307         wb_rst_i    : in std_ulogic;
 308         wb_adr_i    : in std_ulogic_vector(2 downto 0);
 309         wb_dat_i    : in std_ulogic_vector(7 downto 0);
 310         wb_dat_o    : out std_ulogic_vector(7 downto 0);
 311         wb_we_i     : in std_ulogic;
 312         wb_stb_i    : in std_ulogic;
 313         wb_cyc_i    : in std_ulogic;
 314         wb_ack_o    : out std_ulogic;
 315         int_o       : out std_ulogic;
 316         stx_pad_o   : out std_ulogic;
 317         srx_pad_i   : in std_ulogic;
 318         rts_pad_o   : out std_ulogic;
 319         cts_pad_i   : in std_ulogic;
 320         dtr_pad_o   : out std_ulogic;
 321         dsr_pad_i   : in std_ulogic;
 322         ri_pad_i    : in std_ulogic;
 323         dcd_pad_i   : in std_ulogic
 324         );
 325     end component;
 326
 327 begin
 328
 329     -- either external reset, or from syscon
 330     soc_reset <= rst or sw_soc_reset;
 331
 332     resets: process(system_clk)
 333     begin
 334         if rising_edge(system_clk) then
 335             rst_core    <= soc_reset or do_core_reset;
 336             rst_uart    <= soc_reset;
 337             rst_spi     <= soc_reset;
 338             rst_xics    <= soc_reset;
 339             rst_gpio    <= soc_reset;
 340             rst_bram    <= soc_reset;
 341             rst_dtm     <= soc_reset;
 342             rst_wbar    <= soc_reset;
 343             rst_wbdb    <= soc_reset;
 344             alt_reset_d <= alt_reset;
 345         end if;
 346     end process;
 347
 348     -- Processor core
 349     processor: entity work.core
 350         generic map(
 351             SIM => SIM,
 352             HAS_FPU => HAS_FPU,
 353             HAS_BTC => HAS_BTC,
 354             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 355             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 356             LOG_LENGTH => LOG_LENGTH,
 357             ICACHE_NUM_LINES => ICACHE_NUM_LINES,
 358             ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
 359             ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
 360             DCACHE_NUM_LINES => DCACHE_NUM_LINES,
 361             DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
 362             DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
 363             DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
 364             )
 365         port map(
 366             clk => system_clk,
 367             rst => rst_core,
 368             alt_reset => alt_reset_d,
 369             wishbone_insn_in => wishbone_icore_in,
 370             wishbone_insn_out => wishbone_icore_out,
 371             wishbone_data_in => wishbone_dcore_in,
 372             wishbone_data_out => wishbone_dcore_out,
 373             wb_snoop_in => wb_snoop,
 374             dmi_addr => dmi_addr(3 downto 0),
 375             dmi_dout => dmi_core_dout,
 376             dmi_din => dmi_dout,
 377             dmi_wr => dmi_wr,
 378             dmi_ack => dmi_core_ack,
 379             dmi_req => dmi_core_req,
 380             ext_irq => core_ext_irq
 381             );
 382
 383     -- Wishbone bus master arbiter & mux
 384     wb_masters_out <= (0 => wishbone_dcore_out,
 385                        1 => wishbone_icore_out,
 386                        2 => wishbone_widen_data(wishbone_dma_out),
 387                        3 => wishbone_debug_out);
 388     wishbone_dcore_in <= wb_masters_in(0);
 389     wishbone_icore_in <= wb_masters_in(1);
 390     wishbone_dma_in   <= wishbone_narrow_data(wb_masters_in(2), wishbone_dma_out.adr);
 391     wishbone_debug_in <= wb_masters_in(3);
 392     wishbone_arbiter_0: entity work.wishbone_arbiter
 393         generic map(
 394             NUM_MASTERS => NUM_WB_MASTERS
 395             )
 396         port map(
 397             clk => system_clk,
 398             rst => rst_wbar,
 399             wb_masters_in => wb_masters_out,
 400             wb_masters_out => wb_masters_in,
 401             wb_slave_out => wb_master_out,
 402             wb_slave_in => wb_master_in
 403             );
 404
 405     -- Snoop bus going to caches.
 406     -- Gate stb with stall so the caches don't see the stalled strobes.
 407     -- That way if the caches see a strobe when their wishbone is stalled,
 408     -- they know it is an access by another master.
 409     process(all)
 410     begin
 411         wb_snoop <= wb_master_out;
 412         if wb_master_in.stall = '1' then
 413             wb_snoop.stb <= '0';
 414         end if;
 415     end process;
 416
 417     -- Top level Wishbone slaves address decoder & mux
 418     --
 419     -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
 420     -- 0000  - BRAM
 421     -- 0001  - DRAM
 422     -- 01xx  - DRAM
 423     -- 10xx  - BRAM
 424     -- 11xx  - IO
 425     --
 426     slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
 427         type slave_top_type is (SLAVE_TOP_BRAM,
 428                                 SLAVE_TOP_DRAM,
 429                                 SLAVE_TOP_IO);
 430         variable slave_top : slave_top_type;
 431         variable top_decode : std_ulogic_vector(3 downto 0);
 432     begin
 433         -- Top-level address decoder
 434         top_decode := wb_master_out.adr(28 downto 26) & dram_at_0;
 435         slave_top := SLAVE_TOP_BRAM;
 436         if    std_match(top_decode, "0000") then
 437             slave_top := SLAVE_TOP_BRAM;
 438         elsif std_match(top_decode, "0001") then
 439             slave_top := SLAVE_TOP_DRAM;
 440         elsif std_match(top_decode, "01--") then
 441             slave_top := SLAVE_TOP_DRAM;
 442         elsif std_match(top_decode, "10--") then
 443             slave_top := SLAVE_TOP_BRAM;
 444         elsif std_match(top_decode, "11--") then
 445             slave_top := SLAVE_TOP_IO;
 446         end if;
 447
 448         -- Top level wishbone muxing.
 449         wb_bram_in <= wb_master_out;
 450         wb_bram_in.cyc  <= '0';
 451         wb_dram_in <= wb_master_out;
 452         wb_dram_in.cyc  <= '0';
 453         wb_io_in <= wb_master_out;
 454         wb_io_in.cyc  <= '0';
 455         case slave_top is
 456         when SLAVE_TOP_BRAM =>
 457             wb_bram_in.cyc <= wb_master_out.cyc;
 458             wb_master_in <= wb_bram_out;
 459         when SLAVE_TOP_DRAM =>
 460             if HAS_DRAM then
 461                 wb_dram_in.cyc <= wb_master_out.cyc;
 462                 wb_master_in <= wb_dram_out;
 463             else
 464                 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
 465                 wb_master_in.dat <= (others => '1');
 466                 wb_master_in.stall <= '0';
 467             end if;
 468         when SLAVE_TOP_IO =>
 469             wb_io_in.cyc <= wb_master_out.cyc;
 470             wb_master_in <= wb_io_out;
 471         end case;
 472
 473     end process slave_top_intercon;
 474
 475     -- IO wishbone slave 64->32 bits converter
 476     --
 477     -- For timing reasons, this adds a one cycle latch on the way both
 478     -- in and out. This relaxes timing and routing pressure on the "main"
 479     -- memory bus by moving all simple IOs to a slower 32-bit bus.
 480     --
 481     -- This implementation is rather dumb at the moment, no stash buffer,
 482     -- so we stall whenever that latch is busy. This can be improved.
 483     --
 484     slave_io_latch: process(system_clk)
 485         -- State
 486         type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
 487         variable state : state_t;
 488
 489         -- Misc
 490         variable has_top : boolean;
 491         variable has_bot : boolean;
 492         variable do_cyc  : std_ulogic;
 493         variable end_cyc : std_ulogic;
 494         variable slave_io : slave_io_type;
 495         variable match   : std_ulogic_vector(31 downto 12);
 496         variable dat_latch : std_ulogic_vector(31 downto 0);
 497         variable sel_latch : std_ulogic_vector(3 downto 0);
 498     begin
 499         if rising_edge(system_clk) then
 500             do_cyc := '0';
 501             end_cyc := '0';
 502             if (soc_reset) then
 503                 state := IDLE;
 504                 wb_io_out.ack <= '0';
 505                 wb_io_out.stall <= '0';
 506                 wb_sio_out.stb <= '0';
 507                 end_cyc := '1';
 508                 has_top := false;
 509                 has_bot := false;
 510                 dat_latch := (others => '0');
 511                 sel_latch := (others => '0');
 512             else
 513                 case state is
 514                 when IDLE =>
 515                     -- Clear ACK in case it was set
 516                     wb_io_out.ack <= '0';
 517
 518                     -- Do we have a cycle ?
 519                     if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
 520                         -- Stall master until we are done, we are't (yet) pipelining
 521                         -- this, it's all slow IOs. Note: The current cycle has
 522                         -- already been accepted as "stall" was 0, this only blocks
 523                         -- the next one. This means that we must latch
 524                         -- everything we need from wb_io_in in *this* cycle.
 525                         --
 526                         wb_io_out.stall <= '1';
 527
 528                         -- Start cycle downstream
 529                         do_cyc := '1';
 530                         wb_sio_out.stb <= '1';
 531
 532                         -- Copy write enable to IO out, copy address as well
 533                         wb_sio_out.we <= wb_io_in.we;
 534                         wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left - 1 downto 0) & '0';
 535
 536                         -- Do we have a top word and/or a bottom word ?
 537                         has_top := wb_io_in.sel(7 downto 4) /= "0000";
 538                         has_bot := wb_io_in.sel(3 downto 0) /= "0000";
 539
 540                         -- Remember the top word as it might be needed later
 541                         dat_latch := wb_io_in.dat(63 downto 32);
 542                         sel_latch := wb_io_in.sel(7 downto 4);
 543
 544                         -- If we have a bottom word, handle it first, otherwise
 545                         -- send the top word down.
 546                         if has_bot then
 547                             -- Always update out.dat, it doesn't matter if we
 548                             -- update it on reads and it saves  mux
 549                             wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
 550                             wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
 551
 552                             -- Wait for ack
 553                             state := WAIT_ACK_BOT;
 554                         else
 555                             wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 556                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 557
 558                             -- Bump address
 559                             wb_sio_out.adr(0) <= '1';
 560
 561                             -- Wait for ack
 562                             state := WAIT_ACK_TOP;
 563                         end if;
 564                     end if;
 565                 when WAIT_ACK_BOT =>
 566                     -- If we aren't stalled by the device, clear stb
 567                     if wb_sio_in.stall = '0' then
 568                         wb_sio_out.stb <= '0';
 569                     end if;
 570
 571                     -- Handle ack
 572                     if wb_sio_in.ack = '1' then
 573                          -- Always latch the data, it doesn't matter if it was
 574                          -- a write and it saves a mux
 575                         wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
 576
 577                         -- Do we have a "top" part as well ?
 578                         if has_top then
 579                             wb_sio_out.dat <= dat_latch;
 580                             wb_sio_out.sel <= sel_latch;
 581
 582                             -- Bump address and set STB
 583                             wb_sio_out.adr(0) <= '1';
 584                             wb_sio_out.stb <= '1';
 585
 586                             -- Wait for new ack
 587                             state := WAIT_ACK_TOP;
 588                         else
 589                             -- We are done, ack up, clear cyc downstream
 590                             end_cyc := '1';
 591
 592                             -- And ack & unstall upstream
 593                             wb_io_out.ack <= '1';
 594                             wb_io_out.stall <= '0';
 595
 596                             -- Wait for next one
 597                             state := IDLE;
 598                         end if;
 599                     end if;
 600                 when WAIT_ACK_TOP =>
 601                     -- If we aren't stalled by the device, clear stb
 602                     if wb_sio_in.stall = '0' then
 603                         wb_sio_out.stb <= '0';
 604                     end if;
 605
 606                     -- Handle ack
 607                     if wb_sio_in.ack = '1' then
 608                          -- Always latch the data, it doesn't matter if it was
 609                          -- a write and it saves a mux
 610                         wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
 611
 612                         -- We are done, ack up, clear cyc downstram
 613                         end_cyc := '1';
 614
 615                         -- And ack & unstall upstream
 616                         wb_io_out.ack <= '1';
 617                         wb_io_out.stall <= '0';
 618
 619                         -- Wait for next one
 620                         state := IDLE;
 621                     end if;
 622                 end case;
 623             end if;
 624
 625             -- Create individual registered cycle signals for the wishbones
 626             -- going to the various peripherals
 627             --
 628             -- Note: This needs to happen on the cycle matching state = IDLE,
 629             -- as wb_io_in content can only be relied upon on that one cycle.
 630             -- This works here because do_cyc is a variable, not a signal, and
 631             -- thus here we observe the value set above in the state machine
 632             -- on the same cycle rather than the next one.
 633             --
 634             if do_cyc = '1' or end_cyc = '1' then
 635                 io_cycle_none      <= '0';
 636                 io_cycle_syscon    <= '0';
 637                 io_cycle_uart      <= '0';
 638                 io_cycle_uart1     <= '0';
 639                 io_cycle_icp       <= '0';
 640                 io_cycle_ics       <= '0';
 641                 io_cycle_spi_flash <= '0';
 642                 io_cycle_gpio      <= '0';
 643                 io_cycle_external  <= '0';
 644                 wb_sio_out.cyc     <= '0';
 645                 wb_ext_is_dram_init <= '0';
 646                 wb_spiflash_is_map <= '0';
 647                 wb_spiflash_is_reg <= '0';
 648                 wb_ext_is_dram_csr <= '0';
 649                 wb_ext_is_eth      <= '0';
 650                 wb_ext_is_sdcard   <= '0';
 651             end if;
 652             if do_cyc = '1' then
 653                 -- Decode I/O address
 654                 -- This is real address bits 29 downto 12
 655                 match := "11" & wb_io_in.adr(26 downto 9);
 656                 slave_io := SLAVE_IO_SYSCON;
 657                 if    std_match(match, x"FF---") and HAS_DRAM then
 658                     slave_io := SLAVE_IO_EXTERNAL;
 659                     io_cycle_external <= '1';
 660                     wb_ext_is_dram_init <= '1';
 661                 elsif std_match(match, x"F----") then
 662                     slave_io := SLAVE_IO_SPI_FLASH;
 663                     io_cycle_spi_flash <= '1';
 664                     wb_spiflash_is_map <= '1';
 665                 elsif std_match(match, x"C8---") then
 666                     -- Ext IO "chip selects"
 667                     if    std_match(match, x"--00-") and HAS_DRAM then
 668                         slave_io := SLAVE_IO_EXTERNAL;
 669                         io_cycle_external <= '1';
 670                         wb_ext_is_dram_csr <= '1';
 671                     elsif (std_match(match, x"--02-") or std_match(match, x"--03-")) and
 672                            HAS_LITEETH then
 673                         slave_io := SLAVE_IO_EXTERNAL;
 674                         io_cycle_external <= '1';
 675                         wb_ext_is_eth <= '1';
 676                     elsif std_match(match, x"--04-") and HAS_SD_CARD then
 677                         slave_io := SLAVE_IO_EXTERNAL;
 678                         io_cycle_external <= '1';
 679                         wb_ext_is_sdcard <= '1';
 680                     else
 681                         io_cycle_none <= '1';
 682                     end if;
 683                 elsif std_match(match, x"C0000") then
 684                     slave_io := SLAVE_IO_SYSCON;
 685                     io_cycle_syscon <= '1';
 686                 elsif std_match(match, x"C0002") then
 687                     slave_io := SLAVE_IO_UART;
 688                     io_cycle_uart <= '1';
 689                 elsif std_match(match, x"C0003") then
 690                     slave_io := SLAVE_IO_UART1;
 691                     io_cycle_uart1 <= '1';
 692                 elsif std_match(match, x"C0004") then
 693                     slave_io := SLAVE_IO_ICP;
 694                     io_cycle_icp <= '1';
 695                 elsif std_match(match, x"C0005") then
 696                     slave_io := SLAVE_IO_ICS;
 697                     io_cycle_ics <= '1';
 698                 elsif std_match(match, x"C0006") then
 699                     slave_io := SLAVE_IO_SPI_FLASH;
 700                     io_cycle_spi_flash <= '1';
 701                     wb_spiflash_is_reg <= '1';
 702                 elsif std_match(match, x"C0007") then
 703                     slave_io := SLAVE_IO_GPIO;
 704                     io_cycle_gpio <= '1';
 705                 else
 706                     io_cycle_none <= '1';
 707                 end if;
 708                 current_io_decode <= slave_io;
 709                 wb_sio_out.cyc <= '1';
 710             end if;
 711         end if;
 712     end process;
 713
 714     -- IO wishbone slave interconnect.
 715     --
 716     slave_io_intercon: process(all)
 717     begin
 718         wb_uart0_in <= wb_sio_out;
 719         wb_uart0_in.cyc <= io_cycle_uart;
 720         wb_uart1_in <= wb_sio_out;
 721         wb_uart1_in.cyc <= io_cycle_uart1;
 722
 723         wb_spiflash_in <= wb_sio_out;
 724         wb_spiflash_in.cyc <= io_cycle_spi_flash;
 725         -- Clear top bits so they don't make their way to the
 726         -- flash chip.
 727         wb_spiflash_in.adr(27 downto 26) <= "00";
 728
 729         wb_gpio_in <= wb_sio_out;
 730         wb_gpio_in.cyc <= io_cycle_gpio;
 731
 732          -- Only give xics 8 bits of wb addr (for now...)
 733         wb_xics_icp_in <= wb_sio_out;
 734         wb_xics_icp_in.adr <= (others => '0');
 735         wb_xics_icp_in.adr(5 downto 0) <= wb_sio_out.adr(5 downto 0);
 736         wb_xics_icp_in.cyc  <= io_cycle_icp;
 737         wb_xics_ics_in <= wb_sio_out;
 738         wb_xics_ics_in.adr <= (others => '0');
 739         wb_xics_ics_in.adr(9 downto 0) <= wb_sio_out.adr(9 downto 0);
 740         wb_xics_ics_in.cyc  <= io_cycle_ics;
 741
 742         wb_ext_io_in <= wb_sio_out;
 743         wb_ext_io_in.cyc <= io_cycle_external;
 744
 745         wb_syscon_in <= wb_sio_out;
 746         wb_syscon_in.cyc <= io_cycle_syscon;
 747
 748         case current_io_decode is
 749         when SLAVE_IO_EXTERNAL =>
 750             wb_sio_in <= wb_ext_io_out;
 751         when SLAVE_IO_SYSCON =>
 752             wb_sio_in <= wb_syscon_out;
 753         when SLAVE_IO_UART =>
 754             wb_sio_in <= wb_uart0_out;
 755         when SLAVE_IO_ICP =>
 756             wb_sio_in <= wb_xics_icp_out;
 757         when SLAVE_IO_ICS =>
 758             wb_sio_in <= wb_xics_ics_out;
 759         when SLAVE_IO_UART1 =>
 760             wb_sio_in <= wb_uart1_out;
 761         when SLAVE_IO_SPI_FLASH =>
 762             wb_sio_in <= wb_spiflash_out;
 763         when SLAVE_IO_GPIO =>
 764             wb_sio_in <= wb_gpio_out;
 765         end case;
 766
 767         -- Default response, ack & return all 1's
 768         if io_cycle_none = '1' then
 769             wb_sio_in.dat <= (others => '1');
 770             wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
 771             wb_sio_in.stall <= '0';
 772         end if;
 773
 774     end process;
 775
 776     -- Syscon slave
 777     syscon0: entity work.syscon
 778         generic map(
 779             HAS_UART => true,
 780             HAS_DRAM => HAS_DRAM,
 781             BRAM_SIZE => MEMORY_SIZE,
 782             DRAM_SIZE => DRAM_SIZE,
 783             DRAM_INIT_SIZE => DRAM_INIT_SIZE,
 784             CLK_FREQ => CLK_FREQ,
 785             HAS_SPI_FLASH => HAS_SPI_FLASH,
 786             SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
 787             HAS_LITEETH => HAS_LITEETH,
 788             HAS_SD_CARD => HAS_SD_CARD,
 789             UART0_IS_16550 => UART0_IS_16550,
 790             HAS_UART1 => HAS_UART1
 791         )
 792         port map(
 793             clk => system_clk,
 794             rst => soc_reset,
 795             wishbone_in => wb_syscon_in,
 796             wishbone_out => wb_syscon_out,
 797             dram_at_0 => dram_at_0,
 798             core_reset => do_core_reset,
 799             soc_reset => sw_soc_reset,
 800             alt_reset => alt_reset
 801             );
 802
 803     --
 804     -- UART0
 805     --
 806     -- Either potato (legacy) or 16550
 807     --
 808     uart0_pp: if not UART0_IS_16550 generate
 809         uart0: entity work.pp_soc_uart
 810             generic map(
 811                 FIFO_DEPTH => 32
 812                 )
 813             port map(
 814                 clk => system_clk,
 815                 reset => rst_uart,
 816                 txd => uart0_txd,
 817                 rxd => uart0_rxd,
 818                 irq => uart0_irq,
 819                 wb_adr_in => wb_uart0_in.adr(9 downto 0) & "00",
 820                 wb_dat_in => wb_uart0_in.dat(7 downto 0),
 821                 wb_dat_out => uart0_dat8,
 822                 wb_cyc_in => wb_uart0_in.cyc,
 823                 wb_stb_in => wb_uart0_in.stb,
 824                 wb_we_in => wb_uart0_in.we,
 825                 wb_ack_out => wb_uart0_out.ack
 826                 );
 827     end generate;
 828
 829     uart0_16550 : if UART0_IS_16550 generate
 830         signal irq_l : std_ulogic;
 831     begin
 832         uart0: uart_top
 833             port map (
 834                 wb_clk_i   => system_clk,
 835                 wb_rst_i   => rst_uart,
 836                 wb_adr_i   => wb_uart0_in.adr(2 downto 0),
 837                 wb_dat_i   => wb_uart0_in.dat(7 downto 0),
 838                 wb_dat_o   => uart0_dat8,
 839                 wb_we_i    => wb_uart0_in.we,
 840                 wb_stb_i   => wb_uart0_in.stb,
 841                 wb_cyc_i   => wb_uart0_in.cyc,
 842                 wb_ack_o   => wb_uart0_out.ack,
 843                 int_o      => irq_l,
 844                 stx_pad_o  => uart0_txd,
 845                 srx_pad_i  => uart0_rxd,
 846                 rts_pad_o  => open,
 847                 cts_pad_i  => '1',
 848                 dtr_pad_o  => open,
 849                 dsr_pad_i  => '1',
 850                 ri_pad_i   => '0',
 851                 dcd_pad_i  => '1'
 852                 );
 853
 854         -- Add a register on the irq out, helps timing
 855         uart0_irq_latch: process(system_clk)
 856         begin
 857             if rising_edge(system_clk) then
 858                 uart0_irq <= irq_l;
 859             end if;
 860         end process;
 861     end generate;
 862
 863     wb_uart0_out.dat <= x"000000" & uart0_dat8;
 864     wb_uart0_out.stall <= not wb_uart0_out.ack;
 865
 866     --
 867     -- UART1
 868     --
 869     -- Always 16550 if it exists
 870     --
 871     uart1_16550: if HAS_UART1 generate
 872         signal irq_l : std_ulogic;
 873     begin
 874         uart1: uart_top
 875             port map (
 876                 wb_clk_i   => system_clk,
 877                 wb_rst_i   => rst_uart,
 878                 wb_adr_i   => wb_uart1_in.adr(2 downto 0),
 879                 wb_dat_i   => wb_uart1_in.dat(7 downto 0),
 880                 wb_dat_o   => uart1_dat8,
 881                 wb_we_i    => wb_uart1_in.we,
 882                 wb_stb_i   => wb_uart1_in.stb,
 883                 wb_cyc_i   => wb_uart1_in.cyc,
 884                 wb_ack_o   => wb_uart1_out.ack,
 885                 int_o      => irq_l,
 886                 stx_pad_o  => uart1_txd,
 887                 srx_pad_i  => uart1_rxd,
 888                 rts_pad_o  => open,
 889                 cts_pad_i  => '1',
 890                 dtr_pad_o  => open,
 891                 dsr_pad_i  => '1',
 892                 ri_pad_i   => '0',
 893                 dcd_pad_i  => '1'
 894                 );
 895         -- Add a register on the irq out, helps timing
 896         uart0_irq_latch: process(system_clk)
 897         begin
 898             if rising_edge(system_clk) then
 899                 uart1_irq <= irq_l;
 900             end if;
 901         end process;
 902         wb_uart1_out.dat <= x"000000" & uart1_dat8;
 903         wb_uart1_out.stall <= not wb_uart1_out.ack;
 904     end generate;
 905
 906     no_uart1 : if not HAS_UART1 generate
 907         wb_uart1_out.dat <= x"00000000";
 908         wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
 909         wb_uart1_out.stall <= '0';
 910         uart1_irq <= '0';
 911     end generate;
 912
 913     spiflash_gen: if HAS_SPI_FLASH generate
 914         spiflash: entity work.spi_flash_ctrl
 915             generic map (
 916                 DATA_LINES    => SPI_FLASH_DLINES,
 917                 DEF_CLK_DIV   => SPI_FLASH_DEF_CKDV,
 918                 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD,
 919                 BOOT_CLOCKS   => SPI_BOOT_CLOCKS
 920                 )
 921             port map(
 922                 rst => rst_spi,
 923                 clk => system_clk,
 924                 wb_in => wb_spiflash_in,
 925                 wb_out => wb_spiflash_out,
 926                 wb_sel_reg => wb_spiflash_is_reg,
 927                 wb_sel_map => wb_spiflash_is_map,
 928                 sck => spi_flash_sck,
 929                 cs_n => spi_flash_cs_n,
 930                 sdat_o => spi_flash_sdat_o,
 931                 sdat_oe => spi_flash_sdat_oe,
 932                 sdat_i => spi_flash_sdat_i
 933                 );
 934     end generate;
 935
 936     no_spi0_gen: if not HAS_SPI_FLASH generate
 937         wb_spiflash_out.dat   <= (others => '1');
 938         wb_spiflash_out.ack   <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
 939         wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
 940     end generate;
 941
 942     xics_icp: entity work.xics_icp
 943         port map(
 944             clk => system_clk,
 945             rst => rst_xics,
 946             wb_in => wb_xics_icp_in,
 947             wb_out => wb_xics_icp_out,
 948             ics_in => ics_to_icp,
 949             core_irq_out => core_ext_irq
 950             );
 951
 952     xics_ics: entity work.xics_ics
 953         generic map(
 954             SRC_NUM   => 16,
 955             PRIO_BITS => 3
 956             )
 957         port map(
 958             clk => system_clk,
 959             rst => rst_xics,
 960             wb_in => wb_xics_ics_in,
 961             wb_out => wb_xics_ics_out,
 962             int_level_in => int_level_in,
 963             icp_out => ics_to_icp
 964             );
 965
 966     gpio0_gen: if HAS_GPIO generate
 967         gpio : entity work.gpio
 968             generic map(
 969                 NGPIO => NGPIO
 970                 )
 971             port map(
 972                 clk      => system_clk,
 973                 rst      => rst_gpio,
 974                 wb_in    => wb_gpio_in,
 975                 wb_out   => wb_gpio_out,
 976                 gpio_in  => gpio_in,
 977                 gpio_out => gpio_out,
 978                 gpio_dir => gpio_dir,
 979                 intr     => gpio_intr
 980                 );
 981     end generate;
 982
 983     -- Assign external interrupts
 984     interrupts: process(all)
 985     begin
 986         int_level_in <= (others => '0');
 987         int_level_in(0) <= uart0_irq;
 988         int_level_in(1) <= ext_irq_eth;
 989         int_level_in(2) <= uart1_irq;
 990         int_level_in(3) <= ext_irq_sdcard;
 991         int_level_in(4) <= gpio_intr;
 992     end process;
 993
 994     -- BRAM Memory slave
 995     bram: if MEMORY_SIZE /= 0 generate
 996         bram0: entity work.wishbone_bram_wrapper
 997             generic map(
 998                 MEMORY_SIZE   => MEMORY_SIZE,
 999                 RAM_INIT_FILE => RAM_INIT_FILE
1000                 )
1001             port map(
1002                 clk => system_clk,
1003                 rst => rst_bram,
1004                 wishbone_in => wb_bram_in,
1005                 wishbone_out => wb_bram_out
1006                 );
1007     end generate;
1008
1009     no_bram: if MEMORY_SIZE = 0 generate
1010         wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
1011         wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
1012         wb_bram_out.stall <= not wb_bram_out.ack;
1013     end generate;
1014
1015     -- DMI(debug bus) <-> JTAG bridge
1016     dtm: entity work.dmi_dtm
1017         generic map(
1018             ABITS => 8,
1019             DBITS => 64
1020             )
1021         port map(
1022             sys_clk     => system_clk,
1023             sys_reset   => rst_dtm,
1024             dmi_addr    => dmi_addr,
1025             dmi_din     => dmi_din,
1026             dmi_dout    => dmi_dout,
1027             dmi_req     => dmi_req,
1028             dmi_wr      => dmi_wr,
1029             dmi_ack     => dmi_ack
1030             );
1031
1032     -- DMI interconnect
1033     dmi_intercon: process(dmi_addr, dmi_req,
1034                           dmi_wb_ack, dmi_wb_dout,
1035                           dmi_core_ack, dmi_core_dout)
1036
1037         -- DMI address map (each address is a full 64-bit register)
1038         --
1039         -- Offset:   Size:    Slave:
1040         --  0         4       Wishbone
1041         -- 10        16       Core
1042
1043         type slave_type is (SLAVE_WB,
1044                             SLAVE_CORE,
1045                             SLAVE_NONE);
1046         variable slave : slave_type;
1047     begin
1048         -- Simple address decoder
1049         slave := SLAVE_NONE;
1050         if std_match(dmi_addr, "000000--") then
1051             slave := SLAVE_WB;
1052         elsif std_match(dmi_addr, "0001----") then
1053             slave := SLAVE_CORE;
1054         end if;
1055
1056         -- DMI muxing
1057         dmi_wb_req <= '0';
1058         dmi_core_req <= '0';
1059         case slave is
1060         when SLAVE_WB =>
1061             dmi_wb_req <= dmi_req;
1062             dmi_ack <= dmi_wb_ack;
1063             dmi_din <= dmi_wb_dout;
1064         when SLAVE_CORE =>
1065             dmi_core_req <= dmi_req;
1066             dmi_ack <= dmi_core_ack;
1067             dmi_din <= dmi_core_dout;
1068         when others =>
1069             dmi_ack <= dmi_req;
1070             dmi_din <= (others => '1');
1071         end case;
1072
1073         -- SIM magic exit
1074         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
1075             stop;
1076         end if;
1077     end process;
1078
1079     -- Wishbone debug master (TODO: Add a DMI address decoder)
1080     wishbone_debug: entity work.wishbone_debug_master
1081         port map(clk => system_clk,
1082                  rst => rst_wbdb,
1083                  dmi_addr => dmi_addr(1 downto 0),
1084                  dmi_dout => dmi_wb_dout,
1085                  dmi_din => dmi_dout,
1086                  dmi_wr => dmi_wr,
1087                  dmi_ack => dmi_wb_ack,
1088                  dmi_req => dmi_wb_req,
1089                  wb_in => wishbone_debug_in,
1090                  wb_out => wishbone_debug_out);
1091
1092 --pragma synthesis_off
1093     wb_x_state: process(system_clk)
1094     begin
1095         if rising_edge(system_clk) then
1096             if not soc_reset then
1097                 -- Wishbone arbiter
1098                 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
1099                 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
1100                 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
1101                 assert not(is_x(wb_masters_in(0).ack)) severity failure;
1102                 assert not(is_x(wb_masters_in(1).ack)) severity failure;
1103                 assert not(is_x(wb_masters_in(2).ack)) severity failure;
1104
1105                 -- Main memory wishbones
1106                 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
1107                 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
1108                 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
1109                 assert not(is_x(wb_bram_out.ack)) severity failure;
1110                 assert not(is_x(wb_dram_out.ack)) severity failure;
1111                 assert not(is_x(wb_io_out.ack)) severity failure;
1112
1113                 -- I/O wishbones
1114                 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
1115                 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
1116                 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
1117                 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
1118                 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
1119                 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
1120                 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
1121                 assert not(is_x(wb_uart0_out.ack)) severity failure;
1122                 assert not(is_x(wb_uart1_out.ack)) severity failure;
1123                 assert not(is_x(wb_spiflash_out.ack)) severity failure;
1124                 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
1125                 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
1126                 assert not(is_x(wb_ext_io_out.ack)) severity failure;
1127                 assert not(is_x(wb_syscon_out.ack)) severity failure;
1128             end if;
1129         end if;
1130     end process;
1131 --pragma synthesis_on
1132
1133 end architecture behaviour;