soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
  14 --
  15 -- Main bus:
  16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
  17 -- 0x40000000: DRAM (when present)
  18 -- 0x80000000: Block RAM (aliased & repeated)
  19
  20 -- IO Bus:
  21 -- 0xc0000000: SYSCON
  22 -- 0xc0002000: UART0
  23 -- 0xc0003000: UART1 (if any)
  24 -- 0xc0004000: XICS ICP
  25 -- 0xc0005000: XICS ICS
  26 -- 0xc0006000: SPI Flash controller
  27 -- 0xc0007000: GPIO controller
  28 -- 0xc0008000: USB UART (valentyusb)
  29 -- 0xc8nnnnnn: External IO bus
  30 -- 0xf0000000: Flash "ROM" mapping
  31 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
  32
  33 -- External IO bus:
  34 -- 0xc8000000: LiteDRAM control (CSRs)
  35 -- 0xc8020000: LiteEth CSRs (*)
  36 -- 0xc8030000: LiteEth MMIO (*)
  37 -- 0xc8040000: LiteSDCard CSRs
  38
  39 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
  40 --     are actually decoded as a single wishbone which LiteEth will
  41 --     internally split based on bit 16.
  42
  43 -- (**) DRAM init code is currently special and goes to the external
  44 --      IO bus, this will be fixed when it's moved out of litedram and
  45 --      into the main SoC once we have a common "firmware".
  46
  47 -- Interrupt numbers:
  48 --
  49 --   0  : UART0
  50 --   1  : Ethernet
  51 --   2  : UART1
  52 --   3  : SD card
  53 --   4  : GPIO
  54 --   5  : UARTUSB
  55
  56 entity soc is
  57     generic (
  58         MEMORY_SIZE        : natural;
  59         RAM_INIT_FILE      : string;
  60         CLK_FREQ           : positive;
  61         SIM                : boolean;
  62         HAS_FPU            : boolean := true;
  63         HAS_BTC            : boolean := true;
  64         HAS_SHORT_MULT     : boolean := false;
  65         DISABLE_FLATTEN_CORE : boolean := false;
  66         ALT_RESET_ADDRESS  : std_logic_vector(63 downto 0) := (23 downto 0 => '0', others => '1');
  67         HAS_DRAM           : boolean  := false;
  68         DRAM_SIZE          : integer := 0;
  69         DRAM_INIT_SIZE     : integer := 0;
  70         HAS_SPI_FLASH      : boolean := false;
  71         SPI_FLASH_DLINES   : positive := 1;
  72         SPI_FLASH_OFFSET   : integer := 0;
  73         SPI_FLASH_DEF_CKDV : natural := 2;
  74         SPI_FLASH_DEF_QUAD : boolean := false;
  75         SPI_BOOT_CLOCKS    : boolean := true;
  76         LOG_LENGTH         : natural := 512;
  77         HAS_LITEETH        : boolean := false;
  78         UART0_IS_16550     : boolean := true;
  79         HAS_UART1          : boolean := false;
  80         HAS_UARTUSB        : boolean := false;
  81         ICACHE_NUM_LINES   : natural := 64;
  82         ICACHE_NUM_WAYS    : natural := 2;
  83         ICACHE_TLB_SIZE    : natural := 64;
  84         DCACHE_NUM_LINES   : natural := 64;
  85         DCACHE_NUM_WAYS    : natural := 2;
  86         DCACHE_TLB_SET_SIZE : natural := 64;
  87         DCACHE_TLB_NUM_WAYS : natural := 2;
  88         HAS_SD_CARD        : boolean := false;
  89         HAS_GPIO           : boolean := false;
  90         NGPIO              : natural := 32
  91         );
  92     port(
  93         rst          : in  std_ulogic;
  94         system_clk   : in  std_ulogic;
  95         clk_48       : in  std_ulogic := '0';
  96
  97         -- "Large" (64-bit) DRAM wishbone
  98         wb_dram_in       : out wishbone_master_out;
  99         wb_dram_out      : in wishbone_slave_out := wishbone_slave_out_init;
 100
 101         -- "Small" (32-bit) external IO wishbone
 102         wb_ext_io_in         : out wb_io_master_out;
 103         wb_ext_io_out        : in wb_io_slave_out := wb_io_slave_out_init;
 104         wb_ext_is_dram_csr   : out std_ulogic;
 105         wb_ext_is_dram_init  : out std_ulogic;
 106         wb_ext_is_eth        : out std_ulogic;
 107         wb_ext_is_sdcard     : out std_ulogic;
 108
 109         -- external DMA wishbone with 32-bit data/address
 110         wishbone_dma_in      : out wb_io_slave_out := wb_io_slave_out_init;
 111         wishbone_dma_out     : in wb_io_master_out := wb_io_master_out_init;
 112
 113         -- External interrupts
 114         ext_irq_eth          : in std_ulogic := '0';
 115         ext_irq_sdcard       : in std_ulogic := '0';
 116
 117         -- UART0 signals:
 118         uart0_txd    : out std_ulogic;
 119         uart0_rxd    : in  std_ulogic := '0';
 120
 121         -- UART1 signals:
 122         uart1_txd    : out std_ulogic;
 123         uart1_rxd    : in  std_ulogic := '0';
 124
 125         -- USB signals:
 126         usb_d_p    : in std_ulogic := '0';
 127         usb_d_n    : in std_ulogic := '0';
 128         usb_pullup : out std_ulogic;
 129
 130         -- SPI Flash signals
 131         spi_flash_sck     : out std_ulogic;
 132         spi_flash_cs_n    : out std_ulogic;
 133         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 134         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 135         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
 136
 137         -- GPIO signals
 138         gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);
 139         gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);
 140         gpio_in  : in  std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
 141
 142         -- DRAM controller signals
 143         alt_reset    : in std_ulogic := '0'
 144         );
 145 end entity soc;
 146
 147 architecture behaviour of soc is
 148
 149     -- Wishbone master signals:
 150     signal wishbone_dcore_in  : wishbone_slave_out;
 151     signal wishbone_dcore_out : wishbone_master_out;
 152     signal wishbone_icore_in  : wishbone_slave_out;
 153     signal wishbone_icore_out : wishbone_master_out;
 154     signal wishbone_debug_in  : wishbone_slave_out;
 155     signal wishbone_debug_out : wishbone_master_out;
 156
 157     -- Arbiter array (ghdl doesnt' support assigning the array
 158     -- elements in the entity instantiation)
 159     constant NUM_WB_MASTERS : positive := 4;
 160     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
 161     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
 162
 163     -- Wishbone master (output of arbiter):
 164     signal wb_master_in       : wishbone_slave_out;
 165     signal wb_master_out      : wishbone_master_out;
 166     signal wb_snoop           : wishbone_master_out;
 167
 168     -- Main "IO" bus, from main slave decoder to the latch
 169     signal wb_io_in     : wishbone_master_out;
 170     signal wb_io_out    : wishbone_slave_out;
 171
 172     -- Secondary (smaller) IO bus after the IO bus latch
 173     signal wb_sio_out    : wb_io_master_out;
 174     signal wb_sio_in     : wb_io_slave_out;
 175
 176     -- Syscon signals
 177     signal dram_at_0     : std_ulogic;
 178     signal do_core_reset    : std_ulogic;
 179     signal wb_syscon_in  : wb_io_master_out;
 180     signal wb_syscon_out : wb_io_slave_out;
 181
 182     -- UART0 signals:
 183     signal wb_uart0_in   : wb_io_master_out;
 184     signal wb_uart0_out  : wb_io_slave_out;
 185     signal uart0_dat8    : std_ulogic_vector(7 downto 0);
 186     signal uart0_irq     : std_ulogic;
 187
 188     -- UART1 signals:
 189     signal wb_uart1_in   : wb_io_master_out;
 190     signal wb_uart1_out  : wb_io_slave_out;
 191     signal uart1_dat8    : std_ulogic_vector(7 downto 0);
 192     signal uart1_irq     : std_ulogic;
 193
 194     -- UARTUSB signals:
 195     signal wb_uartusb_in   : wb_io_master_out;
 196     signal wb_uartusb_out  : wb_io_slave_out;
 197     signal uartusb_irq     : std_ulogic;
 198
 199     -- SPI Flash controller signals:
 200     signal wb_spiflash_in     : wb_io_master_out;
 201     signal wb_spiflash_out    : wb_io_slave_out;
 202     signal wb_spiflash_is_reg : std_ulogic;
 203     signal wb_spiflash_is_map : std_ulogic;
 204
 205     -- XICS signals:
 206     signal wb_xics_icp_in   : wb_io_master_out;
 207     signal wb_xics_icp_out  : wb_io_slave_out;
 208     signal wb_xics_ics_in   : wb_io_master_out;
 209     signal wb_xics_ics_out  : wb_io_slave_out;
 210     signal int_level_in     : std_ulogic_vector(15 downto 0);
 211     signal ics_to_icp       : ics_to_icp_t;
 212     signal core_ext_irq     : std_ulogic;
 213
 214     -- GPIO signals:
 215     signal wb_gpio_in    : wb_io_master_out;
 216     signal wb_gpio_out   : wb_io_slave_out;
 217     signal gpio_intr     : std_ulogic := '0';
 218
 219     -- Main memory signals:
 220     signal wb_bram_in     : wishbone_master_out;
 221     signal wb_bram_out    : wishbone_slave_out;
 222
 223     -- DMI debug bus signals
 224     signal dmi_addr     : std_ulogic_vector(7 downto 0);
 225     signal dmi_din      : std_ulogic_vector(63 downto 0);
 226     signal dmi_dout     : std_ulogic_vector(63 downto 0);
 227     signal dmi_req      : std_ulogic;
 228     signal dmi_wr       : std_ulogic;
 229     signal dmi_ack      : std_ulogic;
 230
 231     -- Per slave DMI signals
 232     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
 233     signal dmi_wb_req   : std_ulogic;
 234     signal dmi_wb_ack   : std_ulogic;
 235     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
 236     signal dmi_core_req   : std_ulogic;
 237     signal dmi_core_ack   : std_ulogic;
 238
 239     -- Delayed/latched resets and alt_reset
 240     signal rst_core    : std_ulogic := '1';
 241     signal rst_uart    : std_ulogic := '1';
 242     signal rst_xics    : std_ulogic := '1';
 243     signal rst_spi     : std_ulogic := '1';
 244     signal rst_gpio    : std_ulogic := '1';
 245     signal rst_bram    : std_ulogic := '1';
 246     signal rst_dtm     : std_ulogic := '1';
 247     signal rst_wbar    : std_ulogic := '1';
 248     signal rst_wbdb    : std_ulogic := '1';
 249     signal alt_reset_d : std_ulogic;
 250
 251     -- IO branch split:
 252     type slave_io_type is (SLAVE_IO_SYSCON,
 253                            SLAVE_IO_UART,
 254                            SLAVE_IO_ICP,
 255                            SLAVE_IO_ICS,
 256                            SLAVE_IO_UART1,
 257                            SLAVE_IO_SPI_FLASH,
 258                            SLAVE_IO_GPIO,
 259                            SLAVE_IO_UARTUSB,
 260                            SLAVE_IO_EXTERNAL);
 261     signal current_io_decode : slave_io_type;
 262
 263     signal io_cycle_none      : std_ulogic;
 264     signal io_cycle_syscon    : std_ulogic;
 265     signal io_cycle_uart      : std_ulogic;
 266     signal io_cycle_uart1     : std_ulogic;
 267     signal io_cycle_uartusb   : std_ulogic;
 268     signal io_cycle_icp       : std_ulogic;
 269     signal io_cycle_ics       : std_ulogic;
 270     signal io_cycle_spi_flash : std_ulogic;
 271     signal io_cycle_gpio      : std_ulogic;
 272     signal io_cycle_external  : std_ulogic;
 273
 274     function wishbone_widen_data(wb : wb_io_master_out) return wishbone_master_out is
 275         variable wwb : wishbone_master_out;
 276     begin
 277         wwb.adr := wb.adr(wb.adr'left downto 1);
 278         wwb.dat := wb.dat & wb.dat;
 279         wwb.sel := x"00";
 280         if wb.adr(0) = '0' then
 281             wwb.sel(3 downto 0) := wb.sel;
 282         else
 283             wwb.sel(7 downto 4) := wb.sel;
 284         end if;
 285         wwb.cyc := wb.cyc;
 286         wwb.stb := wb.stb;
 287         wwb.we := wb.we;
 288         return wwb;
 289     end;
 290
 291     function wishbone_narrow_data(wwbs : wishbone_slave_out; adr : std_ulogic_vector(29 downto 0))
 292         return wb_io_slave_out is
 293         variable wbs : wb_io_slave_out;
 294     begin
 295         wbs.ack := wwbs.ack;
 296         wbs.stall := wwbs.stall;
 297         if adr(0) = '0' then
 298             wbs.dat := wwbs.dat(31 downto 0);
 299         else
 300             wbs.dat := wwbs.dat(63 downto 32);
 301         end if;
 302         return wbs;
 303     end;
 304
 305     -- This is the component exported by the 16550 compatible
 306     -- UART from FuseSoC.
 307     --
 308     component uart_top port (
 309         wb_clk_i    : in std_ulogic;
 310         wb_rst_i    : in std_ulogic;
 311         wb_adr_i    : in std_ulogic_vector(2 downto 0);
 312         wb_dat_i    : in std_ulogic_vector(7 downto 0);
 313         wb_dat_o    : out std_ulogic_vector(7 downto 0);
 314         wb_we_i     : in std_ulogic;
 315         wb_stb_i    : in std_ulogic;
 316         wb_cyc_i    : in std_ulogic;
 317         wb_ack_o    : out std_ulogic;
 318         int_o       : out std_ulogic;
 319         stx_pad_o   : out std_ulogic;
 320         srx_pad_i   : in std_ulogic;
 321         rts_pad_o   : out std_ulogic;
 322         cts_pad_i   : in std_ulogic;
 323         dtr_pad_o   : out std_ulogic;
 324         dsr_pad_i   : in std_ulogic;
 325         ri_pad_i    : in std_ulogic;
 326         dcd_pad_i   : in std_ulogic
 327         );
 328     end component;
 329
 330     constant UART0_IS_POTATO : boolean := not UART0_IS_16550;
 331 begin
 332
 333     resets: process(system_clk)
 334     begin
 335         if rising_edge(system_clk) then
 336             rst_core    <= rst or do_core_reset;
 337             rst_uart    <= rst;
 338             rst_spi     <= rst;
 339             rst_xics    <= rst;
 340             rst_gpio    <= rst;
 341             rst_bram    <= rst;
 342             rst_dtm     <= rst;
 343             rst_wbar    <= rst;
 344             rst_wbdb    <= rst;
 345             alt_reset_d <= alt_reset;
 346         end if;
 347     end process;
 348
 349     -- Processor core
 350     processor: entity work.core
 351         generic map(
 352             SIM => SIM,
 353             HAS_FPU => HAS_FPU,
 354             HAS_BTC => HAS_BTC,
 355             HAS_SHORT_MULT => HAS_SHORT_MULT,
 356             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 357             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 358             LOG_LENGTH => LOG_LENGTH,
 359             ICACHE_NUM_LINES => ICACHE_NUM_LINES,
 360             ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
 361             ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
 362             DCACHE_NUM_LINES => DCACHE_NUM_LINES,
 363             DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
 364             DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
 365             DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
 366             )
 367         port map(
 368             clk => system_clk,
 369             rst => rst_core,
 370             alt_reset => alt_reset_d,
 371             wishbone_insn_in => wishbone_icore_in,
 372             wishbone_insn_out => wishbone_icore_out,
 373             wishbone_data_in => wishbone_dcore_in,
 374             wishbone_data_out => wishbone_dcore_out,
 375             wb_snoop_in => wb_snoop,
 376             dmi_addr => dmi_addr(3 downto 0),
 377             dmi_dout => dmi_core_dout,
 378             dmi_din => dmi_dout,
 379             dmi_wr => dmi_wr,
 380             dmi_ack => dmi_core_ack,
 381             dmi_req => dmi_core_req,
 382             ext_irq => core_ext_irq
 383             );
 384
 385     -- Wishbone bus master arbiter & mux
 386     wb_masters_out <= (0 => wishbone_dcore_out,
 387                        1 => wishbone_icore_out,
 388                        2 => wishbone_widen_data(wishbone_dma_out),
 389                        3 => wishbone_debug_out);
 390     wishbone_dcore_in <= wb_masters_in(0);
 391     wishbone_icore_in <= wb_masters_in(1);
 392     wishbone_dma_in   <= wishbone_narrow_data(wb_masters_in(2), wishbone_dma_out.adr);
 393     wishbone_debug_in <= wb_masters_in(3);
 394     wishbone_arbiter_0: entity work.wishbone_arbiter
 395         generic map(
 396             NUM_MASTERS => NUM_WB_MASTERS
 397             )
 398         port map(
 399             clk => system_clk,
 400             rst => rst_wbar,
 401             wb_masters_in => wb_masters_out,
 402             wb_masters_out => wb_masters_in,
 403             wb_slave_out => wb_master_out,
 404             wb_slave_in => wb_master_in
 405             );
 406
 407     -- Snoop bus going to caches.
 408     -- Gate stb with stall so the caches don't see the stalled strobes.
 409     -- That way if the caches see a strobe when their wishbone is stalled,
 410     -- they know it is an access by another master.
 411     process(all)
 412     begin
 413         wb_snoop <= wb_master_out;
 414         if wb_master_in.stall = '1' then
 415             wb_snoop.stb <= '0';
 416         end if;
 417     end process;
 418
 419     -- Top level Wishbone slaves address decoder & mux
 420     --
 421     -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
 422     -- 0000  - BRAM
 423     -- 0001  - DRAM
 424     -- 01xx  - DRAM
 425     -- 10xx  - BRAM
 426     -- 11xx  - IO
 427     --
 428     slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
 429         type slave_top_type is (SLAVE_TOP_BRAM,
 430                                 SLAVE_TOP_DRAM,
 431                                 SLAVE_TOP_IO);
 432         variable slave_top : slave_top_type;
 433         variable top_decode : std_ulogic_vector(3 downto 0);
 434     begin
 435         -- Top-level address decoder
 436         top_decode := wb_master_out.adr(28 downto 26) & dram_at_0;
 437         slave_top := SLAVE_TOP_BRAM;
 438         if    std_match(top_decode, "0000") then
 439             slave_top := SLAVE_TOP_BRAM;
 440         elsif std_match(top_decode, "0001") then
 441             slave_top := SLAVE_TOP_DRAM;
 442         elsif std_match(top_decode, "01--") then
 443             slave_top := SLAVE_TOP_DRAM;
 444         elsif std_match(top_decode, "10--") then
 445             slave_top := SLAVE_TOP_BRAM;
 446         elsif std_match(top_decode, "11--") then
 447             slave_top := SLAVE_TOP_IO;
 448         end if;
 449
 450         -- Top level wishbone muxing.
 451         wb_bram_in <= wb_master_out;
 452         wb_bram_in.cyc  <= '0';
 453         wb_dram_in <= wb_master_out;
 454         wb_dram_in.cyc  <= '0';
 455         wb_io_in <= wb_master_out;
 456         wb_io_in.cyc  <= '0';
 457         case slave_top is
 458         when SLAVE_TOP_BRAM =>
 459             wb_bram_in.cyc <= wb_master_out.cyc;
 460             wb_master_in <= wb_bram_out;
 461         when SLAVE_TOP_DRAM =>
 462             if HAS_DRAM then
 463                 wb_dram_in.cyc <= wb_master_out.cyc;
 464                 wb_master_in <= wb_dram_out;
 465             else
 466                 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
 467                 wb_master_in.dat <= (others => '1');
 468                 wb_master_in.stall <= '0';
 469             end if;
 470         when SLAVE_TOP_IO =>
 471             wb_io_in.cyc <= wb_master_out.cyc;
 472             wb_master_in <= wb_io_out;
 473         end case;
 474
 475     end process slave_top_intercon;
 476
 477     -- IO wishbone slave 64->32 bits converter
 478     --
 479     -- For timing reasons, this adds a one cycle latch on the way both
 480     -- in and out. This relaxes timing and routing pressure on the "main"
 481     -- memory bus by moving all simple IOs to a slower 32-bit bus.
 482     --
 483     -- This implementation is rather dumb at the moment, no stash buffer,
 484     -- so we stall whenever that latch is busy. This can be improved.
 485     --
 486     slave_io_latch: process(system_clk)
 487         -- State
 488         type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
 489         variable state : state_t;
 490
 491         -- Misc
 492         variable has_top : boolean;
 493         variable has_bot : boolean;
 494         variable do_cyc  : std_ulogic;
 495         variable end_cyc : std_ulogic;
 496         variable slave_io : slave_io_type;
 497         variable match   : std_ulogic_vector(31 downto 12);
 498     begin
 499         if rising_edge(system_clk) then
 500             do_cyc := '0';
 501             end_cyc := '0';
 502             if (rst) then
 503                 state := IDLE;
 504                 wb_io_out.ack <= '0';
 505                 wb_io_out.stall <= '0';
 506                 wb_sio_out.stb <= '0';
 507                 end_cyc := '1';
 508                 has_top := false;
 509                 has_bot := false;
 510             else
 511                 case state is
 512                 when IDLE =>
 513                     -- Clear ACK in case it was set
 514                     wb_io_out.ack <= '0';
 515
 516                     -- Do we have a cycle ?
 517                     if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
 518                         -- Stall master until we are done, we are't (yet) pipelining
 519                         -- this, it's all slow IOs.
 520                         wb_io_out.stall <= '1';
 521
 522                         -- Start cycle downstream
 523                         do_cyc := '1';
 524                         wb_sio_out.stb <= '1';
 525
 526                         -- Copy write enable to IO out, copy address as well
 527                         wb_sio_out.we <= wb_io_in.we;
 528                         wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left - 1 downto 0) & '0';
 529
 530                         -- Do we have a top word and/or a bottom word ?
 531                         has_top := wb_io_in.sel(7 downto 4) /= "0000";
 532                         has_bot := wb_io_in.sel(3 downto 0) /= "0000";
 533
 534                         -- If we have a bottom word, handle it first, otherwise
 535                         -- send the top word down. XXX Split the actual mux out
 536                         -- and only generate a control signal.
 537                         if has_bot then
 538                             if wb_io_in.we = '1' then
 539                                 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
 540                             end if;
 541                             wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
 542
 543                             -- Wait for ack
 544                             state := WAIT_ACK_BOT;
 545                         else
 546                             if wb_io_in.we = '1' then
 547                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 548                             end if;
 549                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 550
 551                             -- Bump address
 552                             wb_sio_out.adr(0) <= '1';
 553
 554                             -- Wait for ack
 555                             state := WAIT_ACK_TOP;
 556                         end if;
 557                     end if;
 558                 when WAIT_ACK_BOT =>
 559                     -- If we aren't stalled by the device, clear stb
 560                     if wb_sio_in.stall = '0' then
 561                         wb_sio_out.stb <= '0';
 562                     end if;
 563
 564                     -- Handle ack
 565                     if wb_sio_in.ack = '1' then
 566                         -- If it's a read, latch the data
 567                         if wb_sio_out.we = '0' then
 568                             wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
 569                         end if;
 570
 571                         -- Do we have a "top" part as well ?
 572                         if has_top then
 573                             -- Latch data & sel
 574                             if wb_io_in.we = '1' then
 575                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 576                             end if;
 577                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 578
 579                             -- Bump address and set STB
 580                             wb_sio_out.adr(0) <= '1';
 581                             wb_sio_out.stb <= '1';
 582
 583                             -- Wait for new ack
 584                             state := WAIT_ACK_TOP;
 585                         else
 586                             -- We are done, ack up, clear cyc downstream
 587                             end_cyc := '1';
 588
 589                             -- And ack & unstall upstream
 590                             wb_io_out.ack <= '1';
 591                             wb_io_out.stall <= '0';
 592
 593                             -- Wait for next one
 594                             state := IDLE;
 595                         end if;
 596                     end if;
 597                 when WAIT_ACK_TOP =>
 598                     -- If we aren't stalled by the device, clear stb
 599                     if wb_sio_in.stall = '0' then
 600                         wb_sio_out.stb <= '0';
 601                     end if;
 602
 603                     -- Handle ack
 604                     if wb_sio_in.ack = '1' then
 605                         -- If it's a read, latch the data
 606                         if wb_sio_out.we = '0' then
 607                             wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
 608                         end if;
 609
 610                         -- We are done, ack up, clear cyc downstram
 611                         end_cyc := '1';
 612
 613                         -- And ack & unstall upstream
 614                         wb_io_out.ack <= '1';
 615                         wb_io_out.stall <= '0';
 616
 617                         -- Wait for next one
 618                         state := IDLE;
 619                     end if;
 620                 end case;
 621             end if;
 622
 623             -- Create individual registered cycle signals for the wishbones
 624             -- going to the various peripherals
 625             if do_cyc = '1' or end_cyc = '1' then
 626                 io_cycle_none      <= '0';
 627                 io_cycle_syscon    <= '0';
 628                 io_cycle_uart      <= '0';
 629                 io_cycle_uart1     <= '0';
 630                 io_cycle_uartusb   <= '0';
 631                 io_cycle_icp       <= '0';
 632                 io_cycle_ics       <= '0';
 633                 io_cycle_spi_flash <= '0';
 634                 io_cycle_gpio      <= '0';
 635                 io_cycle_external  <= '0';
 636                 wb_sio_out.cyc     <= '0';
 637                 wb_ext_is_dram_init <= '0';
 638                 wb_spiflash_is_map <= '0';
 639                 wb_spiflash_is_reg <= '0';
 640                 wb_ext_is_dram_csr <= '0';
 641                 wb_ext_is_eth      <= '0';
 642                 wb_ext_is_sdcard   <= '0';
 643             end if;
 644             if do_cyc = '1' then
 645                 -- Decode I/O address
 646                 -- This is real address bits 29 downto 12
 647                 match := "11" & wb_io_in.adr(26 downto 9);
 648                 slave_io := SLAVE_IO_SYSCON;
 649                 if    std_match(match, x"FF---") and HAS_DRAM then
 650                     slave_io := SLAVE_IO_EXTERNAL;
 651                     io_cycle_external <= '1';
 652                     wb_ext_is_dram_init <= '1';
 653                 elsif std_match(match, x"F----") then
 654                     slave_io := SLAVE_IO_SPI_FLASH;
 655                     io_cycle_spi_flash <= '1';
 656                     wb_spiflash_is_map <= '1';
 657                 elsif std_match(match, x"C8---") then
 658                     -- Ext IO "chip selects"
 659                     if    std_match(match, x"--00-") and HAS_DRAM then
 660                         slave_io := SLAVE_IO_EXTERNAL;
 661                         io_cycle_external <= '1';
 662                         wb_ext_is_dram_csr <= '1';
 663                     elsif (std_match(match, x"--02-") or std_match(match, x"--03-")) and
 664                            HAS_LITEETH then
 665                         slave_io := SLAVE_IO_EXTERNAL;
 666                         io_cycle_external <= '1';
 667                         wb_ext_is_eth <= '1';
 668                     elsif std_match(match, x"--04-") and HAS_SD_CARD then
 669                         slave_io := SLAVE_IO_EXTERNAL;
 670                         io_cycle_external <= '1';
 671                         wb_ext_is_sdcard <= '1';
 672                     else
 673                         io_cycle_none <= '1';
 674                     end if;
 675                 elsif std_match(match, x"C0000") then
 676                     slave_io := SLAVE_IO_SYSCON;
 677                     io_cycle_syscon <= '1';
 678                 elsif std_match(match, x"C0002") then
 679                     slave_io := SLAVE_IO_UART;
 680                     io_cycle_uart <= '1';
 681                 elsif std_match(match, x"C0003") then
 682                     slave_io := SLAVE_IO_UART1;
 683                     io_cycle_uart1 <= '1';
 684                 elsif std_match(match, x"C0004") then
 685                     slave_io := SLAVE_IO_ICP;
 686                     io_cycle_icp <= '1';
 687                 elsif std_match(match, x"C0005") then
 688                     slave_io := SLAVE_IO_ICS;
 689                     io_cycle_ics <= '1';
 690                 elsif std_match(match, x"C0006") then
 691                     slave_io := SLAVE_IO_SPI_FLASH;
 692                     io_cycle_spi_flash <= '1';
 693                     wb_spiflash_is_reg <= '1';
 694                 elsif std_match(match, x"C0007") then
 695                     slave_io := SLAVE_IO_GPIO;
 696                     io_cycle_gpio <= '1';
 697                 elsif std_match(match, x"C0008") then
 698                     slave_io := SLAVE_IO_UARTUSB;
 699                     io_cycle_uartusb <= '1';
 700                 else
 701                     io_cycle_none <= '1';
 702                 end if;
 703                 current_io_decode <= slave_io;
 704                 wb_sio_out.cyc <= '1';
 705             end if;
 706         end if;
 707     end process;
 708
 709     -- IO wishbone slave interconnect.
 710     --
 711     slave_io_intercon: process(all)
 712     begin
 713         wb_uart0_in <= wb_sio_out;
 714         wb_uart0_in.cyc <= io_cycle_uart;
 715         wb_uart1_in <= wb_sio_out;
 716         wb_uart1_in.cyc <= io_cycle_uart1;
 717
 718         wb_spiflash_in <= wb_sio_out;
 719         wb_spiflash_in.cyc <= io_cycle_spi_flash;
 720         -- Clear top bits so they don't make their way to the
 721         -- flash chip.
 722         wb_spiflash_in.adr(27 downto 26) <= "00";
 723
 724         wb_gpio_in <= wb_sio_out;
 725         wb_gpio_in.cyc <= io_cycle_gpio;
 726
 727         wb_uartusb_in <= wb_sio_out;
 728         wb_uartusb_in.cyc <= io_cycle_uartusb;
 729         -- valentyusb was built at base 0x0, it only needs 5 low bits
 730         wb_uartusb_in.adr <= (others => '0');
 731         wb_uartusb_in.adr(4 downto 0) <= wb_sio_out.adr(4 downto 0);
 732
 733          -- Only give xics 8 bits of wb addr (for now...)
 734         wb_xics_icp_in <= wb_sio_out;
 735         wb_xics_icp_in.adr <= (others => '0');
 736         wb_xics_icp_in.adr(5 downto 0) <= wb_sio_out.adr(5 downto 0);
 737         wb_xics_icp_in.cyc  <= io_cycle_icp;
 738         wb_xics_ics_in <= wb_sio_out;
 739         wb_xics_ics_in.adr <= (others => '0');
 740         wb_xics_ics_in.adr(9 downto 0) <= wb_sio_out.adr(9 downto 0);
 741         wb_xics_ics_in.cyc  <= io_cycle_ics;
 742
 743         wb_ext_io_in <= wb_sio_out;
 744         wb_ext_io_in.cyc <= io_cycle_external;
 745
 746         wb_syscon_in <= wb_sio_out;
 747         wb_syscon_in.cyc <= io_cycle_syscon;
 748
 749         case current_io_decode is
 750         when SLAVE_IO_EXTERNAL =>
 751             wb_sio_in <= wb_ext_io_out;
 752         when SLAVE_IO_SYSCON =>
 753             wb_sio_in <= wb_syscon_out;
 754         when SLAVE_IO_UART =>
 755             wb_sio_in <= wb_uart0_out;
 756         when SLAVE_IO_ICP =>
 757             wb_sio_in <= wb_xics_icp_out;
 758         when SLAVE_IO_ICS =>
 759             wb_sio_in <= wb_xics_ics_out;
 760         when SLAVE_IO_UART1 =>
 761             wb_sio_in <= wb_uart1_out;
 762         when SLAVE_IO_UARTUSB =>
 763             wb_sio_in <= wb_uartusb_out;
 764         when SLAVE_IO_SPI_FLASH =>
 765             wb_sio_in <= wb_spiflash_out;
 766         when SLAVE_IO_GPIO =>
 767             wb_sio_in <= wb_gpio_out;
 768         end case;
 769
 770         -- Default response, ack & return all 1's
 771         if io_cycle_none = '1' then
 772             wb_sio_in.dat <= (others => '1');
 773             wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
 774             wb_sio_in.stall <= '0';
 775         end if;
 776
 777     end process;
 778
 779     -- Syscon slave
 780     syscon0: entity work.syscon
 781         generic map(
 782             HAS_UART => true,
 783             HAS_DRAM => HAS_DRAM,
 784             BRAM_SIZE => MEMORY_SIZE,
 785             DRAM_SIZE => DRAM_SIZE,
 786             DRAM_INIT_SIZE => DRAM_INIT_SIZE,
 787             CLK_FREQ => CLK_FREQ,
 788             HAS_SPI_FLASH => HAS_SPI_FLASH,
 789             SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
 790             HAS_LITEETH => HAS_LITEETH,
 791             HAS_SD_CARD => HAS_SD_CARD,
 792             UART0_IS_16550 => UART0_IS_16550,
 793             HAS_UART1 => HAS_UART1,
 794             HAS_UARTUSB => HAS_UARTUSB
 795         )
 796         port map(
 797             clk => system_clk,
 798             rst => rst,
 799             wishbone_in => wb_syscon_in,
 800             wishbone_out => wb_syscon_out,
 801             dram_at_0 => dram_at_0,
 802             core_reset => do_core_reset,
 803             soc_reset => open -- XXX TODO
 804             );
 805
 806     --
 807     -- UART0
 808     --
 809     -- Either potato (legacy) or 16550
 810     --
 811     uart0_pp: if UART0_IS_POTATO generate
 812         uart0: entity work.pp_soc_uart
 813             generic map(
 814                 FIFO_DEPTH => 32
 815                 )
 816             port map(
 817                 clk => system_clk,
 818                 reset => rst_uart,
 819                 txd => uart0_txd,
 820                 rxd => uart0_rxd,
 821                 irq => uart0_irq,
 822                 wb_adr_in => wb_uart0_in.adr(9 downto 0) & "00",
 823                 wb_dat_in => wb_uart0_in.dat(7 downto 0),
 824                 wb_dat_out => uart0_dat8,
 825                 wb_cyc_in => wb_uart0_in.cyc,
 826                 wb_stb_in => wb_uart0_in.stb,
 827                 wb_we_in => wb_uart0_in.we,
 828                 wb_ack_out => wb_uart0_out.ack
 829                 );
 830
 831         wb_uart0_out.dat <= x"000000" & uart0_dat8;
 832         wb_uart0_out.stall <= not wb_uart0_out.ack;
 833     end generate;
 834
 835     uart0_16550 : if UART0_IS_16550 generate
 836         signal irq_l : std_ulogic;
 837     begin
 838         uart0: uart_top
 839             port map (
 840                 wb_clk_i   => system_clk,
 841                 wb_rst_i   => rst_uart,
 842                 wb_adr_i   => wb_uart0_in.adr(2 downto 0),
 843                 wb_dat_i   => wb_uart0_in.dat(7 downto 0),
 844                 wb_dat_o   => uart0_dat8,
 845                 wb_we_i    => wb_uart0_in.we,
 846                 wb_stb_i   => wb_uart0_in.stb,
 847                 wb_cyc_i   => wb_uart0_in.cyc,
 848                 wb_ack_o   => wb_uart0_out.ack,
 849                 int_o      => irq_l,
 850                 stx_pad_o  => uart0_txd,
 851                 srx_pad_i  => uart0_rxd,
 852                 rts_pad_o  => open,
 853                 cts_pad_i  => '1',
 854                 dtr_pad_o  => open,
 855                 dsr_pad_i  => '1',
 856                 ri_pad_i   => '0',
 857                 dcd_pad_i  => '1'
 858                 );
 859
 860         -- Add a register on the irq out, helps timing
 861         uart0_irq_latch: process(system_clk)
 862         begin
 863             if rising_edge(system_clk) then
 864                 uart0_irq <= irq_l;
 865             end if;
 866         end process;
 867
 868         wb_uart0_out.dat <= x"000000" & uart0_dat8;
 869         wb_uart0_out.stall <= not wb_uart0_out.ack;
 870     end generate;
 871
 872
 873     uart0_valentyusb : if HAS_UARTUSB generate
 874         component valentyusb port (
 875                 clk_clksys : in std_ulogic;
 876                 clk_clk48 : in std_ulogic;
 877                 reset : in std_ulogic;
 878                 usb_d_p : in std_ulogic;
 879                 usb_d_n : in std_ulogic;
 880                 usb_pullup : out std_ulogic;
 881                 usb_tx_en : out std_ulogic;
 882                 interrupt : out std_ulogic;
 883                 wishbone_adr        : in std_ulogic_vector(29 downto 0);
 884                 wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
 885                 wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
 886                 wishbone_sel        : in std_ulogic_vector(3 downto 0);
 887                 wishbone_cyc        : in std_ulogic;
 888                 wishbone_stb        : in std_ulogic;
 889                 wishbone_ack        : out std_ulogic;
 890                 wishbone_we         : in std_ulogic;
 891                 wishbone_cti        : in std_ulogic_vector(2 downto 0);
 892                 wishbone_bte        : in std_ulogic_vector(1 downto 0);
 893                 wishbone_err        : out std_ulogic
 894                 );
 895         end component;
 896         signal irq_l : std_ulogic;
 897     begin
 898         uart0: valentyusb
 899             port map (
 900                 clk_clksys => system_clk,
 901                 clk_clk48 => clk_48,
 902                 reset   => rst_uart,
 903                 usb_d_p => usb_d_p,
 904                 usb_d_n => usb_d_n,
 905                 usb_pullup => usb_pullup,
 906                 -- TODO, output flag
 907                 usb_tx_en => open,
 908                 wishbone_adr => "0000000000000000" & wb_uartusb_in.adr(13 downto 0),
 909                 wishbone_dat_r => wb_uartusb_out.dat,
 910                 wishbone_dat_w => wb_uartusb_in.dat,
 911                 wishbone_sel   => wb_uartusb_in.sel,
 912                 wishbone_cyc => wb_uartusb_in.cyc,
 913                 wishbone_stb => wb_uartusb_in.stb,
 914                 wishbone_ack => wb_uartusb_out.ack,
 915                 wishbone_we => wb_uartusb_in.we,
 916                 interrupt => irq_l,
 917                 -- XXX matt check this
 918                 wishbone_cti => "000",
 919                 -- XXX matt check this
 920                 wishbone_bte => "00",
 921                 wishbone_err => open
 922                 );
 923
 924         wb_uartusb_out.stall <= not wb_uartusb_out.ack;
 925
 926         -- Add a register on the irq out, helps timing
 927         uartusb_irq_latch: process(system_clk)
 928         begin
 929             if rising_edge(system_clk) then
 930                 uartusb_irq <= irq_l;
 931             end if;
 932         end process;
 933     end generate;
 934
 935     --
 936     -- UART1
 937     --
 938     -- Always 16550 if it exists
 939     --
 940     uart1: if HAS_UART1 generate
 941         signal irq_l : std_ulogic;
 942     begin
 943         uart1: uart_top
 944             port map (
 945                 wb_clk_i   => system_clk,
 946                 wb_rst_i   => rst_uart,
 947                 wb_adr_i   => wb_uart1_in.adr(2 downto 0),
 948                 wb_dat_i   => wb_uart1_in.dat(7 downto 0),
 949                 wb_dat_o   => uart1_dat8,
 950                 wb_we_i    => wb_uart1_in.we,
 951                 wb_stb_i   => wb_uart1_in.stb,
 952                 wb_cyc_i   => wb_uart1_in.cyc,
 953                 wb_ack_o   => wb_uart1_out.ack,
 954                 int_o      => irq_l,
 955                 stx_pad_o  => uart1_txd,
 956                 srx_pad_i  => uart1_rxd,
 957                 rts_pad_o  => open,
 958                 cts_pad_i  => '1',
 959                 dtr_pad_o  => open,
 960                 dsr_pad_i  => '1',
 961                 ri_pad_i   => '0',
 962                 dcd_pad_i  => '1'
 963                 );
 964         -- Add a register on the irq out, helps timing
 965         uart0_irq_latch: process(system_clk)
 966         begin
 967             if rising_edge(system_clk) then
 968                 uart1_irq <= irq_l;
 969             end if;
 970         end process;
 971         wb_uart1_out.dat <= x"000000" & uart1_dat8;
 972         wb_uart1_out.stall <= not wb_uart1_out.ack;
 973     end generate;
 974
 975     no_uart1 : if not HAS_UART1 generate
 976         wb_uart1_out.dat <= x"00000000";
 977         wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
 978         wb_uart1_out.stall <= '0';
 979         uart1_irq <= '0';
 980     end generate;
 981
 982     spiflash_gen: if HAS_SPI_FLASH generate
 983         spiflash: entity work.spi_flash_ctrl
 984             generic map (
 985                 DATA_LINES    => SPI_FLASH_DLINES,
 986                 DEF_CLK_DIV   => SPI_FLASH_DEF_CKDV,
 987                 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD,
 988                 BOOT_CLOCKS   => SPI_BOOT_CLOCKS
 989                 )
 990             port map(
 991                 rst => rst_spi,
 992                 clk => system_clk,
 993                 wb_in => wb_spiflash_in,
 994                 wb_out => wb_spiflash_out,
 995                 wb_sel_reg => wb_spiflash_is_reg,
 996                 wb_sel_map => wb_spiflash_is_map,
 997                 sck => spi_flash_sck,
 998                 cs_n => spi_flash_cs_n,
 999                 sdat_o => spi_flash_sdat_o,
1000                 sdat_oe => spi_flash_sdat_oe,
1001                 sdat_i => spi_flash_sdat_i
1002                 );
1003     end generate;
1004
1005     no_spi0_gen: if not HAS_SPI_FLASH generate
1006         wb_spiflash_out.dat   <= (others => '1');
1007         wb_spiflash_out.ack   <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
1008         wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
1009     end generate;
1010
1011     xics_icp: entity work.xics_icp
1012         port map(
1013             clk => system_clk,
1014             rst => rst_xics,
1015             wb_in => wb_xics_icp_in,
1016             wb_out => wb_xics_icp_out,
1017             ics_in => ics_to_icp,
1018             core_irq_out => core_ext_irq
1019             );
1020
1021     xics_ics: entity work.xics_ics
1022         generic map(
1023             SRC_NUM   => 16,
1024             PRIO_BITS => 3
1025             )
1026         port map(
1027             clk => system_clk,
1028             rst => rst_xics,
1029             wb_in => wb_xics_ics_in,
1030             wb_out => wb_xics_ics_out,
1031             int_level_in => int_level_in,
1032             icp_out => ics_to_icp
1033             );
1034
1035     gpio0_gen: if HAS_GPIO generate
1036         gpio : entity work.gpio
1037             generic map(
1038                 NGPIO => NGPIO
1039                 )
1040             port map(
1041                 clk      => system_clk,
1042                 rst      => rst_gpio,
1043                 wb_in    => wb_gpio_in,
1044                 wb_out   => wb_gpio_out,
1045                 gpio_in  => gpio_in,
1046                 gpio_out => gpio_out,
1047                 gpio_dir => gpio_dir,
1048                 intr     => gpio_intr
1049                 );
1050     end generate;
1051
1052     -- Assign external interrupts
1053     interrupts: process(all)
1054     begin
1055         int_level_in <= (others => '0');
1056         int_level_in(0) <= uart0_irq;
1057         int_level_in(1) <= ext_irq_eth;
1058         int_level_in(2) <= uart1_irq;
1059         int_level_in(3) <= ext_irq_sdcard;
1060         int_level_in(4) <= gpio_intr;
1061         int_level_in(5) <= uartusb_irq;
1062     end process;
1063
1064     -- BRAM Memory slave
1065     bram: if MEMORY_SIZE /= 0 generate
1066         bram0: entity work.wishbone_bram_wrapper
1067             generic map(
1068                 MEMORY_SIZE   => MEMORY_SIZE,
1069                 RAM_INIT_FILE => RAM_INIT_FILE
1070                 )
1071             port map(
1072                 clk => system_clk,
1073                 rst => rst_bram,
1074                 wishbone_in => wb_bram_in,
1075                 wishbone_out => wb_bram_out
1076                 );
1077     end generate;
1078
1079     no_bram: if MEMORY_SIZE = 0 generate
1080         wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
1081         wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
1082         wb_bram_out.stall <= not wb_bram_out.ack;
1083     end generate;
1084
1085     -- DMI(debug bus) <-> JTAG bridge
1086     dtm: entity work.dmi_dtm
1087         generic map(
1088             ABITS => 8,
1089             DBITS => 64
1090             )
1091         port map(
1092             sys_clk     => system_clk,
1093             sys_reset   => rst_dtm,
1094             dmi_addr    => dmi_addr,
1095             dmi_din     => dmi_din,
1096             dmi_dout    => dmi_dout,
1097             dmi_req     => dmi_req,
1098             dmi_wr      => dmi_wr,
1099             dmi_ack     => dmi_ack
1100             );
1101
1102     -- DMI interconnect
1103     dmi_intercon: process(dmi_addr, dmi_req,
1104                           dmi_wb_ack, dmi_wb_dout,
1105                           dmi_core_ack, dmi_core_dout)
1106
1107         -- DMI address map (each address is a full 64-bit register)
1108         --
1109         -- Offset:   Size:    Slave:
1110         --  0         4       Wishbone
1111         -- 10        16       Core
1112
1113         type slave_type is (SLAVE_WB,
1114                             SLAVE_CORE,
1115                             SLAVE_NONE);
1116         variable slave : slave_type;
1117     begin
1118         -- Simple address decoder
1119         slave := SLAVE_NONE;
1120         if std_match(dmi_addr, "000000--") then
1121             slave := SLAVE_WB;
1122         elsif std_match(dmi_addr, "0001----") then
1123             slave := SLAVE_CORE;
1124         end if;
1125
1126         -- DMI muxing
1127         dmi_wb_req <= '0';
1128         dmi_core_req <= '0';
1129         case slave is
1130         when SLAVE_WB =>
1131             dmi_wb_req <= dmi_req;
1132             dmi_ack <= dmi_wb_ack;
1133             dmi_din <= dmi_wb_dout;
1134         when SLAVE_CORE =>
1135             dmi_core_req <= dmi_req;
1136             dmi_ack <= dmi_core_ack;
1137             dmi_din <= dmi_core_dout;
1138         when others =>
1139             dmi_ack <= dmi_req;
1140             dmi_din <= (others => '1');
1141         end case;
1142
1143         -- SIM magic exit
1144         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
1145             stop;
1146         end if;
1147     end process;
1148
1149     -- Wishbone debug master (TODO: Add a DMI address decoder)
1150     wishbone_debug: entity work.wishbone_debug_master
1151         port map(clk => system_clk,
1152                  rst => rst_wbdb,
1153                  dmi_addr => dmi_addr(1 downto 0),
1154                  dmi_dout => dmi_wb_dout,
1155                  dmi_din => dmi_dout,
1156                  dmi_wr => dmi_wr,
1157                  dmi_ack => dmi_wb_ack,
1158                  dmi_req => dmi_wb_req,
1159                  wb_in => wishbone_debug_in,
1160                  wb_out => wishbone_debug_out);
1161
1162 --pragma synthesis_off
1163     wb_x_state: process(system_clk)
1164     begin
1165         if rising_edge(system_clk) then
1166             if not rst then
1167                 -- Wishbone arbiter
1168                 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
1169                 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
1170                 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
1171                 assert not(is_x(wb_masters_in(0).ack)) severity failure;
1172                 assert not(is_x(wb_masters_in(1).ack)) severity failure;
1173                 assert not(is_x(wb_masters_in(2).ack)) severity failure;
1174
1175                 -- Main memory wishbones
1176                 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
1177                 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
1178                 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
1179                 assert not(is_x(wb_bram_out.ack)) severity failure;
1180                 assert not(is_x(wb_dram_out.ack)) severity failure;
1181                 assert not(is_x(wb_io_out.ack)) severity failure;
1182
1183                 -- I/O wishbones
1184                 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
1185                 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
1186                 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
1187                 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
1188                 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
1189                 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
1190                 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
1191                 assert not(is_x(wb_uart0_out.ack)) severity failure;
1192                 assert not(is_x(wb_uart1_out.ack)) severity failure;
1193                 assert not(is_x(wb_spiflash_out.ack)) severity failure;
1194                 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
1195                 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
1196                 assert not(is_x(wb_ext_io_out.ack)) severity failure;
1197                 assert not(is_x(wb_syscon_out.ack)) severity failure;
1198             end if;
1199         end if;
1200     end process;
1201 --pragma synthesis_on
1202
1203 end architecture behaviour;