soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
  14 --
  15 -- Main bus:
  16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
  17 -- 0x40000000: DRAM (when present)
  18 -- 0x80000000: Block RAM (aliased & repeated)
  19
  20 -- IO Bus:
  21 -- 0xc0000000: SYSCON
  22 -- 0xc0002000: UART0
  23 -- 0xc0003000: UART1 (if any)
  24 -- 0xc0004000: XICS ICP
  25 -- 0xc0005000: XICS ICS
  26 -- 0xc0006000: SPI Flash controller
  27 -- 0xc8nnnnnn: External IO bus
  28 -- 0xf0000000: Flash "ROM" mapping
  29 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
  30
  31 -- External IO bus:
  32 -- 0xc8000000: LiteDRAM control (CSRs)
  33 -- 0xc8020000: LiteEth CSRs (*)
  34 -- 0xc8030000: LiteEth MMIO (*)
  35
  36 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
  37 --     are actually decoded as a single wishbone which LiteEth will
  38 --     internally split based on bit 16.
  39
  40 -- (**) DRAM init code is currently special and goes to the external
  41 --      IO bus, this will be fixed when it's moved out of litedram and
  42 --      into the main SoC once we have a common "firmware".
  43
  44 -- Interrupt numbers:
  45 --
  46 --   0  : UART0
  47 --   1  : Ethernet
  48
  49 entity soc is
  50     generic (
  51         MEMORY_SIZE        : natural;
  52         RAM_INIT_FILE      : string;
  53         CLK_FREQ           : positive;
  54         SIM                : boolean;
  55         HAS_FPU            : boolean := true;
  56         HAS_BTC            : boolean := true;
  57         DISABLE_FLATTEN_CORE : boolean := false;
  58         HAS_DRAM           : boolean  := false;
  59         DRAM_SIZE          : integer := 0;
  60         DRAM_INIT_SIZE     : integer := 0;
  61         HAS_SPI_FLASH      : boolean := false;
  62         SPI_FLASH_DLINES   : positive := 1;
  63         SPI_FLASH_OFFSET   : integer := 0;
  64         SPI_FLASH_DEF_CKDV : natural := 2;
  65         SPI_FLASH_DEF_QUAD : boolean := false;
  66         SPI_BOOT_CLOCKS    : boolean := true;
  67         LOG_LENGTH         : natural := 512;
  68         HAS_LITEETH        : boolean := false;
  69         UART0_IS_16550     : boolean := true;
  70         HAS_UART1          : boolean := false;
  71         ICACHE_NUM_LINES   : natural := 64;
  72         ICACHE_NUM_WAYS    : natural := 2;
  73         ICACHE_TLB_SIZE    : natural := 64;
  74         DCACHE_NUM_LINES   : natural := 64;
  75         DCACHE_NUM_WAYS    : natural := 2;
  76         DCACHE_TLB_SET_SIZE : natural := 64;
  77         DCACHE_TLB_NUM_WAYS : natural := 2
  78         );
  79     port(
  80         rst          : in  std_ulogic;
  81         system_clk   : in  std_ulogic;
  82
  83         -- "Large" (64-bit) DRAM wishbone
  84         wb_dram_in       : out wishbone_master_out;
  85         wb_dram_out      : in wishbone_slave_out := wishbone_slave_out_init;
  86
  87         -- "Small" (32-bit) external IO wishbone
  88         wb_ext_io_in         : out wb_io_master_out;
  89         wb_ext_io_out        : in wb_io_slave_out := wb_io_slave_out_init;
  90         wb_ext_is_dram_csr   : out std_ulogic;
  91         wb_ext_is_dram_init  : out std_ulogic;
  92         wb_ext_is_eth        : out std_ulogic;
  93
  94         -- External interrupts
  95         ext_irq_eth          : in std_ulogic := '0';
  96
  97         -- UART0 signals:
  98         uart0_txd    : out std_ulogic;
  99         uart0_rxd    : in  std_ulogic := '0';
 100
 101         -- UART1 signals:
 102         uart1_txd    : out std_ulogic;
 103         uart1_rxd    : in  std_ulogic := '0';
 104
 105         -- SPI Flash signals
 106         spi_flash_sck     : out std_ulogic;
 107         spi_flash_cs_n    : out std_ulogic;
 108         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 109         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 110         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
 111
 112         -- DRAM controller signals
 113         alt_reset    : in std_ulogic := '0'
 114         );
 115 end entity soc;
 116
 117 architecture behaviour of soc is
 118
 119     -- Wishbone master signals:
 120     signal wishbone_dcore_in  : wishbone_slave_out;
 121     signal wishbone_dcore_out : wishbone_master_out;
 122     signal wishbone_icore_in  : wishbone_slave_out;
 123     signal wishbone_icore_out : wishbone_master_out;
 124     signal wishbone_debug_in : wishbone_slave_out;
 125     signal wishbone_debug_out : wishbone_master_out;
 126
 127     -- Arbiter array (ghdl doesnt' support assigning the array
 128     -- elements in the entity instantiation)
 129     constant NUM_WB_MASTERS : positive := 3;
 130     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
 131     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
 132
 133     -- Wishbone master (output of arbiter):
 134     signal wb_master_in       : wishbone_slave_out;
 135     signal wb_master_out      : wishbone_master_out;
 136
 137     -- Main "IO" bus, from main slave decoder to the latch
 138     signal wb_io_in     : wishbone_master_out;
 139     signal wb_io_out    : wishbone_slave_out;
 140
 141     -- Secondary (smaller) IO bus after the IO bus latch
 142     signal wb_sio_out    : wb_io_master_out;
 143     signal wb_sio_in     : wb_io_slave_out;
 144
 145     -- Syscon signals
 146     signal dram_at_0     : std_ulogic;
 147     signal do_core_reset    : std_ulogic;
 148     signal wb_syscon_in  : wb_io_master_out;
 149     signal wb_syscon_out : wb_io_slave_out;
 150
 151     -- UART0 signals:
 152     signal wb_uart0_in   : wb_io_master_out;
 153     signal wb_uart0_out  : wb_io_slave_out;
 154     signal uart0_dat8    : std_ulogic_vector(7 downto 0);
 155     signal uart0_irq     : std_ulogic;
 156
 157     -- UART1 signals:
 158     signal wb_uart1_in   : wb_io_master_out;
 159     signal wb_uart1_out  : wb_io_slave_out;
 160     signal uart1_dat8    : std_ulogic_vector(7 downto 0);
 161     signal uart1_irq     : std_ulogic;
 162
 163     -- SPI Flash controller signals:
 164     signal wb_spiflash_in     : wb_io_master_out;
 165     signal wb_spiflash_out    : wb_io_slave_out;
 166     signal wb_spiflash_is_reg : std_ulogic;
 167     signal wb_spiflash_is_map : std_ulogic;
 168
 169     -- XICS signals:
 170     signal wb_xics_icp_in   : wb_io_master_out;
 171     signal wb_xics_icp_out  : wb_io_slave_out;
 172     signal wb_xics_ics_in   : wb_io_master_out;
 173     signal wb_xics_ics_out  : wb_io_slave_out;
 174     signal int_level_in     : std_ulogic_vector(15 downto 0);
 175     signal ics_to_icp       : ics_to_icp_t;
 176     signal core_ext_irq     : std_ulogic;
 177
 178     -- Main memory signals:
 179     signal wb_bram_in     : wishbone_master_out;
 180     signal wb_bram_out    : wishbone_slave_out;
 181
 182     -- DMI debug bus signals
 183     signal dmi_addr     : std_ulogic_vector(7 downto 0);
 184     signal dmi_din      : std_ulogic_vector(63 downto 0);
 185     signal dmi_dout     : std_ulogic_vector(63 downto 0);
 186     signal dmi_req      : std_ulogic;
 187     signal dmi_wr       : std_ulogic;
 188     signal dmi_ack      : std_ulogic;
 189
 190     -- Per slave DMI signals
 191     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
 192     signal dmi_wb_req   : std_ulogic;
 193     signal dmi_wb_ack   : std_ulogic;
 194     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
 195     signal dmi_core_req   : std_ulogic;
 196     signal dmi_core_ack   : std_ulogic;
 197
 198     -- Delayed/latched resets and alt_reset
 199     signal rst_core    : std_ulogic := '1';
 200     signal rst_uart    : std_ulogic := '1';
 201     signal rst_xics    : std_ulogic := '1';
 202     signal rst_spi     : std_ulogic := '1';
 203     signal rst_bram    : std_ulogic := '1';
 204     signal rst_dtm     : std_ulogic := '1';
 205     signal rst_wbar    : std_ulogic := '1';
 206     signal rst_wbdb    : std_ulogic := '1';
 207     signal alt_reset_d : std_ulogic;
 208
 209     -- IO branch split:
 210     type slave_io_type is (SLAVE_IO_SYSCON,
 211                            SLAVE_IO_UART,
 212                            SLAVE_IO_ICP,
 213                            SLAVE_IO_ICS,
 214                            SLAVE_IO_UART1,
 215                            SLAVE_IO_SPI_FLASH_REG,
 216                            SLAVE_IO_SPI_FLASH_MAP,
 217                            SLAVE_IO_EXTERNAL,
 218                            SLAVE_IO_NONE);
 219     signal slave_io_dbg : slave_io_type;
 220
 221     -- This is the component exported by the 16550 compatible
 222     -- UART from FuseSoC.
 223     --
 224     component uart_top port (
 225         wb_clk_i    : in std_ulogic;
 226         wb_rst_i    : in std_ulogic;
 227         wb_adr_i    : in std_ulogic_vector(2 downto 0);
 228         wb_dat_i    : in std_ulogic_vector(7 downto 0);
 229         wb_dat_o    : out std_ulogic_vector(7 downto 0);
 230         wb_we_i     : in std_ulogic;
 231         wb_stb_i    : in std_ulogic;
 232         wb_cyc_i    : in std_ulogic;
 233         wb_ack_o    : out std_ulogic;
 234         int_o       : out std_ulogic;
 235         stx_pad_o   : out std_ulogic;
 236         srx_pad_i   : in std_ulogic;
 237         rts_pad_o   : out std_ulogic;
 238         cts_pad_i   : in std_ulogic;
 239         dtr_pad_o   : out std_ulogic;
 240         dsr_pad_i   : in std_ulogic;
 241         ri_pad_i    : in std_ulogic;
 242         dcd_pad_i   : in std_ulogic
 243         );
 244     end component;
 245 begin
 246
 247     resets: process(system_clk)
 248     begin
 249         if rising_edge(system_clk) then
 250             rst_core    <= rst or do_core_reset;
 251             rst_uart    <= rst;
 252             rst_spi     <= rst;
 253             rst_xics    <= rst;
 254             rst_bram    <= rst;
 255             rst_dtm     <= rst;
 256             rst_wbar    <= rst;
 257             rst_wbdb    <= rst;
 258             alt_reset_d <= alt_reset;
 259         end if;
 260     end process;
 261
 262     -- Processor core
 263     processor: entity work.core
 264         generic map(
 265             SIM => SIM,
 266             HAS_FPU => HAS_FPU,
 267             HAS_BTC => HAS_BTC,
 268             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 269             ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
 270             LOG_LENGTH => LOG_LENGTH,
 271             ICACHE_NUM_LINES => ICACHE_NUM_LINES,
 272             ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
 273             ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
 274             DCACHE_NUM_LINES => DCACHE_NUM_LINES,
 275             DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
 276             DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
 277             DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
 278             )
 279         port map(
 280             clk => system_clk,
 281             rst => rst_core,
 282             alt_reset => alt_reset_d,
 283             wishbone_insn_in => wishbone_icore_in,
 284             wishbone_insn_out => wishbone_icore_out,
 285             wishbone_data_in => wishbone_dcore_in,
 286             wishbone_data_out => wishbone_dcore_out,
 287             dmi_addr => dmi_addr(3 downto 0),
 288             dmi_dout => dmi_core_dout,
 289             dmi_din => dmi_dout,
 290             dmi_wr => dmi_wr,
 291             dmi_ack => dmi_core_ack,
 292             dmi_req => dmi_core_req,
 293             ext_irq => core_ext_irq
 294             );
 295
 296     -- Wishbone bus master arbiter & mux
 297     wb_masters_out <= (0 => wishbone_dcore_out,
 298                        1 => wishbone_icore_out,
 299                        2 => wishbone_debug_out);
 300     wishbone_dcore_in <= wb_masters_in(0);
 301     wishbone_icore_in <= wb_masters_in(1);
 302     wishbone_debug_in <= wb_masters_in(2);
 303     wishbone_arbiter_0: entity work.wishbone_arbiter
 304         generic map(
 305             NUM_MASTERS => NUM_WB_MASTERS
 306             )
 307         port map(
 308             clk => system_clk,
 309             rst => rst_wbar,
 310             wb_masters_in => wb_masters_out,
 311             wb_masters_out => wb_masters_in,
 312             wb_slave_out => wb_master_out,
 313             wb_slave_in => wb_master_in
 314             );
 315
 316     -- Top level Wishbone slaves address decoder & mux
 317     --
 318     -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
 319     -- 0000  - BRAM
 320     -- 0001  - DRAM
 321     -- 01xx  - DRAM
 322     -- 10xx  - BRAM
 323     -- 11xx  - IO
 324     --
 325     slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
 326         type slave_top_type is (SLAVE_TOP_BRAM,
 327                                 SLAVE_TOP_DRAM,
 328                                 SLAVE_TOP_IO);
 329         variable slave_top : slave_top_type;
 330         variable top_decode : std_ulogic_vector(3 downto 0);
 331     begin
 332         -- Top-level address decoder
 333         top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
 334         slave_top := SLAVE_TOP_BRAM;
 335         if    std_match(top_decode, "0000") then
 336             slave_top := SLAVE_TOP_BRAM;
 337         elsif std_match(top_decode, "0001") then
 338             slave_top := SLAVE_TOP_DRAM;
 339         elsif std_match(top_decode, "01--") then
 340             slave_top := SLAVE_TOP_DRAM;
 341         elsif std_match(top_decode, "10--") then
 342             slave_top := SLAVE_TOP_BRAM;
 343         elsif std_match(top_decode, "11--") then
 344             slave_top := SLAVE_TOP_IO;
 345         end if;
 346
 347         -- Top level wishbone muxing.
 348         wb_bram_in <= wb_master_out;
 349         wb_bram_in.cyc  <= '0';
 350         wb_dram_in <= wb_master_out;
 351         wb_dram_in.cyc  <= '0';
 352         wb_io_in <= wb_master_out;
 353         wb_io_in.cyc  <= '0';
 354         case slave_top is
 355         when SLAVE_TOP_BRAM =>
 356             wb_bram_in.cyc <= wb_master_out.cyc;
 357             wb_master_in <= wb_bram_out;
 358         when SLAVE_TOP_DRAM =>
 359             if HAS_DRAM then
 360                 wb_dram_in.cyc <= wb_master_out.cyc;
 361                 wb_master_in <= wb_dram_out;
 362             else
 363                 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
 364                 wb_master_in.dat <= (others => '1');
 365                 wb_master_in.stall <= '0';
 366             end if;
 367         when SLAVE_TOP_IO =>
 368             wb_io_in.cyc <= wb_master_out.cyc;
 369             wb_master_in <= wb_io_out;
 370         end case;
 371
 372     end process slave_top_intercon;
 373
 374     -- IO wishbone slave 64->32 bits converter
 375     --
 376     -- For timing reasons, this adds a one cycle latch on the way both
 377     -- in and out. This relaxes timing and routing pressure on the "main"
 378     -- memory bus by moving all simple IOs to a slower 32-bit bus.
 379     --
 380     -- This implementation is rather dumb at the moment, no stash buffer,
 381     -- so we stall whenever that latch is busy. This can be improved.
 382     --
 383     slave_io_latch: process(system_clk)
 384         -- State
 385         type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
 386         variable state : state_t;
 387
 388         -- Misc
 389         variable has_top : boolean;
 390         variable has_bot : boolean;
 391     begin
 392         if rising_edge(system_clk) then
 393             if (rst) then
 394                 state := IDLE;
 395                 wb_io_out.ack <= '0';
 396                 wb_io_out.stall <= '0';
 397                 wb_sio_out.cyc <= '0';
 398                 wb_sio_out.stb <= '0';
 399                 has_top := false;
 400                 has_bot := false;
 401             else
 402                 case state is
 403                 when IDLE =>
 404                     -- Clear ACK in case it was set
 405                     wb_io_out.ack <= '0';
 406
 407                     -- Do we have a cycle ?
 408                     if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
 409                         -- Stall master until we are done, we are't (yet) pipelining
 410                         -- this, it's all slow IOs.
 411                         wb_io_out.stall <= '1';
 412
 413                         -- Start cycle downstream
 414                         wb_sio_out.cyc <= '1';
 415                         wb_sio_out.stb <= '1';
 416
 417                         -- Copy write enable to IO out, copy address as well
 418                         wb_sio_out.we <= wb_io_in.we;
 419                         wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
 420
 421                         -- Do we have a top word and/or a bottom word ?
 422                         has_top := wb_io_in.sel(7 downto 4) /= "0000";
 423                         has_bot := wb_io_in.sel(3 downto 0) /= "0000";
 424
 425                         -- If we have a bottom word, handle it first, otherwise
 426                         -- send the top word down. XXX Split the actual mux out
 427                         -- and only generate a control signal.
 428                         if has_bot then
 429                             if wb_io_in.we = '1' then
 430                                 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
 431                             end if;
 432                             wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
 433
 434                             -- Wait for ack
 435                             state := WAIT_ACK_BOT;
 436                         else
 437                             if wb_io_in.we = '1' then
 438                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 439                             end if;
 440                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 441
 442                             -- Bump address
 443                             wb_sio_out.adr(2) <= '1';
 444
 445                             -- Wait for ack
 446                             state := WAIT_ACK_TOP;
 447                         end if;
 448                     end if;
 449                 when WAIT_ACK_BOT =>
 450                     -- If we aren't stalled by the device, clear stb
 451                     if wb_sio_in.stall = '0' then
 452                         wb_sio_out.stb <= '0';
 453                     end if;
 454
 455                     -- Handle ack
 456                     if wb_sio_in.ack = '1' then
 457                         -- If it's a read, latch the data
 458                         if wb_sio_out.we = '0' then
 459                             wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
 460                         end if;
 461
 462                         -- Do we have a "top" part as well ?
 463                         if has_top then
 464                             -- Latch data & sel
 465                             if wb_io_in.we = '1' then
 466                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 467                             end if;
 468                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 469
 470                             -- Bump address and set STB
 471                             wb_sio_out.adr(2) <= '1';
 472                             wb_sio_out.stb <= '1';
 473
 474                             -- Wait for new ack
 475                             state := WAIT_ACK_TOP;
 476                         else
 477                             -- We are done, ack up, clear cyc downstram
 478                             wb_sio_out.cyc <= '0';
 479
 480                             -- And ack & unstall upstream
 481                             wb_io_out.ack <= '1';
 482                             wb_io_out.stall <= '0';
 483
 484                             -- Wait for next one
 485                             state := IDLE;
 486                         end if;
 487                     end if;
 488                 when WAIT_ACK_TOP =>
 489                     -- If we aren't stalled by the device, clear stb
 490                     if wb_sio_in.stall = '0' then
 491                         wb_sio_out.stb <= '0';
 492                     end if;
 493
 494                     -- Handle ack
 495                     if wb_sio_in.ack = '1' then
 496                         -- If it's a read, latch the data
 497                         if wb_sio_out.we = '0' then
 498                             wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
 499                         end if;
 500
 501                         -- We are done, ack up, clear cyc downstram
 502                         wb_sio_out.cyc <= '0';
 503
 504                         -- And ack & unstall upstream
 505                         wb_io_out.ack <= '1';
 506                         wb_io_out.stall <= '0';
 507
 508                         -- Wait for next one
 509                         state := IDLE;
 510                     end if;
 511                 end case;
 512             end if;
 513         end if;
 514     end process;
 515
 516     -- IO wishbone slave intercon.
 517     --
 518     slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
 519                                wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
 520                                wb_spiflash_out)
 521         variable slave_io : slave_io_type;
 522
 523         variable match : std_ulogic_vector(31 downto 12);
 524         variable ext_valid : boolean;
 525     begin
 526
 527         -- Simple address decoder.
 528         slave_io := SLAVE_IO_NONE;
 529         match := "11" & wb_sio_out.adr(29 downto 12);
 530         if    std_match(match, x"FF---") and HAS_DRAM then
 531             slave_io := SLAVE_IO_EXTERNAL;
 532         elsif std_match(match, x"F----") then
 533             slave_io := SLAVE_IO_SPI_FLASH_MAP;
 534         elsif std_match(match, x"C0000") then
 535             slave_io := SLAVE_IO_SYSCON;
 536         elsif std_match(match, x"C0002") then
 537             slave_io := SLAVE_IO_UART;
 538         elsif std_match(match, x"C0003") then
 539             slave_io := SLAVE_IO_UART1;
 540         elsif std_match(match, x"C8---") then
 541             slave_io := SLAVE_IO_EXTERNAL;
 542         elsif std_match(match, x"C0004") then
 543             slave_io := SLAVE_IO_ICP;
 544         elsif std_match(match, x"C0005") then
 545             slave_io := SLAVE_IO_ICS;
 546         elsif std_match(match, x"C0006") then
 547             slave_io := SLAVE_IO_SPI_FLASH_REG;
 548         end if;
 549         slave_io_dbg <= slave_io;
 550         wb_uart0_in <= wb_sio_out;
 551         wb_uart0_in.cyc <= '0';
 552         wb_uart1_in <= wb_sio_out;
 553         wb_uart1_in.cyc <= '0';
 554         wb_spiflash_in <= wb_sio_out;
 555         wb_spiflash_in.cyc <= '0';
 556         wb_spiflash_is_reg <= '0';
 557         wb_spiflash_is_map <= '0';
 558
 559          -- Only give xics 8 bits of wb addr (for now...)
 560         wb_xics_icp_in <= wb_sio_out;
 561         wb_xics_icp_in.adr <= (others => '0');
 562         wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
 563         wb_xics_icp_in.cyc  <= '0';
 564         wb_xics_ics_in <= wb_sio_out;
 565         wb_xics_ics_in.adr <= (others => '0');
 566         wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
 567         wb_xics_ics_in.cyc  <= '0';
 568
 569         wb_ext_io_in <= wb_sio_out;
 570         wb_ext_io_in.cyc <= '0';
 571
 572         wb_syscon_in <= wb_sio_out;
 573         wb_syscon_in.cyc <= '0';
 574
 575         wb_ext_is_dram_csr   <= '0';
 576         wb_ext_is_dram_init  <= '0';
 577         wb_ext_is_eth        <= '0';
 578
 579         -- Default response, ack & return all 1's
 580         wb_sio_in.dat <= (others => '1');
 581         wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
 582         wb_sio_in.stall <= '0';
 583
 584         case slave_io is
 585         when SLAVE_IO_EXTERNAL =>
 586             -- Ext IO "chip selects"
 587             --
 588             -- DRAM init is special at 0xFF* so we just test the top
 589             -- bit. Everything else is at 0xC8* so we test only bits
 590             -- 23 downto 16.
 591             --
 592             ext_valid := false;
 593             if wb_sio_out.adr(29) = '1' and HAS_DRAM then  -- DRAM init is special
 594                 wb_ext_is_dram_init <= '1';
 595                 ext_valid := true;
 596             elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
 597                 wb_ext_is_dram_csr  <= '1';
 598                 ext_valid := true;
 599             elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
 600                 wb_ext_is_eth       <= '1';
 601                 ext_valid := true;
 602             elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
 603                 wb_ext_is_eth       <= '1';
 604                 ext_valid := true;
 605             end if;
 606             if ext_valid then
 607                 wb_ext_io_in.cyc <= wb_sio_out.cyc;
 608                 wb_sio_in <= wb_ext_io_out;
 609             end if;
 610
 611         when SLAVE_IO_SYSCON =>
 612             wb_syscon_in.cyc <= wb_sio_out.cyc;
 613             wb_sio_in <= wb_syscon_out;
 614         when SLAVE_IO_UART =>
 615             wb_uart0_in.cyc <= wb_sio_out.cyc;
 616             wb_sio_in <= wb_uart0_out;
 617         when SLAVE_IO_ICP =>
 618             wb_xics_icp_in.cyc <= wb_sio_out.cyc;
 619             wb_sio_in <= wb_xics_icp_out;
 620         when SLAVE_IO_ICS =>
 621             wb_xics_ics_in.cyc <= wb_sio_out.cyc;
 622             wb_sio_in <= wb_xics_ics_out;
 623         when SLAVE_IO_UART1 =>
 624             wb_uart1_in.cyc <= wb_sio_out.cyc;
 625             wb_sio_in <= wb_uart1_out;
 626         when SLAVE_IO_SPI_FLASH_MAP =>
 627             -- Clear top bits so they don't make their way to the
 628             -- fash chip.
 629             wb_spiflash_in.adr(29 downto 28) <= "00";
 630             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 631             wb_sio_in <= wb_spiflash_out;
 632             wb_spiflash_is_map <= '1';
 633         when SLAVE_IO_SPI_FLASH_REG =>
 634             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 635             wb_sio_in <= wb_spiflash_out;
 636             wb_spiflash_is_reg <= '1';
 637         when others =>
 638         end case;
 639
 640     end process;
 641
 642     -- Syscon slave
 643     syscon0: entity work.syscon
 644         generic map(
 645             HAS_UART => true,
 646             HAS_DRAM => HAS_DRAM,
 647             BRAM_SIZE => MEMORY_SIZE,
 648             DRAM_SIZE => DRAM_SIZE,
 649             DRAM_INIT_SIZE => DRAM_INIT_SIZE,
 650             CLK_FREQ => CLK_FREQ,
 651             HAS_SPI_FLASH => HAS_SPI_FLASH,
 652             SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
 653             HAS_LITEETH => HAS_LITEETH,
 654             UART0_IS_16550 => UART0_IS_16550,
 655             HAS_UART1 => HAS_UART1
 656         )
 657         port map(
 658             clk => system_clk,
 659             rst => rst,
 660             wishbone_in => wb_syscon_in,
 661             wishbone_out => wb_syscon_out,
 662             dram_at_0 => dram_at_0,
 663             core_reset => do_core_reset,
 664             soc_reset => open -- XXX TODO
 665             );
 666
 667     --
 668     -- UART0
 669     --
 670     -- Either potato (legacy) or 16550
 671     --
 672     uart0_pp: if not UART0_IS_16550 generate
 673         uart0: entity work.pp_soc_uart
 674             generic map(
 675                 FIFO_DEPTH => 32
 676                 )
 677             port map(
 678                 clk => system_clk,
 679                 reset => rst_uart,
 680                 txd => uart0_txd,
 681                 rxd => uart0_rxd,
 682                 irq => uart0_irq,
 683                 wb_adr_in => wb_uart0_in.adr(11 downto 0),
 684                 wb_dat_in => wb_uart0_in.dat(7 downto 0),
 685                 wb_dat_out => uart0_dat8,
 686                 wb_cyc_in => wb_uart0_in.cyc,
 687                 wb_stb_in => wb_uart0_in.stb,
 688                 wb_we_in => wb_uart0_in.we,
 689                 wb_ack_out => wb_uart0_out.ack
 690                 );
 691     end generate;
 692
 693     uart0_16550 : if UART0_IS_16550 generate
 694         signal irq_l : std_ulogic;
 695     begin
 696         uart0: uart_top
 697             port map (
 698                 wb_clk_i   => system_clk,
 699                 wb_rst_i   => rst_uart,
 700                 wb_adr_i   => wb_uart0_in.adr(4 downto 2),
 701                 wb_dat_i   => wb_uart0_in.dat(7 downto 0),
 702                 wb_dat_o   => uart0_dat8,
 703                 wb_we_i    => wb_uart0_in.we,
 704                 wb_stb_i   => wb_uart0_in.stb,
 705                 wb_cyc_i   => wb_uart0_in.cyc,
 706                 wb_ack_o   => wb_uart0_out.ack,
 707                 int_o      => irq_l,
 708                 stx_pad_o  => uart0_txd,
 709                 srx_pad_i  => uart0_rxd,
 710                 rts_pad_o  => open,
 711                 cts_pad_i  => '1',
 712                 dtr_pad_o  => open,
 713                 dsr_pad_i  => '1',
 714                 ri_pad_i   => '0',
 715                 dcd_pad_i  => '1'
 716                 );
 717
 718         -- Add a register on the irq out, helps timing
 719         uart0_irq_latch: process(system_clk)
 720         begin
 721             if rising_edge(system_clk) then
 722                 uart0_irq <= irq_l;
 723             end if;
 724         end process;
 725     end generate;
 726
 727     wb_uart0_out.dat <= x"000000" & uart0_dat8;
 728     wb_uart0_out.stall <= not wb_uart0_out.ack;
 729
 730     --
 731     -- UART1
 732     --
 733     -- Always 16550 if it exists
 734     --
 735     uart1: if HAS_UART1 generate
 736         signal irq_l : std_ulogic;
 737     begin
 738         uart1: uart_top
 739             port map (
 740                 wb_clk_i   => system_clk,
 741                 wb_rst_i   => rst_uart,
 742                 wb_adr_i   => wb_uart1_in.adr(4 downto 2),
 743                 wb_dat_i   => wb_uart1_in.dat(7 downto 0),
 744                 wb_dat_o   => uart1_dat8,
 745                 wb_we_i    => wb_uart1_in.we,
 746                 wb_stb_i   => wb_uart1_in.stb,
 747                 wb_cyc_i   => wb_uart1_in.cyc,
 748                 wb_ack_o   => wb_uart1_out.ack,
 749                 int_o      => irq_l,
 750                 stx_pad_o  => uart1_txd,
 751                 srx_pad_i  => uart1_rxd,
 752                 rts_pad_o  => open,
 753                 cts_pad_i  => '1',
 754                 dtr_pad_o  => open,
 755                 dsr_pad_i  => '1',
 756                 ri_pad_i   => '0',
 757                 dcd_pad_i  => '1'
 758                 );
 759         -- Add a register on the irq out, helps timing
 760         uart0_irq_latch: process(system_clk)
 761         begin
 762             if rising_edge(system_clk) then
 763                 uart1_irq <= irq_l;
 764             end if;
 765         end process;
 766         wb_uart1_out.dat <= x"000000" & uart1_dat8;
 767         wb_uart1_out.stall <= not wb_uart1_out.ack;
 768     end generate;
 769
 770     no_uart1 : if not HAS_UART1 generate
 771         wb_uart1_out.dat <= x"00000000";
 772         wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
 773         wb_uart1_out.stall <= '0';
 774         uart1_irq <= '0';
 775     end generate;
 776
 777     spiflash_gen: if HAS_SPI_FLASH generate
 778         spiflash: entity work.spi_flash_ctrl
 779             generic map (
 780                 DATA_LINES    => SPI_FLASH_DLINES,
 781                 DEF_CLK_DIV   => SPI_FLASH_DEF_CKDV,
 782                 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD,
 783                 BOOT_CLOCKS   => SPI_BOOT_CLOCKS
 784                 )
 785             port map(
 786                 rst => rst_spi,
 787                 clk => system_clk,
 788                 wb_in => wb_spiflash_in,
 789                 wb_out => wb_spiflash_out,
 790                 wb_sel_reg => wb_spiflash_is_reg,
 791                 wb_sel_map => wb_spiflash_is_map,
 792                 sck => spi_flash_sck,
 793                 cs_n => spi_flash_cs_n,
 794                 sdat_o => spi_flash_sdat_o,
 795                 sdat_oe => spi_flash_sdat_oe,
 796                 sdat_i => spi_flash_sdat_i
 797                 );
 798     end generate;
 799
 800     no_spi0_gen: if not HAS_SPI_FLASH generate
 801         wb_spiflash_out.dat   <= (others => '1');
 802         wb_spiflash_out.ack   <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
 803         wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
 804     end generate;
 805
 806     xics_icp: entity work.xics_icp
 807         port map(
 808             clk => system_clk,
 809             rst => rst_xics,
 810             wb_in => wb_xics_icp_in,
 811             wb_out => wb_xics_icp_out,
 812             ics_in => ics_to_icp,
 813             core_irq_out => core_ext_irq
 814             );
 815
 816     xics_ics: entity work.xics_ics
 817         generic map(
 818             SRC_NUM   => 16,
 819             PRIO_BITS => 3
 820             )
 821         port map(
 822             clk => system_clk,
 823             rst => rst_xics,
 824             wb_in => wb_xics_ics_in,
 825             wb_out => wb_xics_ics_out,
 826             int_level_in => int_level_in,
 827             icp_out => ics_to_icp
 828             );
 829
 830     -- Assign external interrupts
 831     interrupts: process(all)
 832     begin
 833         int_level_in <= (others => '0');
 834         int_level_in(0) <= uart0_irq;
 835         int_level_in(1) <= ext_irq_eth;
 836         int_level_in(2) <= uart1_irq;
 837     end process;
 838
 839     -- BRAM Memory slave
 840     bram: if MEMORY_SIZE /= 0 generate
 841         bram0: entity work.wishbone_bram_wrapper
 842             generic map(
 843                 MEMORY_SIZE   => MEMORY_SIZE,
 844                 RAM_INIT_FILE => RAM_INIT_FILE
 845                 )
 846             port map(
 847                 clk => system_clk,
 848                 rst => rst_bram,
 849                 wishbone_in => wb_bram_in,
 850                 wishbone_out => wb_bram_out
 851                 );
 852     end generate;
 853
 854     no_bram: if MEMORY_SIZE = 0 generate
 855         wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
 856         wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
 857         wb_bram_out.stall <= not wb_bram_out.ack;
 858     end generate;
 859
 860     -- DMI(debug bus) <-> JTAG bridge
 861     dtm: entity work.dmi_dtm
 862         generic map(
 863             ABITS => 8,
 864             DBITS => 64
 865             )
 866         port map(
 867             sys_clk     => system_clk,
 868             sys_reset   => rst_dtm,
 869             dmi_addr    => dmi_addr,
 870             dmi_din     => dmi_din,
 871             dmi_dout    => dmi_dout,
 872             dmi_req     => dmi_req,
 873             dmi_wr      => dmi_wr,
 874             dmi_ack     => dmi_ack
 875             );
 876
 877     -- DMI interconnect
 878     dmi_intercon: process(dmi_addr, dmi_req,
 879                           dmi_wb_ack, dmi_wb_dout,
 880                           dmi_core_ack, dmi_core_dout)
 881
 882         -- DMI address map (each address is a full 64-bit register)
 883         --
 884         -- Offset:   Size:    Slave:
 885         --  0         4       Wishbone
 886         -- 10        16       Core
 887
 888         type slave_type is (SLAVE_WB,
 889                             SLAVE_CORE,
 890                             SLAVE_NONE);
 891         variable slave : slave_type;
 892     begin
 893         -- Simple address decoder
 894         slave := SLAVE_NONE;
 895         if std_match(dmi_addr, "000000--") then
 896             slave := SLAVE_WB;
 897         elsif std_match(dmi_addr, "0001----") then
 898             slave := SLAVE_CORE;
 899         end if;
 900
 901         -- DMI muxing
 902         dmi_wb_req <= '0';
 903         dmi_core_req <= '0';
 904         case slave is
 905         when SLAVE_WB =>
 906             dmi_wb_req <= dmi_req;
 907             dmi_ack <= dmi_wb_ack;
 908             dmi_din <= dmi_wb_dout;
 909         when SLAVE_CORE =>
 910             dmi_core_req <= dmi_req;
 911             dmi_ack <= dmi_core_ack;
 912             dmi_din <= dmi_core_dout;
 913         when others =>
 914             dmi_ack <= dmi_req;
 915             dmi_din <= (others => '1');
 916         end case;
 917
 918         -- SIM magic exit
 919         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
 920             stop;
 921         end if;
 922     end process;
 923
 924     -- Wishbone debug master (TODO: Add a DMI address decoder)
 925     wishbone_debug: entity work.wishbone_debug_master
 926         port map(clk => system_clk,
 927                  rst => rst_wbdb,
 928                  dmi_addr => dmi_addr(1 downto 0),
 929                  dmi_dout => dmi_wb_dout,
 930                  dmi_din => dmi_dout,
 931                  dmi_wr => dmi_wr,
 932                  dmi_ack => dmi_wb_ack,
 933                  dmi_req => dmi_wb_req,
 934                  wb_in => wishbone_debug_in,
 935                  wb_out => wishbone_debug_out);
 936
 937 --pragma synthesis_off
 938     wb_x_state: process(system_clk)
 939     begin
 940         if rising_edge(system_clk) then
 941             if not rst then
 942                 -- Wishbone arbiter
 943                 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
 944                 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
 945                 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
 946                 assert not(is_x(wb_masters_in(0).ack)) severity failure;
 947                 assert not(is_x(wb_masters_in(1).ack)) severity failure;
 948                 assert not(is_x(wb_masters_in(2).ack)) severity failure;
 949
 950                 -- Main memory wishbones
 951                 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
 952                 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
 953                 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
 954                 assert not(is_x(wb_bram_out.ack)) severity failure;
 955                 assert not(is_x(wb_dram_out.ack)) severity failure;
 956                 assert not(is_x(wb_io_out.ack)) severity failure;
 957
 958                 -- I/O wishbones
 959                 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
 960                 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
 961                 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
 962                 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
 963                 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
 964                 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
 965                 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
 966                 assert not(is_x(wb_uart0_out.ack)) severity failure;
 967                 assert not(is_x(wb_uart1_out.ack)) severity failure;
 968                 assert not(is_x(wb_spiflash_out.ack)) severity failure;
 969                 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
 970                 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
 971                 assert not(is_x(wb_ext_io_out.ack)) severity failure;
 972                 assert not(is_x(wb_syscon_out.ack)) severity failure;
 973             end if;
 974         end if;
 975     end process;
 976 --pragma synthesis_on
 977
 978 end architecture behaviour;