soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.math_real.all;
   4
   5 use std.textio.all;
   6
   7 library work;
   8 use work.common.all;
   9 use work.wishbone_types.all;
  10
  11
  12 -- 0x00000000: Main memory (1 MB)
  13 -- 0xc0002000: UART0 (for host communication)
  14 entity soc is
  15     generic (
  16         MEMORY_SIZE   : positive;
  17         RAM_INIT_FILE : string;
  18         RESET_LOW     : boolean;
  19         SIM           : boolean
  20         );
  21     port(
  22         rst          : in  std_ulogic;
  23         system_clk   : in  std_logic;
  24
  25         -- UART0 signals:
  26         uart0_txd    : out std_logic;
  27         uart0_rxd    : in  std_logic
  28         );
  29 end entity soc;
  30
  31 architecture behaviour of soc is
  32
  33     -- Wishbone master signals:
  34     signal wishbone_dcore_in : wishbone_slave_out;
  35     signal wishbone_dcore_out : wishbone_master_out;
  36     signal wishbone_icore_in : wishbone_slave_out;
  37     signal wishbone_icore_out : wishbone_master_out;
  38
  39     -- Wishbone master (output of arbiter):
  40     signal wb_master_in : wishbone_slave_out;
  41     signal wb_master_out : wishbone_master_out;
  42
  43     -- UART0 signals:
  44     signal wb_uart0_in   : wishbone_master_out;
  45     signal wb_uart0_out  : wishbone_slave_out;
  46     signal uart_dat8     : std_logic_vector(7 downto 0);
  47
  48     -- Main memory signals:
  49     signal wb_bram_in     : wishbone_master_out;
  50     signal wb_bram_out    : wishbone_slave_out;
  51     constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
  52
  53     -- Debug signals (used in SIM only)
  54     signal registers     : regfile;
  55     signal terminate     : std_ulogic;
  56
  57 begin
  58
  59     -- Processor core
  60     processor: entity work.core
  61         generic map(
  62             SIM => SIM
  63             )
  64         port map(
  65             clk => system_clk,
  66             rst => rst,
  67             wishbone_insn_in => wishbone_icore_in,
  68             wishbone_insn_out => wishbone_icore_out,
  69             wishbone_data_in => wishbone_dcore_in,
  70             wishbone_data_out => wishbone_dcore_out,
  71             registers => registers,
  72             terminate_out => terminate
  73             );
  74
  75     -- Wishbone bus master arbiter & mux
  76     wishbone_arbiter_0: entity work.wishbone_arbiter
  77         port map(
  78             clk => system_clk,
  79             rst => rst,
  80             wb1_in => wishbone_dcore_out,
  81             wb1_out => wishbone_dcore_in,
  82             wb2_in => wishbone_icore_out,
  83             wb2_out => wishbone_icore_in,
  84             wb_out => wb_master_out,
  85             wb_in => wb_master_in
  86             );
  87
  88     -- Wishbone slaves address decoder & mux
  89     slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
  90         -- Selected slave
  91         type slave_type is (SLAVE_UART,
  92                             SLAVE_MEMORY,
  93                             SLAVE_NONE);
  94         variable slave : slave_type;
  95     begin
  96         -- Simple address decoder
  97         slave := SLAVE_NONE;
  98         if wb_master_out.adr(63 downto 24) = x"0000000000" then
  99             slave := SLAVE_MEMORY;
 100         elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
 101             if wb_master_out.adr(15 downto 12) = x"2" then
 102                 slave := SLAVE_UART;
 103             end if;
 104         end if;
 105
 106         -- Wishbone muxing. Defaults:
 107         wb_bram_in <= wb_master_out;
 108         wb_bram_in.cyc  <= '0';
 109         wb_uart0_in <= wb_master_out;
 110         wb_uart0_in.cyc <= '0';
 111         case slave is
 112         when SLAVE_MEMORY =>
 113             wb_bram_in.cyc <= wb_master_out.cyc;
 114             wb_master_in <= wb_bram_out;
 115         when SLAVE_UART =>
 116             wb_uart0_in.cyc <= wb_master_out.cyc;
 117             wb_master_in <= wb_uart0_out;
 118         when others =>
 119             wb_master_in.dat <= (others => '1');
 120             wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
 121         end case;
 122     end process slave_intercon;
 123
 124     -- Simulated memory and UART
 125     sim_terminate_test: if SIM generate
 126
 127         -- Dump registers if core terminates
 128         dump_registers: process(all)
 129         begin
 130             if terminate = '1' then
 131                 loop_0: for i in 0 to 31 loop
 132                     report "REG " & to_hstring(registers(i));
 133                 end loop loop_0;
 134                 assert false report "end of test" severity failure;
 135             end if;
 136         end process;
 137
 138     end generate;
 139
 140     -- UART0 wishbone slave
 141     -- XXX FIXME: Need a proper wb64->wb8 adapter that
 142     --            converts SELs into low address bits and muxes
 143     --            data accordingly (either that or rejects large
 144     --            cycles).
 145     uart0: entity work.pp_soc_uart
 146         generic map(
 147             FIFO_DEPTH => 32
 148             )
 149         port map(
 150             clk => system_clk,
 151             reset => rst,
 152             txd => uart0_txd,
 153             rxd => uart0_rxd,
 154             wb_adr_in => wb_uart0_in.adr(11 downto 0),
 155             wb_dat_in => wb_uart0_in.dat(7 downto 0),
 156             wb_dat_out => uart_dat8,
 157             wb_cyc_in => wb_uart0_in.cyc,
 158             wb_stb_in => wb_uart0_in.stb,
 159             wb_we_in => wb_uart0_in.we,
 160             wb_ack_out => wb_uart0_out.ack
 161             );
 162     wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
 163
 164     -- BRAM Memory slave
 165     bram0: entity work.mw_soc_memory
 166         generic map(
 167             MEMORY_SIZE   => MEMORY_SIZE,
 168             RAM_INIT_FILE => RAM_INIT_FILE
 169             )
 170         port map(
 171             clk => system_clk,
 172             rst => rst,
 173             wishbone_in => wb_bram_in,
 174             wishbone_out => wb_bram_out
 175             );
 176
 177 end architecture behaviour;