soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- 0x00000000: Main memory (1 MB)
  14 -- 0xc0002000: UART0 (for host communication)
  15 entity soc is
  16     generic (
  17         MEMORY_SIZE   : positive;
  18         RAM_INIT_FILE : string;
  19         RESET_LOW     : boolean;
  20         SIM           : boolean;
  21         DISABLE_FLATTEN_CORE : boolean := false
  22         );
  23     port(
  24         rst          : in  std_ulogic;
  25         system_clk   : in  std_ulogic;
  26
  27         -- UART0 signals:
  28         uart0_txd    : out std_ulogic;
  29         uart0_rxd    : in  std_ulogic
  30         );
  31 end entity soc;
  32
  33 architecture behaviour of soc is
  34
  35     -- Wishbone master signals:
  36     signal wishbone_dcore_in : wishbone_slave_out;
  37     signal wishbone_dcore_out : wishbone_master_out;
  38     signal wishbone_icore_in : wishbone_slave_out;
  39     signal wishbone_icore_out : wishbone_master_out;
  40     signal wishbone_debug_in : wishbone_slave_out;
  41     signal wishbone_debug_out : wishbone_master_out;
  42
  43     -- Arbiter array (ghdl doesnt' support assigning the array
  44     -- elements in the entity instantiation)
  45     constant NUM_WB_MASTERS : positive := 3;
  46     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
  47     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
  48
  49     -- Wishbone master (output of arbiter):
  50     signal wb_master_in : wishbone_slave_out;
  51     signal wb_master_out : wishbone_master_out;
  52
  53     -- UART0 signals:
  54     signal wb_uart0_in   : wishbone_master_out;
  55     signal wb_uart0_out  : wishbone_slave_out;
  56     signal uart_dat8     : std_ulogic_vector(7 downto 0);
  57
  58     -- Main memory signals:
  59     signal wb_bram_in     : wishbone_master_out;
  60     signal wb_bram_out    : wishbone_slave_out;
  61     constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
  62
  63     -- DMI debug bus signals
  64     signal dmi_addr     : std_ulogic_vector(7 downto 0);
  65     signal dmi_din      : std_ulogic_vector(63 downto 0);
  66     signal dmi_dout     : std_ulogic_vector(63 downto 0);
  67     signal dmi_req      : std_ulogic;
  68     signal dmi_wr       : std_ulogic;
  69     signal dmi_ack      : std_ulogic;
  70
  71     -- Per slave DMI signals
  72     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
  73     signal dmi_wb_req   : std_ulogic;
  74     signal dmi_wb_ack   : std_ulogic;
  75     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
  76     signal dmi_core_req   : std_ulogic;
  77     signal dmi_core_ack   : std_ulogic;
  78 begin
  79
  80     -- Processor core
  81     processor: entity work.core
  82         generic map(
  83             SIM => SIM,
  84             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE
  85             )
  86         port map(
  87             clk => system_clk,
  88             rst => rst,
  89             wishbone_insn_in => wishbone_icore_in,
  90             wishbone_insn_out => wishbone_icore_out,
  91             wishbone_data_in => wishbone_dcore_in,
  92             wishbone_data_out => wishbone_dcore_out,
  93             dmi_addr => dmi_addr(3 downto 0),
  94             dmi_dout => dmi_core_dout,
  95             dmi_din => dmi_dout,
  96             dmi_wr => dmi_wr,
  97             dmi_ack => dmi_core_ack,
  98             dmi_req => dmi_core_req
  99             );
 100
 101     -- Wishbone bus master arbiter & mux
 102     wb_masters_out <= (0 => wishbone_dcore_out,
 103                        1 => wishbone_icore_out,
 104                        2 => wishbone_debug_out);
 105     wishbone_dcore_in <= wb_masters_in(0);
 106     wishbone_icore_in <= wb_masters_in(1);
 107     wishbone_debug_in <= wb_masters_in(2);
 108     wishbone_arbiter_0: entity work.wishbone_arbiter
 109         generic map(
 110             NUM_MASTERS => NUM_WB_MASTERS
 111             )
 112         port map(
 113             clk => system_clk, rst => rst,
 114             wb_masters_in => wb_masters_out,
 115             wb_masters_out => wb_masters_in,
 116             wb_slave_out => wb_master_out,
 117             wb_slave_in => wb_master_in
 118             );
 119
 120     -- Wishbone slaves address decoder & mux
 121     slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
 122         -- Selected slave
 123         type slave_type is (SLAVE_UART_0,
 124                             SLAVE_MEMORY,
 125                             SLAVE_NONE);
 126         variable slave : slave_type;
 127     begin
 128         -- Simple address decoder.
 129         slave := SLAVE_NONE;
 130         if wb_master_out.adr(31 downto 24) = x"00" then
 131             slave := SLAVE_MEMORY;
 132         elsif wb_master_out.adr(31 downto 24) = x"c0" then
 133             if wb_master_out.adr(23 downto 12) = x"002" then
 134                 slave := SLAVE_UART_0;
 135             end if;
 136         end if;
 137
 138         -- Wishbone muxing. Defaults:
 139         wb_bram_in <= wb_master_out;
 140         wb_bram_in.cyc  <= '0';
 141         wb_uart0_in <= wb_master_out;
 142         wb_uart0_in.cyc <= '0';
 143         case slave is
 144         when SLAVE_MEMORY =>
 145             wb_bram_in.cyc <= wb_master_out.cyc;
 146             wb_master_in <= wb_bram_out;
 147         when SLAVE_UART_0 =>
 148             wb_uart0_in.cyc <= wb_master_out.cyc;
 149             wb_master_in <= wb_uart0_out;
 150         when others =>
 151             wb_master_in.dat <= (others => '1');
 152             wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
 153             wb_master_in.stall <= '0';
 154         end case;
 155     end process slave_intercon;
 156
 157     -- Simulated memory and UART
 158
 159     -- UART0 wishbone slave
 160     -- XXX FIXME: Need a proper wb64->wb8 adapter that
 161     --            converts SELs into low address bits and muxes
 162     --            data accordingly (either that or rejects large
 163     --            cycles).
 164     uart0: entity work.pp_soc_uart
 165         generic map(
 166             FIFO_DEPTH => 32
 167             )
 168         port map(
 169             clk => system_clk,
 170             reset => rst,
 171             txd => uart0_txd,
 172             rxd => uart0_rxd,
 173             wb_adr_in => wb_uart0_in.adr(11 downto 0),
 174             wb_dat_in => wb_uart0_in.dat(7 downto 0),
 175             wb_dat_out => uart_dat8,
 176             wb_cyc_in => wb_uart0_in.cyc,
 177             wb_stb_in => wb_uart0_in.stb,
 178             wb_we_in => wb_uart0_in.we,
 179             wb_ack_out => wb_uart0_out.ack
 180             );
 181     wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
 182     wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
 183
 184     -- BRAM Memory slave
 185     bram0: entity work.wishbone_bram_wrapper
 186         generic map(
 187             MEMORY_SIZE   => MEMORY_SIZE,
 188             RAM_INIT_FILE => RAM_INIT_FILE
 189             )
 190         port map(
 191             clk => system_clk,
 192             rst => rst,
 193             wishbone_in => wb_bram_in,
 194             wishbone_out => wb_bram_out
 195             );
 196
 197     -- DMI(debug bus) <-> JTAG bridge
 198     dtm: entity work.dmi_dtm
 199         generic map(
 200             ABITS => 8,
 201             DBITS => 64
 202             )
 203         port map(
 204             sys_clk     => system_clk,
 205             sys_reset   => rst,
 206             dmi_addr    => dmi_addr,
 207             dmi_din     => dmi_din,
 208             dmi_dout    => dmi_dout,
 209             dmi_req     => dmi_req,
 210             dmi_wr      => dmi_wr,
 211             dmi_ack     => dmi_ack
 212             );
 213
 214     -- DMI interconnect
 215     dmi_intercon: process(dmi_addr, dmi_req,
 216                           dmi_wb_ack, dmi_wb_dout,
 217                           dmi_core_ack, dmi_core_dout)
 218
 219         -- DMI address map (each address is a full 64-bit register)
 220         --
 221         -- Offset:   Size:    Slave:
 222         --  0         4       Wishbone
 223         -- 10        16       Core
 224
 225         type slave_type is (SLAVE_WB,
 226                             SLAVE_CORE,
 227                             SLAVE_NONE);
 228         variable slave : slave_type;
 229     begin
 230         -- Simple address decoder
 231         slave := SLAVE_NONE;
 232         if std_match(dmi_addr, "000000--") then
 233             slave := SLAVE_WB;
 234         elsif std_match(dmi_addr, "0001----") then
 235             slave := SLAVE_CORE;
 236         end if;
 237
 238         -- DMI muxing
 239         dmi_wb_req <= '0';
 240         dmi_core_req <= '0';
 241         case slave is
 242         when SLAVE_WB =>
 243             dmi_wb_req <= dmi_req;
 244             dmi_ack <= dmi_wb_ack;
 245             dmi_din <= dmi_wb_dout;
 246         when SLAVE_CORE =>
 247             dmi_core_req <= dmi_req;
 248             dmi_ack <= dmi_core_ack;
 249             dmi_din <= dmi_core_dout;
 250         when others =>
 251             dmi_ack <= dmi_req;
 252             dmi_din <= (others => '1');
 253         end case;
 254
 255         -- SIM magic exit
 256         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
 257             stop;
 258         end if;
 259     end process;
 260
 261     -- Wishbone debug master (TODO: Add a DMI address decoder)
 262     wishbone_debug: entity work.wishbone_debug_master
 263         port map(clk => system_clk, rst => rst,
 264                  dmi_addr => dmi_addr(1 downto 0),
 265                  dmi_dout => dmi_wb_dout,
 266                  dmi_din => dmi_dout,
 267                  dmi_wr => dmi_wr,
 268                  dmi_ack => dmi_wb_ack,
 269                  dmi_req => dmi_wb_req,
 270                  wb_in => wishbone_debug_in,
 271                  wb_out => wishbone_debug_out);
 272
 273
 274 end architecture behaviour;