2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
10 use work.wishbone_types.all;
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
23 -- 0xc0004000: XICS ICP
24 -- 0xc0005000: XICS ICS
25 -- 0xc0006000: SPI Flash controller
26 -- 0xc8nnnnnn: External IO bus
27 -- 0xf0000000: Flash "ROM" mapping
28 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
31 -- 0xc8000000: LiteDRAM control (CSRs)
33 -- (**) DRAM init code is currently special and goes to the external
34 -- IO bus, this will be fixed when it's moved out of litedram and
35 -- into the main SoC once we have a common "firmware".
43 MEMORY_SIZE : natural;
44 RAM_INIT_FILE : string;
47 DISABLE_FLATTEN_CORE : boolean := false;
48 HAS_DRAM : boolean := false;
49 DRAM_SIZE : integer := 0;
50 DRAM_INIT_SIZE : integer := 0;
51 HAS_SPI_FLASH : boolean := false;
52 SPI_FLASH_DLINES : positive := 1;
53 SPI_FLASH_OFFSET : integer := 0;
54 SPI_FLASH_DEF_CKDV : natural := 2;
55 SPI_FLASH_DEF_QUAD : boolean := false;
56 LOG_LENGTH : natural := 512
60 system_clk : in std_ulogic;
62 -- "Large" (64-bit) DRAM wishbone
63 wb_dram_in : out wishbone_master_out;
64 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
66 -- "Small" (32-bit) external IO wishbone
67 wb_ext_io_in : out wb_io_master_out;
68 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
69 wb_ext_is_dram_csr : out std_ulogic;
70 wb_ext_is_dram_init : out std_ulogic;
73 uart0_txd : out std_ulogic;
74 uart0_rxd : in std_ulogic := '0';
77 spi_flash_sck : out std_ulogic;
78 spi_flash_cs_n : out std_ulogic;
79 spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
80 spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
81 spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
83 -- DRAM controller signals
84 alt_reset : in std_ulogic := '0'
88 architecture behaviour of soc is
90 -- Wishbone master signals:
91 signal wishbone_dcore_in : wishbone_slave_out;
92 signal wishbone_dcore_out : wishbone_master_out;
93 signal wishbone_icore_in : wishbone_slave_out;
94 signal wishbone_icore_out : wishbone_master_out;
95 signal wishbone_debug_in : wishbone_slave_out;
96 signal wishbone_debug_out : wishbone_master_out;
98 -- Arbiter array (ghdl doesnt' support assigning the array
99 -- elements in the entity instantiation)
100 constant NUM_WB_MASTERS : positive := 3;
101 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
102 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
104 -- Wishbone master (output of arbiter):
105 signal wb_master_in : wishbone_slave_out;
106 signal wb_master_out : wishbone_master_out;
108 -- Main "IO" bus, from main slave decoder to the latch
109 signal wb_io_in : wishbone_master_out;
110 signal wb_io_out : wishbone_slave_out;
112 -- Secondary (smaller) IO bus after the IO bus latch
113 signal wb_sio_out : wb_io_master_out;
114 signal wb_sio_in : wb_io_slave_out;
117 signal dram_at_0 : std_ulogic;
118 signal do_core_reset : std_ulogic;
119 signal wb_syscon_in : wb_io_master_out;
120 signal wb_syscon_out : wb_io_slave_out;
123 signal wb_uart0_in : wb_io_master_out;
124 signal wb_uart0_out : wb_io_slave_out;
125 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
126 signal uart0_irq : std_ulogic;
128 -- SPI Flash controller signals:
129 signal wb_spiflash_in : wb_io_master_out;
130 signal wb_spiflash_out : wb_io_slave_out;
131 signal wb_spiflash_is_reg : std_ulogic;
132 signal wb_spiflash_is_map : std_ulogic;
135 signal wb_xics_icp_in : wb_io_master_out;
136 signal wb_xics_icp_out : wb_io_slave_out;
137 signal wb_xics_ics_in : wb_io_master_out;
138 signal wb_xics_ics_out : wb_io_slave_out;
139 signal int_level_in : std_ulogic_vector(15 downto 0);
140 signal ics_to_icp : ics_to_icp_t;
141 signal core_ext_irq : std_ulogic;
143 -- Main memory signals:
144 signal wb_bram_in : wishbone_master_out;
145 signal wb_bram_out : wishbone_slave_out;
147 -- DMI debug bus signals
148 signal dmi_addr : std_ulogic_vector(7 downto 0);
149 signal dmi_din : std_ulogic_vector(63 downto 0);
150 signal dmi_dout : std_ulogic_vector(63 downto 0);
151 signal dmi_req : std_ulogic;
152 signal dmi_wr : std_ulogic;
153 signal dmi_ack : std_ulogic;
155 -- Per slave DMI signals
156 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
157 signal dmi_wb_req : std_ulogic;
158 signal dmi_wb_ack : std_ulogic;
159 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
160 signal dmi_core_req : std_ulogic;
161 signal dmi_core_ack : std_ulogic;
163 -- Delayed/latched resets and alt_reset
164 signal rst_core : std_ulogic := '1';
165 signal rst_uart : std_ulogic := '1';
166 signal rst_xics : std_ulogic := '1';
167 signal rst_spi : std_ulogic := '1';
168 signal rst_bram : std_ulogic := '1';
169 signal rst_dtm : std_ulogic := '1';
170 signal rst_wbar : std_ulogic := '1';
171 signal rst_wbdb : std_ulogic := '1';
172 signal alt_reset_d : std_ulogic;
175 type slave_io_type is (SLAVE_IO_SYSCON,
179 SLAVE_IO_SPI_FLASH_REG,
180 SLAVE_IO_SPI_FLASH_MAP,
183 signal slave_io_dbg : slave_io_type;
186 resets: process(system_clk)
188 if rising_edge(system_clk) then
189 rst_core <= rst or do_core_reset;
197 alt_reset_d <= alt_reset;
202 processor: entity work.core
205 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
206 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
207 LOG_LENGTH => LOG_LENGTH
212 alt_reset => alt_reset_d,
213 wishbone_insn_in => wishbone_icore_in,
214 wishbone_insn_out => wishbone_icore_out,
215 wishbone_data_in => wishbone_dcore_in,
216 wishbone_data_out => wishbone_dcore_out,
217 dmi_addr => dmi_addr(3 downto 0),
218 dmi_dout => dmi_core_dout,
221 dmi_ack => dmi_core_ack,
222 dmi_req => dmi_core_req,
223 ext_irq => core_ext_irq
226 -- Wishbone bus master arbiter & mux
227 wb_masters_out <= (0 => wishbone_dcore_out,
228 1 => wishbone_icore_out,
229 2 => wishbone_debug_out);
230 wishbone_dcore_in <= wb_masters_in(0);
231 wishbone_icore_in <= wb_masters_in(1);
232 wishbone_debug_in <= wb_masters_in(2);
233 wishbone_arbiter_0: entity work.wishbone_arbiter
235 NUM_MASTERS => NUM_WB_MASTERS
240 wb_masters_in => wb_masters_out,
241 wb_masters_out => wb_masters_in,
242 wb_slave_out => wb_master_out,
243 wb_slave_in => wb_master_in
246 -- Top level Wishbone slaves address decoder & mux
248 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
255 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
256 type slave_top_type is (SLAVE_TOP_BRAM,
259 variable slave_top : slave_top_type;
260 variable top_decode : std_ulogic_vector(3 downto 0);
262 -- Top-level address decoder
263 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
264 slave_top := SLAVE_TOP_BRAM;
265 if std_match(top_decode, "0000") then
266 slave_top := SLAVE_TOP_BRAM;
267 elsif std_match(top_decode, "0001") then
268 slave_top := SLAVE_TOP_DRAM;
269 elsif std_match(top_decode, "01--") then
270 slave_top := SLAVE_TOP_DRAM;
271 elsif std_match(top_decode, "10--") then
272 slave_top := SLAVE_TOP_BRAM;
273 elsif std_match(top_decode, "11--") then
274 slave_top := SLAVE_TOP_IO;
277 -- Top level wishbone muxing.
278 wb_bram_in <= wb_master_out;
279 wb_bram_in.cyc <= '0';
280 wb_dram_in <= wb_master_out;
281 wb_dram_in.cyc <= '0';
282 wb_io_in <= wb_master_out;
285 when SLAVE_TOP_BRAM =>
286 wb_bram_in.cyc <= wb_master_out.cyc;
287 wb_master_in <= wb_bram_out;
288 when SLAVE_TOP_DRAM =>
290 wb_dram_in.cyc <= wb_master_out.cyc;
291 wb_master_in <= wb_dram_out;
293 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
294 wb_master_in.dat <= (others => '1');
295 wb_master_in.stall <= '0';
298 wb_io_in.cyc <= wb_master_out.cyc;
299 wb_master_in <= wb_io_out;
301 end process slave_top_intercon;
303 -- IO wishbone slave 64->32 bits converter
305 -- For timing reasons, this adds a one cycle latch on the way both
306 -- in and out. This relaxes timing and routing pressure on the "main"
307 -- memory bus by moving all simple IOs to a slower 32-bit bus.
309 -- This implementation is rather dumb at the moment, no stash buffer,
310 -- so we stall whenever that latch is busy. This can be improved.
312 slave_io_latch: process(system_clk)
314 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
315 variable state : state_t;
318 variable has_top : boolean;
319 variable has_bot : boolean;
321 if rising_edge(system_clk) then
324 wb_io_out.ack <= '0';
325 wb_io_out.stall <= '0';
326 wb_sio_out.cyc <= '0';
327 wb_sio_out.stb <= '0';
333 -- Clear ACK in case it was set
334 wb_io_out.ack <= '0';
336 -- Do we have a cycle ?
337 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
338 -- Stall master until we are done, we are't (yet) pipelining
339 -- this, it's all slow IOs.
340 wb_io_out.stall <= '1';
342 -- Start cycle downstream
343 wb_sio_out.cyc <= '1';
344 wb_sio_out.stb <= '1';
346 -- Copy write enable to IO out, copy address as well
347 wb_sio_out.we <= wb_io_in.we;
348 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
350 -- Do we have a top word and/or a bottom word ?
351 has_top := wb_io_in.sel(7 downto 4) /= "0000";
352 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
354 -- If we have a bottom word, handle it first, otherwise
355 -- send the top word down. XXX Split the actual mux out
356 -- and only generate a control signal.
358 if wb_io_in.we = '1' then
359 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
361 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
364 state := WAIT_ACK_BOT;
366 if wb_io_in.we = '1' then
367 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
369 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
372 wb_sio_out.adr(2) <= '1';
375 state := WAIT_ACK_TOP;
379 -- If we aren't stalled by the device, clear stb
380 if wb_sio_in.stall = '0' then
381 wb_sio_out.stb <= '0';
385 if wb_sio_in.ack = '1' then
386 -- If it's a read, latch the data
387 if wb_sio_out.we = '0' then
388 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
391 -- Do we have a "top" part as well ?
394 if wb_io_in.we = '1' then
395 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
397 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
399 -- Bump address and set STB
400 wb_sio_out.adr(2) <= '1';
401 wb_sio_out.stb <= '1';
404 state := WAIT_ACK_TOP;
406 -- We are done, ack up, clear cyc downstram
407 wb_sio_out.cyc <= '0';
409 -- And ack & unstall upstream
410 wb_io_out.ack <= '1';
411 wb_io_out.stall <= '0';
418 -- If we aren't stalled by the device, clear stb
419 if wb_sio_in.stall = '0' then
420 wb_sio_out.stb <= '0';
424 if wb_sio_in.ack = '1' then
425 -- If it's a read, latch the data
426 if wb_sio_out.we = '0' then
427 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
430 -- We are done, ack up, clear cyc downstram
431 wb_sio_out.cyc <= '0';
433 -- And ack & unstall upstream
434 wb_io_out.ack <= '1';
435 wb_io_out.stall <= '0';
445 -- IO wishbone slave intercon.
447 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out,
448 wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
450 variable slave_io : slave_io_type;
452 variable match : std_ulogic_vector(31 downto 12);
453 variable ext_valid : boolean;
456 -- Simple address decoder.
457 slave_io := SLAVE_IO_NONE;
458 match := "11" & wb_sio_out.adr(29 downto 12);
459 if std_match(match, x"FF---") and HAS_DRAM then
460 slave_io := SLAVE_IO_EXTERNAL;
461 elsif std_match(match, x"F----") then
462 slave_io := SLAVE_IO_SPI_FLASH_MAP;
463 elsif std_match(match, x"C0000") then
464 slave_io := SLAVE_IO_SYSCON;
465 elsif std_match(match, x"C0002") then
466 slave_io := SLAVE_IO_UART;
467 elsif std_match(match, x"C8---") then
468 slave_io := SLAVE_IO_EXTERNAL;
469 elsif std_match(match, x"C0004") then
470 slave_io := SLAVE_IO_ICP;
471 elsif std_match(match, x"C0005") then
472 slave_io := SLAVE_IO_ICS;
473 elsif std_match(match, x"C0006") then
474 slave_io := SLAVE_IO_SPI_FLASH_REG;
476 slave_io_dbg <= slave_io;
477 wb_uart0_in <= wb_sio_out;
478 wb_uart0_in.cyc <= '0';
479 wb_spiflash_in <= wb_sio_out;
480 wb_spiflash_in.cyc <= '0';
481 wb_spiflash_is_reg <= '0';
482 wb_spiflash_is_map <= '0';
484 -- Only give xics 8 bits of wb addr (for now...)
485 wb_xics_icp_in <= wb_sio_out;
486 wb_xics_icp_in.adr <= (others => '0');
487 wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
488 wb_xics_icp_in.cyc <= '0';
489 wb_xics_ics_in <= wb_sio_out;
490 wb_xics_ics_in.adr <= (others => '0');
491 wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
492 wb_xics_ics_in.cyc <= '0';
494 wb_ext_io_in <= wb_sio_out;
495 wb_ext_io_in.cyc <= '0';
497 wb_syscon_in <= wb_sio_out;
498 wb_syscon_in.cyc <= '0';
500 wb_ext_is_dram_csr <= '0';
501 wb_ext_is_dram_init <= '0';
503 -- Default response, ack & return all 1's
504 wb_sio_in.dat <= (others => '1');
505 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
506 wb_sio_in.stall <= '0';
509 when SLAVE_IO_EXTERNAL =>
510 -- Ext IO "chip selects"
512 -- DRAM init is special at 0xFF* so we just test the top
513 -- bit. Everything else is at 0xC8* so we test only bits
517 if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
518 wb_ext_is_dram_init <= '1';
520 elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
521 wb_ext_is_dram_csr <= '1';
525 wb_ext_io_in.cyc <= wb_sio_out.cyc;
526 wb_sio_in <= wb_ext_io_out;
529 when SLAVE_IO_SYSCON =>
530 wb_syscon_in.cyc <= wb_sio_out.cyc;
531 wb_sio_in <= wb_syscon_out;
532 when SLAVE_IO_UART =>
533 wb_uart0_in.cyc <= wb_sio_out.cyc;
534 wb_sio_in <= wb_uart0_out;
536 wb_xics_icp_in.cyc <= wb_sio_out.cyc;
537 wb_sio_in <= wb_xics_icp_out;
539 wb_xics_ics_in.cyc <= wb_sio_out.cyc;
540 wb_sio_in <= wb_xics_ics_out;
541 when SLAVE_IO_SPI_FLASH_MAP =>
542 -- Clear top bits so they don't make their way to the
544 wb_spiflash_in.adr(29 downto 28) <= "00";
545 wb_spiflash_in.cyc <= wb_sio_out.cyc;
546 wb_sio_in <= wb_spiflash_out;
547 wb_spiflash_is_map <= '1';
548 when SLAVE_IO_SPI_FLASH_REG =>
549 wb_spiflash_in.cyc <= wb_sio_out.cyc;
550 wb_sio_in <= wb_spiflash_out;
551 wb_spiflash_is_reg <= '1';
558 syscon0: entity work.syscon
561 HAS_DRAM => HAS_DRAM,
562 BRAM_SIZE => MEMORY_SIZE,
563 DRAM_SIZE => DRAM_SIZE,
564 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
565 CLK_FREQ => CLK_FREQ,
566 HAS_SPI_FLASH => HAS_SPI_FLASH,
567 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET
572 wishbone_in => wb_syscon_in,
573 wishbone_out => wb_syscon_out,
574 dram_at_0 => dram_at_0,
575 core_reset => do_core_reset,
576 soc_reset => open -- XXX TODO
579 -- Simulated memory and UART
581 -- UART0 wishbone slave
582 uart0: entity work.pp_soc_uart
592 wb_adr_in => wb_uart0_in.adr(11 downto 0),
593 wb_dat_in => wb_uart0_in.dat(7 downto 0),
594 wb_dat_out => uart0_dat8,
595 wb_cyc_in => wb_uart0_in.cyc,
596 wb_stb_in => wb_uart0_in.stb,
597 wb_we_in => wb_uart0_in.we,
598 wb_ack_out => wb_uart0_out.ack
600 wb_uart0_out.dat <= x"000000" & uart0_dat8;
601 wb_uart0_out.stall <= not wb_uart0_out.ack;
603 spiflash_gen: if HAS_SPI_FLASH generate
604 spiflash: entity work.spi_flash_ctrl
606 DATA_LINES => SPI_FLASH_DLINES,
607 DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
608 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
613 wb_in => wb_spiflash_in,
614 wb_out => wb_spiflash_out,
615 wb_sel_reg => wb_spiflash_is_reg,
616 wb_sel_map => wb_spiflash_is_map,
617 sck => spi_flash_sck,
618 cs_n => spi_flash_cs_n,
619 sdat_o => spi_flash_sdat_o,
620 sdat_oe => spi_flash_sdat_oe,
621 sdat_i => spi_flash_sdat_i
625 no_spi0_gen: if not HAS_SPI_FLASH generate
626 wb_spiflash_out.dat <= (others => '1');
627 wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
628 wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
631 xics_icp: entity work.xics_icp
635 wb_in => wb_xics_icp_in,
636 wb_out => wb_xics_icp_out,
637 ics_in => ics_to_icp,
638 core_irq_out => core_ext_irq
641 xics_ics: entity work.xics_ics
648 wb_in => wb_xics_ics_in,
649 wb_out => wb_xics_ics_out,
650 int_level_in => int_level_in,
651 icp_out => ics_to_icp
654 -- Assign external interrupts
655 interrupts: process(all)
657 int_level_in <= (others => '0');
658 int_level_in(0) <= uart0_irq;
662 bram: if MEMORY_SIZE /= 0 generate
663 bram0: entity work.wishbone_bram_wrapper
665 MEMORY_SIZE => MEMORY_SIZE,
666 RAM_INIT_FILE => RAM_INIT_FILE
671 wishbone_in => wb_bram_in,
672 wishbone_out => wb_bram_out
676 no_bram: if MEMORY_SIZE = 0 generate
677 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
678 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
679 wb_bram_out.stall <= not wb_bram_out.ack;
682 -- DMI(debug bus) <-> JTAG bridge
683 dtm: entity work.dmi_dtm
689 sys_clk => system_clk,
690 sys_reset => rst_dtm,
691 dmi_addr => dmi_addr,
693 dmi_dout => dmi_dout,
700 dmi_intercon: process(dmi_addr, dmi_req,
701 dmi_wb_ack, dmi_wb_dout,
702 dmi_core_ack, dmi_core_dout)
704 -- DMI address map (each address is a full 64-bit register)
706 -- Offset: Size: Slave:
710 type slave_type is (SLAVE_WB,
713 variable slave : slave_type;
715 -- Simple address decoder
717 if std_match(dmi_addr, "000000--") then
719 elsif std_match(dmi_addr, "0001----") then
728 dmi_wb_req <= dmi_req;
729 dmi_ack <= dmi_wb_ack;
730 dmi_din <= dmi_wb_dout;
732 dmi_core_req <= dmi_req;
733 dmi_ack <= dmi_core_ack;
734 dmi_din <= dmi_core_dout;
737 dmi_din <= (others => '1');
741 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
746 -- Wishbone debug master (TODO: Add a DMI address decoder)
747 wishbone_debug: entity work.wishbone_debug_master
748 port map(clk => system_clk,
750 dmi_addr => dmi_addr(1 downto 0),
751 dmi_dout => dmi_wb_dout,
754 dmi_ack => dmi_wb_ack,
755 dmi_req => dmi_wb_req,
756 wb_in => wishbone_debug_in,
757 wb_out => wishbone_debug_out);
760 end architecture behaviour;