2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
10 use work.wishbone_types.all;
15 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
16 -- 0x40000000: DRAM (when present)
19 -- 0xc0004000: XICS ICP
20 -- 0xc0100000: LiteDRAM control (CSRs)
21 -- 0xf0000000: Block RAM (aliased & repeated)
22 -- 0xffff0000: DRAM init code (if any)
26 MEMORY_SIZE : positive;
27 RAM_INIT_FILE : string;
31 DISABLE_FLATTEN_CORE : boolean := false;
32 HAS_DRAM : boolean := false;
33 DRAM_SIZE : integer := 0
37 system_clk : in std_ulogic;
39 -- DRAM controller signals
40 wb_dram_in : out wishbone_master_out;
41 wb_dram_out : in wishbone_slave_out;
42 wb_dram_ctrl : out std_ulogic;
43 wb_dram_init : out std_ulogic;
46 uart0_txd : out std_ulogic;
47 uart0_rxd : in std_ulogic;
49 -- DRAM controller signals
50 alt_reset : in std_ulogic
54 architecture behaviour of soc is
56 -- Wishbone master signals:
57 signal wishbone_dcore_in : wishbone_slave_out;
58 signal wishbone_dcore_out : wishbone_master_out;
59 signal wishbone_icore_in : wishbone_slave_out;
60 signal wishbone_icore_out : wishbone_master_out;
61 signal wishbone_debug_in : wishbone_slave_out;
62 signal wishbone_debug_out : wishbone_master_out;
64 -- Arbiter array (ghdl doesnt' support assigning the array
65 -- elements in the entity instantiation)
66 constant NUM_WB_MASTERS : positive := 3;
67 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
68 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
70 -- Wishbone master (output of arbiter):
71 signal wb_master_in : wishbone_slave_out;
72 signal wb_master_out : wishbone_master_out;
75 signal dram_at_0 : std_ulogic;
76 signal do_core_reset : std_ulogic;
77 signal wb_syscon_in : wishbone_master_out;
78 signal wb_syscon_out : wishbone_slave_out;
81 signal wb_uart0_in : wishbone_master_out;
82 signal wb_uart0_out : wishbone_slave_out;
83 signal uart_dat8 : std_ulogic_vector(7 downto 0);
86 signal wb_xics0_in : wishbone_master_out;
87 signal wb_xics0_out : wishbone_slave_out;
88 signal int_level_in : std_ulogic_vector(15 downto 0);
90 signal xics_to_execute1 : XicsToExecute1Type;
92 -- Main memory signals:
93 signal wb_bram_in : wishbone_master_out;
94 signal wb_bram_out : wishbone_slave_out;
95 constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
97 -- DMI debug bus signals
98 signal dmi_addr : std_ulogic_vector(7 downto 0);
99 signal dmi_din : std_ulogic_vector(63 downto 0);
100 signal dmi_dout : std_ulogic_vector(63 downto 0);
101 signal dmi_req : std_ulogic;
102 signal dmi_wr : std_ulogic;
103 signal dmi_ack : std_ulogic;
105 -- Per slave DMI signals
106 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
107 signal dmi_wb_req : std_ulogic;
108 signal dmi_wb_ack : std_ulogic;
109 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
110 signal dmi_core_req : std_ulogic;
111 signal dmi_core_ack : std_ulogic;
113 -- Delayed/latched resets and alt_reset
114 signal rst_core : std_ulogic := '1';
115 signal rst_uart : std_ulogic := '1';
116 signal rst_xics : std_ulogic := '1';
117 signal rst_bram : std_ulogic := '1';
118 signal rst_dtm : std_ulogic := '1';
119 signal rst_wbar : std_ulogic := '1';
120 signal rst_wbdb : std_ulogic := '1';
121 signal alt_reset_d : std_ulogic;
125 resets: process(system_clk)
127 if rising_edge(system_clk) then
128 rst_core <= rst or do_core_reset;
135 alt_reset_d <= alt_reset;
140 processor: entity work.core
143 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
144 ALT_RESET_ADDRESS => (15 downto 0 => '0', others => '1')
149 alt_reset => alt_reset_d,
150 wishbone_insn_in => wishbone_icore_in,
151 wishbone_insn_out => wishbone_icore_out,
152 wishbone_data_in => wishbone_dcore_in,
153 wishbone_data_out => wishbone_dcore_out,
154 dmi_addr => dmi_addr(3 downto 0),
155 dmi_dout => dmi_core_dout,
158 dmi_ack => dmi_core_ack,
159 dmi_req => dmi_core_req,
160 xics_in => xics_to_execute1
163 -- Wishbone bus master arbiter & mux
164 wb_masters_out <= (0 => wishbone_dcore_out,
165 1 => wishbone_icore_out,
166 2 => wishbone_debug_out);
167 wishbone_dcore_in <= wb_masters_in(0);
168 wishbone_icore_in <= wb_masters_in(1);
169 wishbone_debug_in <= wb_masters_in(2);
170 wishbone_arbiter_0: entity work.wishbone_arbiter
172 NUM_MASTERS => NUM_WB_MASTERS
177 wb_masters_in => wb_masters_out,
178 wb_masters_out => wb_masters_in,
179 wb_slave_out => wb_master_out,
180 wb_slave_in => wb_master_in
183 -- Wishbone slaves address decoder & mux
184 slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out, wb_dram_out, wb_syscon_out)
186 type slave_type is (SLAVE_SYSCON,
194 variable slave : slave_type;
196 -- Simple address decoder.
198 -- Simple address decoder. Ignore top bits to save silicon for now
200 if std_match(wb_master_out.adr, x"0-------") then
201 slave := SLAVE_DRAM when HAS_DRAM and dram_at_0 = '1' else
203 elsif std_match(wb_master_out.adr, x"FFFF----") then
204 slave := SLAVE_DRAM_INIT;
205 elsif std_match(wb_master_out.adr, x"F-------") then
207 elsif std_match(wb_master_out.adr, x"4-------") and HAS_DRAM then
209 elsif std_match(wb_master_out.adr, x"C0000---") then
210 slave := SLAVE_SYSCON;
211 elsif std_match(wb_master_out.adr, x"C0002---") then
213 elsif std_match(wb_master_out.adr, x"C01-----") then
214 slave := SLAVE_DRAM_CTRL;
215 elsif std_match(wb_master_out.adr, x"C0004---") then
216 slave := SLAVE_ICP_0;
219 -- Wishbone muxing. Defaults:
220 wb_bram_in <= wb_master_out;
221 wb_bram_in.cyc <= '0';
222 wb_uart0_in <= wb_master_out;
223 wb_uart0_in.cyc <= '0';
225 -- Only give xics 8 bits of wb addr
226 wb_xics0_in <= wb_master_out;
227 wb_xics0_in.adr <= (others => '0');
228 wb_xics0_in.adr(7 downto 0) <= wb_master_out.adr(7 downto 0);
229 wb_xics0_in.cyc <= '0';
231 wb_dram_in <= wb_master_out;
232 wb_dram_in.cyc <= '0';
235 wb_syscon_in <= wb_master_out;
236 wb_syscon_in.cyc <= '0';
239 wb_bram_in.cyc <= wb_master_out.cyc;
240 wb_master_in <= wb_bram_out;
242 wb_dram_in.cyc <= wb_master_out.cyc;
243 wb_master_in <= wb_dram_out;
244 when SLAVE_DRAM_INIT =>
245 wb_dram_in.cyc <= wb_master_out.cyc;
246 wb_master_in <= wb_dram_out;
248 when SLAVE_DRAM_CTRL =>
249 wb_dram_in.cyc <= wb_master_out.cyc;
250 wb_master_in <= wb_dram_out;
253 wb_syscon_in.cyc <= wb_master_out.cyc;
254 wb_master_in <= wb_syscon_out;
256 wb_uart0_in.cyc <= wb_master_out.cyc;
257 wb_master_in <= wb_uart0_out;
259 wb_xics0_in.cyc <= wb_master_out.cyc;
260 wb_master_in <= wb_xics0_out;
262 wb_master_in.dat <= (others => '1');
263 wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
264 wb_master_in.stall <= '0';
266 end process slave_intercon;
269 syscon0: entity work.syscon
272 HAS_DRAM => HAS_DRAM,
273 BRAM_SIZE => MEMORY_SIZE,
274 DRAM_SIZE => DRAM_SIZE,
280 wishbone_in => wb_syscon_in,
281 wishbone_out => wb_syscon_out,
282 dram_at_0 => dram_at_0,
283 core_reset => do_core_reset,
284 soc_reset => open -- XXX TODO
287 -- Simulated memory and UART
289 -- UART0 wishbone slave
290 -- XXX FIXME: Need a proper wb64->wb8 adapter that
291 -- converts SELs into low address bits and muxes
292 -- data accordingly (either that or rejects large
294 uart0: entity work.pp_soc_uart
303 irq => int_level_in(0),
304 wb_adr_in => wb_uart0_in.adr(11 downto 0),
305 wb_dat_in => wb_uart0_in.dat(7 downto 0),
306 wb_dat_out => uart_dat8,
307 wb_cyc_in => wb_uart0_in.cyc,
308 wb_stb_in => wb_uart0_in.stb,
309 wb_we_in => wb_uart0_in.we,
310 wb_ack_out => wb_uart0_out.ack
312 wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
313 wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
315 xics0: entity work.xics
322 wb_in => wb_xics0_in,
323 wb_out => wb_xics0_out,
324 int_level_in => int_level_in,
325 e_out => xics_to_execute1
329 bram0: entity work.wishbone_bram_wrapper
331 MEMORY_SIZE => MEMORY_SIZE,
332 RAM_INIT_FILE => RAM_INIT_FILE
337 wishbone_in => wb_bram_in,
338 wishbone_out => wb_bram_out
341 -- DMI(debug bus) <-> JTAG bridge
342 dtm: entity work.dmi_dtm
348 sys_clk => system_clk,
349 sys_reset => rst_dtm,
350 dmi_addr => dmi_addr,
352 dmi_dout => dmi_dout,
359 dmi_intercon: process(dmi_addr, dmi_req,
360 dmi_wb_ack, dmi_wb_dout,
361 dmi_core_ack, dmi_core_dout)
363 -- DMI address map (each address is a full 64-bit register)
365 -- Offset: Size: Slave:
369 type slave_type is (SLAVE_WB,
372 variable slave : slave_type;
374 -- Simple address decoder
376 if std_match(dmi_addr, "000000--") then
378 elsif std_match(dmi_addr, "0001----") then
387 dmi_wb_req <= dmi_req;
388 dmi_ack <= dmi_wb_ack;
389 dmi_din <= dmi_wb_dout;
391 dmi_core_req <= dmi_req;
392 dmi_ack <= dmi_core_ack;
393 dmi_din <= dmi_core_dout;
396 dmi_din <= (others => '1');
400 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
405 -- Wishbone debug master (TODO: Add a DMI address decoder)
406 wishbone_debug: entity work.wishbone_debug_master
407 port map(clk => system_clk,
409 dmi_addr => dmi_addr(1 downto 0),
410 dmi_dout => dmi_wb_dout,
413 dmi_ack => dmi_wb_ack,
414 dmi_req => dmi_wb_req,
415 wb_in => wishbone_debug_in,
416 wb_out => wishbone_debug_out);
419 end architecture behaviour;