soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
  14 --
  15 -- Main bus:
  16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
  17 -- 0x40000000: DRAM (when present)
  18 -- 0x80000000: Block RAM (aliased & repeated)
  19
  20 -- IO Bus:
  21 -- 0xc0000000: SYSCON
  22 -- 0xc0002000: UART0
  23 -- 0xc0004000: XICS ICP
  24 -- 0xc0006000: SPI Flash controller
  25 -- 0xc0100000: LiteDRAM control (CSRs)
  26 -- 0xf0000000: Flash "ROM" mapping
  27 -- 0xff000000: DRAM init code (if any) or flash ROM
  28
  29 entity soc is
  30     generic (
  31         MEMORY_SIZE        : natural;
  32         RAM_INIT_FILE      : string;
  33         CLK_FREQ           : positive;
  34         SIM                : boolean;
  35         DISABLE_FLATTEN_CORE : boolean := false;
  36         HAS_DRAM           : boolean  := false;
  37         DRAM_SIZE          : integer := 0;
  38         DRAM_INIT_SIZE     : integer := 0;
  39         HAS_SPI_FLASH      : boolean := false;
  40         SPI_FLASH_DLINES   : positive := 1;
  41         SPI_FLASH_OFFSET   : integer := 0;
  42         SPI_FLASH_DEF_CKDV : natural := 2;
  43         SPI_FLASH_DEF_QUAD : boolean := false
  44         );
  45     port(
  46         rst          : in  std_ulogic;
  47         system_clk   : in  std_ulogic;
  48
  49         -- DRAM controller signals
  50         wb_dram_in       : out wishbone_master_out;
  51         wb_dram_out      : in wishbone_slave_out := wishbone_slave_out_init;
  52         wb_dram_ctrl_in  : out wb_io_master_out;
  53         wb_dram_ctrl_out : in wb_io_slave_out := wb_io_slave_out_init;
  54         wb_dram_is_csr   : out std_ulogic;
  55         wb_dram_is_init  : out std_ulogic;
  56
  57         -- UART0 signals:
  58         uart0_txd    : out std_ulogic;
  59         uart0_rxd    : in  std_ulogic := '0';
  60
  61         -- SPI Flash signals
  62         spi_flash_sck     : out std_ulogic;
  63         spi_flash_cs_n    : out std_ulogic;
  64         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
  65         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
  66         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
  67
  68         -- DRAM controller signals
  69         alt_reset    : in std_ulogic := '0'
  70         );
  71 end entity soc;
  72
  73 architecture behaviour of soc is
  74
  75     -- Wishbone master signals:
  76     signal wishbone_dcore_in  : wishbone_slave_out;
  77     signal wishbone_dcore_out : wishbone_master_out;
  78     signal wishbone_icore_in  : wishbone_slave_out;
  79     signal wishbone_icore_out : wishbone_master_out;
  80     signal wishbone_debug_in : wishbone_slave_out;
  81     signal wishbone_debug_out : wishbone_master_out;
  82
  83     -- Arbiter array (ghdl doesnt' support assigning the array
  84     -- elements in the entity instantiation)
  85     constant NUM_WB_MASTERS : positive := 3;
  86     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
  87     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
  88
  89     -- Wishbone master (output of arbiter):
  90     signal wb_master_in       : wishbone_slave_out;
  91     signal wb_master_out      : wishbone_master_out;
  92
  93     -- Main "IO" bus, from main slave decoder to the latch
  94     signal wb_io_in     : wishbone_master_out;
  95     signal wb_io_out    : wishbone_slave_out;
  96
  97     -- Secondary (smaller) IO bus after the IO bus latch
  98     signal wb_sio_out    : wb_io_master_out;
  99     signal wb_sio_in     : wb_io_slave_out;
 100
 101     -- Syscon signals
 102     signal dram_at_0     : std_ulogic;
 103     signal do_core_reset    : std_ulogic;
 104     signal wb_syscon_in  : wb_io_master_out;
 105     signal wb_syscon_out : wb_io_slave_out;
 106
 107     -- UART0 signals:
 108     signal wb_uart0_in   : wb_io_master_out;
 109     signal wb_uart0_out  : wb_io_slave_out;
 110     signal uart_dat8     : std_ulogic_vector(7 downto 0);
 111
 112     -- SPI Flash controller signals:
 113     signal wb_spiflash_in     : wb_io_master_out;
 114     signal wb_spiflash_out    : wb_io_slave_out;
 115     signal wb_spiflash_is_reg : std_ulogic;
 116     signal wb_spiflash_is_map : std_ulogic;
 117
 118     -- XICS0 signals:
 119     signal wb_xics0_in   : wb_io_master_out;
 120     signal wb_xics0_out  : wb_io_slave_out;
 121     signal int_level_in  : std_ulogic_vector(15 downto 0);
 122
 123     signal core_ext_irq  : std_ulogic;
 124
 125     -- Main memory signals:
 126     signal wb_bram_in     : wishbone_master_out;
 127     signal wb_bram_out    : wishbone_slave_out;
 128
 129     -- DMI debug bus signals
 130     signal dmi_addr     : std_ulogic_vector(7 downto 0);
 131     signal dmi_din      : std_ulogic_vector(63 downto 0);
 132     signal dmi_dout     : std_ulogic_vector(63 downto 0);
 133     signal dmi_req      : std_ulogic;
 134     signal dmi_wr       : std_ulogic;
 135     signal dmi_ack      : std_ulogic;
 136
 137     -- Per slave DMI signals
 138     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
 139     signal dmi_wb_req   : std_ulogic;
 140     signal dmi_wb_ack   : std_ulogic;
 141     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
 142     signal dmi_core_req   : std_ulogic;
 143     signal dmi_core_ack   : std_ulogic;
 144
 145     -- Delayed/latched resets and alt_reset
 146     signal rst_core    : std_ulogic := '1';
 147     signal rst_uart    : std_ulogic := '1';
 148     signal rst_xics    : std_ulogic := '1';
 149     signal rst_spi     : std_ulogic := '1';
 150     signal rst_bram    : std_ulogic := '1';
 151     signal rst_dtm     : std_ulogic := '1';
 152     signal rst_wbar    : std_ulogic := '1';
 153     signal rst_wbdb    : std_ulogic := '1';
 154     signal alt_reset_d : std_ulogic;
 155
 156         -- IO branch split:
 157         type slave_io_type is (SLAVE_IO_SYSCON,
 158                                SLAVE_IO_UART,
 159                                SLAVE_IO_DRAM_INIT,
 160                                SLAVE_IO_DRAM_CSR,
 161                                SLAVE_IO_ICP_0,
 162                                SLAVE_IO_SPI_FLASH_REG,
 163                                SLAVE_IO_SPI_FLASH_MAP,
 164                                SLAVE_IO_NONE);
 165     signal slave_io_dbg : slave_io_type;
 166 begin
 167
 168     resets: process(system_clk)
 169     begin
 170         if rising_edge(system_clk) then
 171             rst_core    <= rst or do_core_reset;
 172             rst_uart    <= rst;
 173             rst_spi     <= rst;
 174             rst_xics    <= rst;
 175             rst_bram    <= rst;
 176             rst_dtm     <= rst;
 177             rst_wbar    <= rst;
 178             rst_wbdb    <= rst;
 179             alt_reset_d <= alt_reset;
 180         end if;
 181     end process;
 182
 183     -- Processor core
 184     processor: entity work.core
 185         generic map(
 186             SIM => SIM,
 187             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 188             ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1')
 189             )
 190         port map(
 191             clk => system_clk,
 192             rst => rst_core,
 193             alt_reset => alt_reset_d,
 194             wishbone_insn_in => wishbone_icore_in,
 195             wishbone_insn_out => wishbone_icore_out,
 196             wishbone_data_in => wishbone_dcore_in,
 197             wishbone_data_out => wishbone_dcore_out,
 198             dmi_addr => dmi_addr(3 downto 0),
 199             dmi_dout => dmi_core_dout,
 200             dmi_din => dmi_dout,
 201             dmi_wr => dmi_wr,
 202             dmi_ack => dmi_core_ack,
 203             dmi_req => dmi_core_req,
 204             ext_irq => core_ext_irq
 205             );
 206
 207     -- Wishbone bus master arbiter & mux
 208     wb_masters_out <= (0 => wishbone_dcore_out,
 209                        1 => wishbone_icore_out,
 210                        2 => wishbone_debug_out);
 211     wishbone_dcore_in <= wb_masters_in(0);
 212     wishbone_icore_in <= wb_masters_in(1);
 213     wishbone_debug_in <= wb_masters_in(2);
 214     wishbone_arbiter_0: entity work.wishbone_arbiter
 215         generic map(
 216             NUM_MASTERS => NUM_WB_MASTERS
 217             )
 218         port map(
 219             clk => system_clk,
 220             rst => rst_wbar,
 221             wb_masters_in => wb_masters_out,
 222             wb_masters_out => wb_masters_in,
 223             wb_slave_out => wb_master_out,
 224             wb_slave_in => wb_master_in
 225             );
 226
 227     -- Top level Wishbone slaves address decoder & mux
 228     --
 229     -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
 230     -- 0000  - BRAM
 231     -- 0001  - DRAM
 232     -- 01xx  - DRAM
 233     -- 10xx  - BRAM
 234     -- 11xx  - IO
 235     --
 236     slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
 237         type slave_top_type is (SLAVE_TOP_BRAM,
 238                                 SLAVE_TOP_DRAM,
 239                                 SLAVE_TOP_IO);
 240         variable slave_top : slave_top_type;
 241         variable top_decode : std_ulogic_vector(3 downto 0);
 242     begin
 243         -- Top-level address decoder
 244         top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
 245         slave_top := SLAVE_TOP_BRAM;
 246         if    std_match(top_decode, "0000") then
 247             slave_top := SLAVE_TOP_BRAM;
 248         elsif std_match(top_decode, "0001") then
 249             slave_top := SLAVE_TOP_DRAM;
 250         elsif std_match(top_decode, "01--") then
 251             slave_top := SLAVE_TOP_DRAM;
 252         elsif std_match(top_decode, "10--") then
 253             slave_top := SLAVE_TOP_BRAM;
 254         elsif std_match(top_decode, "11--") then
 255             slave_top := SLAVE_TOP_IO;
 256         end if;
 257
 258         -- Top level wishbone muxing.
 259         wb_bram_in <= wb_master_out;
 260         wb_bram_in.cyc  <= '0';
 261         wb_dram_in <= wb_master_out;
 262         wb_dram_in.cyc  <= '0';
 263         wb_io_in <= wb_master_out;
 264         wb_io_in.cyc  <= '0';
 265         case slave_top is
 266         when SLAVE_TOP_BRAM =>
 267             wb_bram_in.cyc <= wb_master_out.cyc;
 268             wb_master_in <= wb_bram_out;
 269         when SLAVE_TOP_DRAM =>
 270             if HAS_DRAM then
 271                 wb_dram_in.cyc <= wb_master_out.cyc;
 272                 wb_master_in <= wb_dram_out;
 273             else
 274                 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
 275                 wb_master_in.dat <= (others => '1');
 276                 wb_master_in.stall <= '0';
 277             end if;
 278         when SLAVE_TOP_IO =>
 279             wb_io_in.cyc <= wb_master_out.cyc;
 280             wb_master_in <= wb_io_out;
 281         end case;
 282     end process slave_top_intercon;
 283
 284     -- IO wishbone slave 64->32 bits converter
 285     --
 286     -- For timing reasons, this adds a one cycle latch on the way both
 287     -- in and out. This relaxes timing and routing pressure on the "main"
 288     -- memory bus by moving all simple IOs to a slower 32-bit bus.
 289     --
 290     -- This implementation is rather dumb at the moment, no stash buffer,
 291     -- so we stall whenever that latch is busy. This can be improved.
 292     --
 293     slave_io_latch: process(system_clk)
 294         -- State
 295         type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
 296         variable state : state_t;
 297
 298         -- Misc
 299         variable has_top : boolean;
 300         variable has_bot : boolean;
 301     begin
 302         if rising_edge(system_clk) then
 303             if (rst) then
 304                 state := IDLE;
 305                 wb_io_out.ack <= '0';
 306                 wb_io_out.stall <= '0';
 307                 wb_sio_out.cyc <= '0';
 308                 wb_sio_out.stb <= '0';
 309                 has_top := false;
 310                 has_bot := false;
 311             else
 312                 case state is
 313                 when IDLE =>
 314                     -- Clear ACK in case it was set
 315                     wb_io_out.ack <= '0';
 316
 317                     -- Do we have a cycle ?
 318                     if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
 319                         -- Stall master until we are done, we are't (yet) pipelining
 320                         -- this, it's all slow IOs.
 321                         wb_io_out.stall <= '1';
 322
 323                         -- Start cycle downstream
 324                         wb_sio_out.cyc <= '1';
 325                         wb_sio_out.stb <= '1';
 326
 327                         -- Copy write enable to IO out, copy address as well
 328                         wb_sio_out.we <= wb_io_in.we;
 329                         wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
 330
 331                         -- Do we have a top word and/or a bottom word ?
 332                         has_top := wb_io_in.sel(7 downto 4) /= "0000";
 333                         has_bot := wb_io_in.sel(3 downto 0) /= "0000";
 334
 335                         -- If we have a bottom word, handle it first, otherwise
 336                         -- send the top word down. XXX Split the actual mux out
 337                         -- and only generate a control signal.
 338                         if has_bot then
 339                             if wb_io_in.we = '1' then
 340                                 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
 341                             end if;
 342                             wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
 343
 344                             -- Wait for ack
 345                             state := WAIT_ACK_BOT;
 346                         else
 347                             if wb_io_in.we = '1' then
 348                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 349                             end if;
 350                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 351
 352                             -- Bump address
 353                             wb_sio_out.adr(2) <= '1';
 354
 355                             -- Wait for ack
 356                             state := WAIT_ACK_TOP;
 357                         end if;
 358                     end if;
 359                 when WAIT_ACK_BOT =>
 360                     -- If we aren't stalled by the device, clear stb
 361                     if wb_sio_in.stall = '0' then
 362                         wb_sio_out.stb <= '0';
 363                     end if;
 364
 365                     -- Handle ack
 366                     if wb_sio_in.ack = '1' then
 367                         -- If it's a read, latch the data
 368                         if wb_sio_out.we = '0' then
 369                             wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
 370                         end if;
 371
 372                         -- Do we have a "top" part as well ?
 373                         if has_top then
 374                             -- Latch data & sel
 375                             if wb_io_in.we = '1' then
 376                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 377                             end if;
 378                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 379
 380                             -- Bump address and set STB
 381                             wb_sio_out.adr(2) <= '1';
 382                             wb_sio_out.stb <= '1';
 383
 384                             -- Wait for new ack
 385                             state := WAIT_ACK_TOP;
 386                         else
 387                             -- We are done, ack up, clear cyc downstram
 388                             wb_sio_out.cyc <= '0';
 389
 390                             -- And ack & unstall upstream
 391                             wb_io_out.ack <= '1';
 392                             wb_io_out.stall <= '0';
 393
 394                             -- Wait for next one
 395                             state := IDLE;
 396                         end if;
 397                     end if;
 398                 when WAIT_ACK_TOP =>
 399                     -- If we aren't stalled by the device, clear stb
 400                     if wb_sio_in.stall = '0' then
 401                         wb_sio_out.stb <= '0';
 402                     end if;
 403
 404                     -- Handle ack
 405                     if wb_sio_in.ack = '1' then
 406                         -- If it's a read, latch the data
 407                         if wb_sio_out.we = '0' then
 408                             wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
 409                         end if;
 410
 411                         -- We are done, ack up, clear cyc downstram
 412                         wb_sio_out.cyc <= '0';
 413
 414                         -- And ack & unstall upstream
 415                         wb_io_out.ack <= '1';
 416                         wb_io_out.stall <= '0';
 417
 418                         -- Wait for next one
 419                         state := IDLE;
 420                     end if;
 421                 end case;
 422             end if;
 423         end if;
 424     end process;
 425
 426     -- IO wishbone slave intercon.
 427     --
 428     slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out,
 429                                wb_dram_ctrl_out, wb_xics0_out, wb_spiflash_out)
 430         variable slave_io : slave_io_type;
 431
 432         variable match : std_ulogic_vector(31 downto 12);
 433     begin
 434
 435         -- Simple address decoder.
 436         slave_io := SLAVE_IO_NONE;
 437         match := "11" & wb_sio_out.adr(29 downto 12);
 438         if    std_match(match, x"FF---") and HAS_DRAM then
 439             slave_io := SLAVE_IO_DRAM_INIT;
 440         elsif std_match(match, x"F----") then
 441             slave_io := SLAVE_IO_SPI_FLASH_MAP;
 442         elsif std_match(match, x"C0000") then
 443             slave_io := SLAVE_IO_SYSCON;
 444         elsif std_match(match, x"C0002") then
 445             slave_io := SLAVE_IO_UART;
 446         elsif std_match(match, x"C01--") then
 447             slave_io := SLAVE_IO_DRAM_CSR;
 448         elsif std_match(match, x"C0004") then
 449             slave_io := SLAVE_IO_ICP_0;
 450         elsif std_match(match, x"C0006") then
 451             slave_io := SLAVE_IO_SPI_FLASH_REG;
 452         end if;
 453         slave_io_dbg <= slave_io;
 454         wb_uart0_in <= wb_sio_out;
 455         wb_uart0_in.cyc <= '0';
 456         wb_spiflash_in <= wb_sio_out;
 457         wb_spiflash_in.cyc <= '0';
 458         wb_spiflash_is_reg <= '0';
 459         wb_spiflash_is_map <= '0';
 460
 461          -- Only give xics 8 bits of wb addr
 462         wb_xics0_in <= wb_sio_out;
 463         wb_xics0_in.adr <= (others => '0');
 464         wb_xics0_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
 465         wb_xics0_in.cyc  <= '0';
 466
 467         wb_dram_ctrl_in <= wb_sio_out;
 468         wb_dram_ctrl_in.cyc <= '0';
 469         wb_dram_is_csr <= '0';
 470         wb_dram_is_init <= '0';
 471
 472         wb_syscon_in <= wb_sio_out;
 473         wb_syscon_in.cyc <= '0';
 474
 475         case slave_io is
 476         when SLAVE_IO_DRAM_INIT =>
 477             if HAS_DRAM then
 478                 wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
 479                 wb_sio_in <= wb_dram_ctrl_out;
 480             else
 481                 wb_sio_in.ack <= wb_sio_out.cyc and wb_sio_out.stb;
 482                 wb_sio_in.dat <= (others => '1');
 483                 wb_sio_in.stall <= '0';
 484             end if;
 485             wb_dram_is_init <= '1';
 486         when SLAVE_IO_DRAM_CSR =>
 487             if HAS_DRAM then
 488                 wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
 489                 wb_sio_in <= wb_dram_ctrl_out;
 490             else
 491                 wb_sio_in.ack <= wb_sio_out.cyc and wb_sio_out.stb;
 492                 wb_sio_in.dat <= (others => '1');
 493                 wb_sio_in.stall <= '0';
 494             end if;
 495             wb_dram_is_csr <= '1';
 496         when SLAVE_IO_SYSCON =>
 497             wb_syscon_in.cyc <= wb_sio_out.cyc;
 498             wb_sio_in <= wb_syscon_out;
 499         when SLAVE_IO_UART =>
 500             wb_uart0_in.cyc <= wb_sio_out.cyc;
 501             wb_sio_in <= wb_uart0_out;
 502         when SLAVE_IO_ICP_0 =>
 503             wb_xics0_in.cyc <= wb_sio_out.cyc;
 504             wb_sio_in <= wb_xics0_out;
 505         when SLAVE_IO_SPI_FLASH_MAP =>
 506             -- Clear top bits so they don't make their way to the
 507             -- fash chip.
 508             wb_spiflash_in.adr(29 downto 28) <= "00";
 509             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 510             wb_sio_in <= wb_spiflash_out;
 511             wb_spiflash_is_map <= '1';
 512         when SLAVE_IO_SPI_FLASH_REG =>
 513             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 514             wb_sio_in <= wb_spiflash_out;
 515             wb_spiflash_is_reg <= '1';
 516         when others =>
 517             wb_sio_in.dat <= (others => '1');
 518             wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
 519             wb_sio_in.stall <= '0';
 520         end case;
 521
 522     end process;
 523
 524     -- Syscon slave
 525     syscon0: entity work.syscon
 526         generic map(
 527             HAS_UART => true,
 528             HAS_DRAM => HAS_DRAM,
 529             BRAM_SIZE => MEMORY_SIZE,
 530             DRAM_SIZE => DRAM_SIZE,
 531             DRAM_INIT_SIZE => DRAM_INIT_SIZE,
 532             CLK_FREQ => CLK_FREQ,
 533             HAS_SPI_FLASH => HAS_SPI_FLASH,
 534             SPI_FLASH_OFFSET => SPI_FLASH_OFFSET
 535         )
 536         port map(
 537             clk => system_clk,
 538             rst => rst,
 539             wishbone_in => wb_syscon_in,
 540             wishbone_out => wb_syscon_out,
 541             dram_at_0 => dram_at_0,
 542             core_reset => do_core_reset,
 543             soc_reset => open -- XXX TODO
 544             );
 545
 546     -- Simulated memory and UART
 547
 548     -- UART0 wishbone slave
 549     uart0: entity work.pp_soc_uart
 550         generic map(
 551             FIFO_DEPTH => 32
 552             )
 553         port map(
 554             clk => system_clk,
 555             reset => rst_uart,
 556             txd => uart0_txd,
 557             rxd => uart0_rxd,
 558             irq => int_level_in(0),
 559             wb_adr_in => wb_uart0_in.adr(11 downto 0),
 560             wb_dat_in => wb_uart0_in.dat(7 downto 0),
 561             wb_dat_out => uart_dat8,
 562             wb_cyc_in => wb_uart0_in.cyc,
 563             wb_stb_in => wb_uart0_in.stb,
 564             wb_we_in => wb_uart0_in.we,
 565             wb_ack_out => wb_uart0_out.ack
 566             );
 567     wb_uart0_out.dat <= x"000000" & uart_dat8;
 568     wb_uart0_out.stall <= not wb_uart0_out.ack;
 569
 570     spiflash_gen: if HAS_SPI_FLASH generate
 571         spiflash: entity work.spi_flash_ctrl
 572             generic map (
 573                 DATA_LINES    => SPI_FLASH_DLINES,
 574                 DEF_CLK_DIV   => SPI_FLASH_DEF_CKDV,
 575                 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
 576                 )
 577             port map(
 578                 rst => rst_spi,
 579                 clk => system_clk,
 580                 wb_in => wb_spiflash_in,
 581                 wb_out => wb_spiflash_out,
 582                 wb_sel_reg => wb_spiflash_is_reg,
 583                 wb_sel_map => wb_spiflash_is_map,
 584                 sck => spi_flash_sck,
 585                 cs_n => spi_flash_cs_n,
 586                 sdat_o => spi_flash_sdat_o,
 587                 sdat_oe => spi_flash_sdat_oe,
 588                 sdat_i => spi_flash_sdat_i
 589                 );
 590     end generate;
 591
 592     no_spi0_gen: if not HAS_SPI_FLASH generate
 593         wb_spiflash_out.dat   <= (others => '1');
 594         wb_spiflash_out.ack   <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
 595         wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
 596     end generate;
 597
 598     xics0: entity work.xics
 599         generic map(
 600             LEVEL_NUM => 16
 601             )
 602         port map(
 603             clk => system_clk,
 604             rst => rst_xics,
 605             wb_in => wb_xics0_in,
 606             wb_out => wb_xics0_out,
 607             int_level_in => int_level_in,
 608             core_irq_out => core_ext_irq
 609             );
 610
 611     -- BRAM Memory slave
 612     bram: if MEMORY_SIZE /= 0 generate
 613         bram0: entity work.wishbone_bram_wrapper
 614             generic map(
 615                 MEMORY_SIZE   => MEMORY_SIZE,
 616                 RAM_INIT_FILE => RAM_INIT_FILE
 617                 )
 618             port map(
 619                 clk => system_clk,
 620                 rst => rst_bram,
 621                 wishbone_in => wb_bram_in,
 622                 wishbone_out => wb_bram_out
 623                 );
 624     end generate;
 625
 626     no_bram: if MEMORY_SIZE = 0 generate
 627         wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
 628         wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
 629         wb_bram_out.stall <= not wb_bram_out.ack;
 630     end generate;
 631
 632     -- DMI(debug bus) <-> JTAG bridge
 633     dtm: entity work.dmi_dtm
 634         generic map(
 635             ABITS => 8,
 636             DBITS => 64
 637             )
 638         port map(
 639             sys_clk     => system_clk,
 640             sys_reset   => rst_dtm,
 641             dmi_addr    => dmi_addr,
 642             dmi_din     => dmi_din,
 643             dmi_dout    => dmi_dout,
 644             dmi_req     => dmi_req,
 645             dmi_wr      => dmi_wr,
 646             dmi_ack     => dmi_ack
 647             );
 648
 649     -- DMI interconnect
 650     dmi_intercon: process(dmi_addr, dmi_req,
 651                           dmi_wb_ack, dmi_wb_dout,
 652                           dmi_core_ack, dmi_core_dout)
 653
 654         -- DMI address map (each address is a full 64-bit register)
 655         --
 656         -- Offset:   Size:    Slave:
 657         --  0         4       Wishbone
 658         -- 10        16       Core
 659
 660         type slave_type is (SLAVE_WB,
 661                             SLAVE_CORE,
 662                             SLAVE_NONE);
 663         variable slave : slave_type;
 664     begin
 665         -- Simple address decoder
 666         slave := SLAVE_NONE;
 667         if std_match(dmi_addr, "000000--") then
 668             slave := SLAVE_WB;
 669         elsif std_match(dmi_addr, "0001----") then
 670             slave := SLAVE_CORE;
 671         end if;
 672
 673         -- DMI muxing
 674         dmi_wb_req <= '0';
 675         dmi_core_req <= '0';
 676         case slave is
 677         when SLAVE_WB =>
 678             dmi_wb_req <= dmi_req;
 679             dmi_ack <= dmi_wb_ack;
 680             dmi_din <= dmi_wb_dout;
 681         when SLAVE_CORE =>
 682             dmi_core_req <= dmi_req;
 683             dmi_ack <= dmi_core_ack;
 684             dmi_din <= dmi_core_dout;
 685         when others =>
 686             dmi_ack <= dmi_req;
 687             dmi_din <= (others => '1');
 688         end case;
 689
 690         -- SIM magic exit
 691         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
 692             stop;
 693         end if;
 694     end process;
 695
 696     -- Wishbone debug master (TODO: Add a DMI address decoder)
 697     wishbone_debug: entity work.wishbone_debug_master
 698         port map(clk => system_clk,
 699                  rst => rst_wbdb,
 700                  dmi_addr => dmi_addr(1 downto 0),
 701                  dmi_dout => dmi_wb_dout,
 702                  dmi_din => dmi_dout,
 703                  dmi_wr => dmi_wr,
 704                  dmi_ack => dmi_wb_ack,
 705                  dmi_req => dmi_wb_req,
 706                  wb_in => wishbone_debug_in,
 707                  wb_out => wishbone_debug_out);
 708
 709
 710 end architecture behaviour;