2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
10 use work.wishbone_types.all;
13 -- 0x00000000: Main memory (1 MB)
14 -- 0xc0002000: UART0 (for host communication)
17 MEMORY_SIZE : positive;
18 RAM_INIT_FILE : string;
21 DISABLE_FLATTEN_CORE : boolean := false
25 system_clk : in std_ulogic;
28 uart0_txd : out std_ulogic;
29 uart0_rxd : in std_ulogic;
31 -- Misc (to use for things like LEDs)
32 core_terminated : out std_ulogic
36 architecture behaviour of soc is
38 -- Wishbone master signals:
39 signal wishbone_dcore_in : wishbone_slave_out;
40 signal wishbone_dcore_out : wishbone_master_out;
41 signal wishbone_icore_in : wishbone_slave_out;
42 signal wishbone_icore_out : wishbone_master_out;
43 signal wishbone_debug_in : wishbone_slave_out;
44 signal wishbone_debug_out : wishbone_master_out;
46 -- Wishbone master (output of arbiter):
47 signal wb_master_in : wishbone_slave_out;
48 signal wb_master_out : wishbone_master_out;
51 signal wb_uart0_in : wishbone_master_out;
52 signal wb_uart0_out : wishbone_slave_out;
53 signal uart_dat8 : std_ulogic_vector(7 downto 0);
55 -- Main memory signals:
56 signal wb_bram_in : wishbone_master_out;
57 signal wb_bram_out : wishbone_slave_out;
58 constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
60 -- DMI debug bus signals
61 signal dmi_addr : std_ulogic_vector(7 downto 0);
62 signal dmi_din : std_ulogic_vector(63 downto 0);
63 signal dmi_dout : std_ulogic_vector(63 downto 0);
64 signal dmi_req : std_ulogic;
65 signal dmi_wr : std_ulogic;
66 signal dmi_ack : std_ulogic;
68 -- Per slave DMI signals
69 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
70 signal dmi_wb_req : std_ulogic;
71 signal dmi_wb_ack : std_ulogic;
72 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
73 signal dmi_core_req : std_ulogic;
74 signal dmi_core_ack : std_ulogic;
78 processor: entity work.core
81 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE
86 wishbone_insn_in => wishbone_icore_in,
87 wishbone_insn_out => wishbone_icore_out,
88 wishbone_data_in => wishbone_dcore_in,
89 wishbone_data_out => wishbone_dcore_out,
90 dmi_addr => dmi_addr(3 downto 0),
91 dmi_dout => dmi_core_dout,
94 dmi_ack => dmi_core_ack,
95 dmi_req => dmi_core_req
98 -- Wishbone bus master arbiter & mux
99 wishbone_arbiter_0: entity work.wishbone_arbiter
101 clk => system_clk, rst => rst,
102 wb1_in => wishbone_dcore_out, wb1_out => wishbone_dcore_in,
103 wb2_in => wishbone_icore_out, wb2_out => wishbone_icore_in,
104 wb3_in => wishbone_debug_out, wb3_out => wishbone_debug_in,
105 wb_out => wb_master_out, wb_in => wb_master_in
108 -- Wishbone slaves address decoder & mux
109 slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
111 type slave_type is (SLAVE_UART_0,
114 variable slave : slave_type;
116 -- Simple address decoder.
118 if wb_master_out.adr(31 downto 24) = x"00" then
119 slave := SLAVE_MEMORY;
120 elsif wb_master_out.adr(31 downto 24) = x"c0" then
121 if wb_master_out.adr(23 downto 12) = x"002" then
122 slave := SLAVE_UART_0;
126 -- Wishbone muxing. Defaults:
127 wb_bram_in <= wb_master_out;
128 wb_bram_in.cyc <= '0';
129 wb_uart0_in <= wb_master_out;
130 wb_uart0_in.cyc <= '0';
133 wb_bram_in.cyc <= wb_master_out.cyc;
134 wb_master_in <= wb_bram_out;
136 wb_uart0_in.cyc <= wb_master_out.cyc;
137 wb_master_in <= wb_uart0_out;
139 wb_master_in.dat <= (others => '1');
140 wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
141 wb_master_in.stall <= '0';
143 end process slave_intercon;
145 -- Simulated memory and UART
147 -- UART0 wishbone slave
148 -- XXX FIXME: Need a proper wb64->wb8 adapter that
149 -- converts SELs into low address bits and muxes
150 -- data accordingly (either that or rejects large
152 uart0: entity work.pp_soc_uart
161 wb_adr_in => wb_uart0_in.adr(11 downto 0),
162 wb_dat_in => wb_uart0_in.dat(7 downto 0),
163 wb_dat_out => uart_dat8,
164 wb_cyc_in => wb_uart0_in.cyc,
165 wb_stb_in => wb_uart0_in.stb,
166 wb_we_in => wb_uart0_in.we,
167 wb_ack_out => wb_uart0_out.ack
169 wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
170 wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
173 bram0: entity work.mw_soc_memory
175 MEMORY_SIZE => MEMORY_SIZE,
176 RAM_INIT_FILE => RAM_INIT_FILE
181 wishbone_in => wb_bram_in,
182 wishbone_out => wb_bram_out
185 -- DMI(debug bus) <-> JTAG bridge
186 dtm: entity work.dmi_dtm
192 sys_clk => system_clk,
194 dmi_addr => dmi_addr,
196 dmi_dout => dmi_dout,
203 dmi_intercon: process(dmi_addr, dmi_req,
204 dmi_wb_ack, dmi_wb_dout,
205 dmi_core_ack, dmi_core_dout)
207 -- DMI address map (each address is a full 64-bit register)
209 -- Offset: Size: Slave:
213 type slave_type is (SLAVE_WB,
216 variable slave : slave_type;
218 -- Simple address decoder
220 if std_match(dmi_addr, "000000--") then
222 elsif std_match(dmi_addr, "0001----") then
231 dmi_wb_req <= dmi_req;
232 dmi_ack <= dmi_wb_ack;
233 dmi_din <= dmi_wb_dout;
235 dmi_core_req <= dmi_req;
236 dmi_ack <= dmi_core_ack;
237 dmi_din <= dmi_core_dout;
240 dmi_din <= (others => '1');
244 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
249 -- Wishbone debug master (TODO: Add a DMI address decoder)
250 wishbone_debug: entity work.wishbone_debug_master
251 port map(clk => system_clk, rst => rst,
252 dmi_addr => dmi_addr(1 downto 0),
253 dmi_dout => dmi_wb_dout,
256 dmi_ack => dmi_wb_ack,
257 dmi_req => dmi_wb_req,
258 wb_in => wishbone_debug_in,
259 wb_out => wishbone_debug_out);
262 end architecture behaviour;