soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.math_real.all;
   4
   5 use std.textio.all;
   6
   7 library work;
   8 use work.common.all;
   9 use work.wishbone_types.all;
  10
  11
  12 -- 0x00000000: Main memory (1 MB)
  13 -- 0xc0002000: UART0 (for host communication)
  14 entity soc is
  15     generic (
  16         MEMORY_SIZE   : positive;
  17         RAM_INIT_FILE : string;
  18         RESET_LOW     : boolean;
  19         SIM           : boolean
  20         );
  21     port(
  22         rst          : in  std_ulogic;
  23         system_clk   : in  std_ulogic;
  24
  25         -- UART0 signals:
  26         uart0_txd    : out std_ulogic;
  27         uart0_rxd    : in  std_ulogic
  28         );
  29 end entity soc;
  30
  31 architecture behaviour of soc is
  32
  33     -- Wishbone master signals:
  34     signal wishbone_dcore_in : wishbone_slave_out;
  35     signal wishbone_dcore_out : wishbone_master_out;
  36     signal wishbone_icore_in : wishbone_slave_out;
  37     signal wishbone_icore_out : wishbone_master_out;
  38     signal wishbone_debug_in : wishbone_slave_out;
  39     signal wishbone_debug_out : wishbone_master_out;
  40
  41     -- Wishbone master (output of arbiter):
  42     signal wb_master_in : wishbone_slave_out;
  43     signal wb_master_out : wishbone_master_out;
  44
  45     -- UART0 signals:
  46     signal wb_uart0_in   : wishbone_master_out;
  47     signal wb_uart0_out  : wishbone_slave_out;
  48     signal uart_dat8     : std_ulogic_vector(7 downto 0);
  49
  50     -- Main memory signals:
  51     signal wb_bram_in     : wishbone_master_out;
  52     signal wb_bram_out    : wishbone_slave_out;
  53     constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
  54
  55     -- Core debug signals (used in SIM only)
  56     signal registers     : regfile;
  57     signal terminate     : std_ulogic;
  58
  59     -- DMI debug bus signals
  60     signal dmi_addr     : std_ulogic_vector(7 downto 0);
  61     signal dmi_din      : std_ulogic_vector(63 downto 0);
  62     signal dmi_dout     : std_ulogic_vector(63 downto 0);
  63     signal dmi_req      : std_ulogic;
  64     signal dmi_wr       : std_ulogic;
  65     signal dmi_ack      : std_ulogic;
  66
  67 begin
  68
  69     -- Processor core
  70     processor: entity work.core
  71         generic map(
  72             SIM => SIM
  73             )
  74         port map(
  75             clk => system_clk,
  76             rst => rst,
  77             wishbone_insn_in => wishbone_icore_in,
  78             wishbone_insn_out => wishbone_icore_out,
  79             wishbone_data_in => wishbone_dcore_in,
  80             wishbone_data_out => wishbone_dcore_out,
  81             registers => registers,
  82             terminate_out => terminate
  83             );
  84
  85     -- Wishbone bus master arbiter & mux
  86     wishbone_arbiter_0: entity work.wishbone_arbiter
  87         port map(
  88             clk => system_clk, rst => rst,
  89             wb1_in => wishbone_dcore_out, wb1_out => wishbone_dcore_in,
  90             wb2_in => wishbone_icore_out, wb2_out => wishbone_icore_in,
  91             wb3_in => wishbone_debug_out, wb3_out => wishbone_debug_in,
  92             wb_out => wb_master_out, wb_in => wb_master_in
  93             );
  94
  95     -- Dummy wishbone debug module
  96     wishbone_debug_out.cyc <= '0';
  97     wishbone_debug_out.stb <= '0';
  98
  99     -- Wishbone slaves address decoder & mux
 100     slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
 101         -- Selected slave
 102         type slave_type is (SLAVE_UART,
 103                             SLAVE_MEMORY,
 104                             SLAVE_NONE);
 105         variable slave : slave_type;
 106     begin
 107         -- Simple address decoder
 108         slave := SLAVE_NONE;
 109         if wb_master_out.adr(63 downto 24) = x"0000000000" then
 110             slave := SLAVE_MEMORY;
 111         elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
 112             if wb_master_out.adr(15 downto 12) = x"2" then
 113                 slave := SLAVE_UART;
 114             end if;
 115         end if;
 116
 117         -- Wishbone muxing. Defaults:
 118         wb_bram_in <= wb_master_out;
 119         wb_bram_in.cyc  <= '0';
 120         wb_uart0_in <= wb_master_out;
 121         wb_uart0_in.cyc <= '0';
 122         case slave is
 123         when SLAVE_MEMORY =>
 124             wb_bram_in.cyc <= wb_master_out.cyc;
 125             wb_master_in <= wb_bram_out;
 126         when SLAVE_UART =>
 127             wb_uart0_in.cyc <= wb_master_out.cyc;
 128             wb_master_in <= wb_uart0_out;
 129         when others =>
 130             wb_master_in.dat <= (others => '1');
 131             wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
 132         end case;
 133     end process slave_intercon;
 134
 135     -- Simulated memory and UART
 136     sim_terminate_test: if SIM generate
 137
 138         -- Dump registers if core terminates
 139         dump_registers: process(all)
 140         begin
 141             if terminate = '1' then
 142                 loop_0: for i in 0 to 31 loop
 143                     report "REG " & to_hstring(registers(i));
 144                 end loop loop_0;
 145                 assert false report "end of test" severity failure;
 146             end if;
 147         end process;
 148
 149     end generate;
 150
 151     -- UART0 wishbone slave
 152     -- XXX FIXME: Need a proper wb64->wb8 adapter that
 153     --            converts SELs into low address bits and muxes
 154     --            data accordingly (either that or rejects large
 155     --            cycles).
 156     uart0: entity work.pp_soc_uart
 157         generic map(
 158             FIFO_DEPTH => 32
 159             )
 160         port map(
 161             clk => system_clk,
 162             reset => rst,
 163             txd => uart0_txd,
 164             rxd => uart0_rxd,
 165             wb_adr_in => wb_uart0_in.adr(11 downto 0),
 166             wb_dat_in => wb_uart0_in.dat(7 downto 0),
 167             wb_dat_out => uart_dat8,
 168             wb_cyc_in => wb_uart0_in.cyc,
 169             wb_stb_in => wb_uart0_in.stb,
 170             wb_we_in => wb_uart0_in.we,
 171             wb_ack_out => wb_uart0_out.ack
 172             );
 173     wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
 174
 175     -- BRAM Memory slave
 176     bram0: entity work.mw_soc_memory
 177         generic map(
 178             MEMORY_SIZE   => MEMORY_SIZE,
 179             RAM_INIT_FILE => RAM_INIT_FILE
 180             )
 181         port map(
 182             clk => system_clk,
 183             rst => rst,
 184             wishbone_in => wb_bram_in,
 185             wishbone_out => wb_bram_out
 186             );
 187
 188     -- DMI(debug bus) <-> JTAG bridge
 189     dtm: entity work.dmi_dtm
 190         generic map(
 191             ABITS => 8,
 192             DBITS => 64
 193             )
 194         port map(
 195             sys_clk     => system_clk,
 196             sys_reset   => rst,
 197             dmi_addr    => dmi_addr,
 198             dmi_din     => dmi_din,
 199             dmi_dout    => dmi_dout,
 200             dmi_req     => dmi_req,
 201             dmi_wr      => dmi_wr,
 202             dmi_ack     => dmi_ack
 203             );
 204
 205     -- Dummy loopback until a debug module is present
 206     dmi_din <= dmi_dout;
 207     dmi_ack <= dmi_ack;
 208
 209 end architecture behaviour;