soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- Memory map:
  14 --
  15 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
  16 -- 0x40000000: DRAM (when present)
  17 -- 0xc0000000: SYSCON
  18 -- 0xc0002000: UART0
  19 -- 0xc0004000: XICS ICP
  20 -- 0xc0100000: DRAM CSRs
  21 -- 0xf0000000: Block RAM (aliased & repeated)
  22 -- 0xffff0000: DRAM init code (if any)
  23
  24 entity soc is
  25     generic (
  26         MEMORY_SIZE   : positive;
  27         RAM_INIT_FILE : string;
  28         RESET_LOW     : boolean;
  29         CLK_FREQ      : positive;
  30         SIM           : boolean;
  31         DISABLE_FLATTEN_CORE : boolean := false;
  32         HAS_DRAM      : boolean  := false;
  33         DRAM_SIZE     : integer := 0
  34         );
  35     port(
  36         rst          : in  std_ulogic;
  37         system_clk   : in  std_ulogic;
  38
  39         -- DRAM controller signals
  40         wb_dram_in   : out wishbone_master_out;
  41         wb_dram_out  : in wishbone_slave_out;
  42         wb_dram_csr  : out std_ulogic;
  43         wb_dram_init : out std_ulogic;
  44
  45         -- UART0 signals:
  46         uart0_txd    : out std_ulogic;
  47         uart0_rxd    : in  std_ulogic;
  48
  49         -- DRAM controller signals
  50         alt_reset    : in std_ulogic
  51         );
  52 end entity soc;
  53
  54 architecture behaviour of soc is
  55
  56     -- Wishbone master signals:
  57     signal wishbone_dcore_in  : wishbone_slave_out;
  58     signal wishbone_dcore_out : wishbone_master_out;
  59     signal wishbone_icore_in  : wishbone_slave_out;
  60     signal wishbone_icore_out : wishbone_master_out;
  61     signal wishbone_debug_in : wishbone_slave_out;
  62     signal wishbone_debug_out : wishbone_master_out;
  63
  64     -- Arbiter array (ghdl doesnt' support assigning the array
  65     -- elements in the entity instantiation)
  66     constant NUM_WB_MASTERS : positive := 3;
  67     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
  68     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
  69
  70     -- Wishbone master (output of arbiter):
  71     signal wb_master_in       : wishbone_slave_out;
  72     signal wb_master_out      : wishbone_master_out;
  73
  74     -- Syscon signals
  75     signal dram_at_0     : std_ulogic;
  76     signal core_reset    : std_ulogic;
  77     signal wb_syscon_in  : wishbone_master_out;
  78     signal wb_syscon_out : wishbone_slave_out;
  79
  80     -- UART0 signals:
  81     signal wb_uart0_in   : wishbone_master_out;
  82     signal wb_uart0_out  : wishbone_slave_out;
  83     signal uart_dat8     : std_ulogic_vector(7 downto 0);
  84
  85     -- XICS0 signals:
  86     signal wb_xics0_in   : wishbone_master_out;
  87     signal wb_xics0_out  : wishbone_slave_out;
  88     signal int_level_in  : std_ulogic_vector(15 downto 0);
  89
  90     signal xics_to_execute1 : XicsToExecute1Type;
  91
  92     -- Main memory signals:
  93     signal wb_bram_in     : wishbone_master_out;
  94     signal wb_bram_out    : wishbone_slave_out;
  95     constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
  96
  97     -- DMI debug bus signals
  98     signal dmi_addr     : std_ulogic_vector(7 downto 0);
  99     signal dmi_din      : std_ulogic_vector(63 downto 0);
 100     signal dmi_dout     : std_ulogic_vector(63 downto 0);
 101     signal dmi_req      : std_ulogic;
 102     signal dmi_wr       : std_ulogic;
 103     signal dmi_ack      : std_ulogic;
 104
 105     -- Per slave DMI signals
 106     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
 107     signal dmi_wb_req   : std_ulogic;
 108     signal dmi_wb_ack   : std_ulogic;
 109     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
 110     signal dmi_core_req   : std_ulogic;
 111     signal dmi_core_ack   : std_ulogic;
 112 begin
 113
 114     -- Processor core
 115     processor: entity work.core
 116         generic map(
 117             SIM => SIM,
 118             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 119             ALT_RESET_ADDRESS => (15 downto 0 => '0', others => '1')
 120             )
 121         port map(
 122             clk => system_clk,
 123             rst => rst or core_reset,
 124             alt_reset => alt_reset,
 125             wishbone_insn_in => wishbone_icore_in,
 126             wishbone_insn_out => wishbone_icore_out,
 127             wishbone_data_in => wishbone_dcore_in,
 128             wishbone_data_out => wishbone_dcore_out,
 129             dmi_addr => dmi_addr(3 downto 0),
 130             dmi_dout => dmi_core_dout,
 131             dmi_din => dmi_dout,
 132             dmi_wr => dmi_wr,
 133             dmi_ack => dmi_core_ack,
 134             dmi_req => dmi_core_req,
 135             xics_in => xics_to_execute1
 136             );
 137
 138     -- Wishbone bus master arbiter & mux
 139     wb_masters_out <= (0 => wishbone_dcore_out,
 140                        1 => wishbone_icore_out,
 141                        2 => wishbone_debug_out);
 142     wishbone_dcore_in <= wb_masters_in(0);
 143     wishbone_icore_in <= wb_masters_in(1);
 144     wishbone_debug_in <= wb_masters_in(2);
 145     wishbone_arbiter_0: entity work.wishbone_arbiter
 146         generic map(
 147             NUM_MASTERS => NUM_WB_MASTERS
 148             )
 149         port map(
 150             clk => system_clk, rst => rst,
 151             wb_masters_in => wb_masters_out,
 152             wb_masters_out => wb_masters_in,
 153             wb_slave_out => wb_master_out,
 154             wb_slave_in => wb_master_in
 155             );
 156
 157     -- Wishbone slaves address decoder & mux
 158     slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out, wb_dram_out, wb_syscon_out)
 159         -- Selected slave
 160         type slave_type is (SLAVE_SYSCON,
 161                             SLAVE_UART,
 162                             SLAVE_BRAM,
 163                             SLAVE_DRAM,
 164                             SLAVE_DRAM_INIT,
 165                             SLAVE_DRAM_CSR,
 166                             SLAVE_ICP_0,
 167                             SLAVE_NONE);
 168         variable slave : slave_type;
 169     begin
 170         -- Simple address decoder.
 171         slave := SLAVE_NONE;
 172         -- Simple address decoder. Ignore top bits to save silicon for now
 173         slave := SLAVE_NONE;
 174         if    std_match(wb_master_out.adr, x"0-------") then
 175             slave := SLAVE_DRAM when HAS_DRAM and dram_at_0 = '1' else
 176                      SLAVE_BRAM;
 177         elsif std_match(wb_master_out.adr, x"FFFF----") then
 178             slave := SLAVE_DRAM_INIT;
 179         elsif std_match(wb_master_out.adr, x"F-------") then
 180             slave := SLAVE_BRAM;
 181         elsif std_match(wb_master_out.adr, x"4-------") and HAS_DRAM then
 182             slave := SLAVE_DRAM;
 183         elsif std_match(wb_master_out.adr, x"C0000---") then
 184             slave := SLAVE_SYSCON;
 185         elsif std_match(wb_master_out.adr, x"C0002---") then
 186             slave := SLAVE_UART;
 187         elsif std_match(wb_master_out.adr, x"C01-----") then
 188             slave := SLAVE_DRAM_CSR;
 189         elsif std_match(wb_master_out.adr, x"C0004---") then
 190             slave := SLAVE_ICP_0;
 191         end if;
 192
 193         -- Wishbone muxing. Defaults:
 194         wb_bram_in <= wb_master_out;
 195         wb_bram_in.cyc  <= '0';
 196         wb_uart0_in <= wb_master_out;
 197         wb_uart0_in.cyc <= '0';
 198
 199          -- Only give xics 8 bits of wb addr
 200         wb_xics0_in <= wb_master_out;
 201         wb_xics0_in.adr <= (others => '0');
 202         wb_xics0_in.adr(7 downto 0) <= wb_master_out.adr(7 downto 0);
 203         wb_xics0_in.cyc  <= '0';
 204
 205         wb_dram_in <= wb_master_out;
 206         wb_dram_in.cyc <= '0';
 207         wb_dram_csr <= '0';
 208         wb_dram_init <= '0';
 209         wb_syscon_in <= wb_master_out;
 210         wb_syscon_in.cyc <= '0';
 211         case slave is
 212         when SLAVE_BRAM =>
 213             wb_bram_in.cyc <= wb_master_out.cyc;
 214             wb_master_in <= wb_bram_out;
 215         when SLAVE_DRAM =>
 216             wb_dram_in.cyc <= wb_master_out.cyc;
 217             wb_master_in <= wb_dram_out;
 218         when SLAVE_DRAM_INIT =>
 219             wb_dram_in.cyc <= wb_master_out.cyc;
 220             wb_master_in <= wb_dram_out;
 221             wb_dram_init <= '1';
 222         when SLAVE_DRAM_CSR =>
 223             wb_dram_in.cyc <= wb_master_out.cyc;
 224             wb_master_in <= wb_dram_out;
 225             wb_dram_csr <= '1';
 226         when SLAVE_SYSCON =>
 227             wb_syscon_in.cyc <= wb_master_out.cyc;
 228             wb_master_in <= wb_syscon_out;
 229         when SLAVE_UART =>
 230             wb_uart0_in.cyc <= wb_master_out.cyc;
 231             wb_master_in <= wb_uart0_out;
 232         when SLAVE_ICP_0 =>
 233             wb_xics0_in.cyc <= wb_master_out.cyc;
 234             wb_master_in <= wb_xics0_out;
 235         when others =>
 236             wb_master_in.dat <= (others => '1');
 237             wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
 238             wb_master_in.stall <= '0';
 239         end case;
 240     end process slave_intercon;
 241
 242     -- Syscon slave
 243     syscon0: entity work.syscon
 244         generic map(
 245             HAS_UART => true,
 246             HAS_DRAM => HAS_DRAM,
 247             BRAM_SIZE => MEMORY_SIZE,
 248             DRAM_SIZE => DRAM_SIZE,
 249             CLK_FREQ => CLK_FREQ
 250         )
 251         port map(
 252             clk => system_clk,
 253             rst => rst,
 254             wishbone_in => wb_syscon_in,
 255             wishbone_out => wb_syscon_out,
 256             dram_at_0 => dram_at_0,
 257             core_reset => core_reset,
 258             soc_reset => open -- XXX TODO
 259             );
 260
 261     -- Simulated memory and UART
 262
 263     -- UART0 wishbone slave
 264     -- XXX FIXME: Need a proper wb64->wb8 adapter that
 265     --            converts SELs into low address bits and muxes
 266     --            data accordingly (either that or rejects large
 267     --            cycles).
 268     uart0: entity work.pp_soc_uart
 269         generic map(
 270             FIFO_DEPTH => 32
 271             )
 272         port map(
 273             clk => system_clk,
 274             reset => rst,
 275             txd => uart0_txd,
 276             rxd => uart0_rxd,
 277             irq => int_level_in(0),
 278             wb_adr_in => wb_uart0_in.adr(11 downto 0),
 279             wb_dat_in => wb_uart0_in.dat(7 downto 0),
 280             wb_dat_out => uart_dat8,
 281             wb_cyc_in => wb_uart0_in.cyc,
 282             wb_stb_in => wb_uart0_in.stb,
 283             wb_we_in => wb_uart0_in.we,
 284             wb_ack_out => wb_uart0_out.ack
 285             );
 286     wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
 287     wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
 288
 289     xics0: entity work.xics
 290         generic map(
 291             LEVEL_NUM => 16
 292             )
 293         port map(
 294             clk => system_clk,
 295             rst => rst,
 296             wb_in => wb_xics0_in,
 297             wb_out => wb_xics0_out,
 298             int_level_in => int_level_in,
 299             e_out => xics_to_execute1
 300             );
 301
 302     -- BRAM Memory slave
 303     bram0: entity work.wishbone_bram_wrapper
 304         generic map(
 305             MEMORY_SIZE   => MEMORY_SIZE,
 306             RAM_INIT_FILE => RAM_INIT_FILE
 307             )
 308         port map(
 309             clk => system_clk,
 310             rst => rst,
 311             wishbone_in => wb_bram_in,
 312             wishbone_out => wb_bram_out
 313             );
 314
 315     -- DMI(debug bus) <-> JTAG bridge
 316     dtm: entity work.dmi_dtm
 317         generic map(
 318             ABITS => 8,
 319             DBITS => 64
 320             )
 321         port map(
 322             sys_clk     => system_clk,
 323             sys_reset   => rst,
 324             dmi_addr    => dmi_addr,
 325             dmi_din     => dmi_din,
 326             dmi_dout    => dmi_dout,
 327             dmi_req     => dmi_req,
 328             dmi_wr      => dmi_wr,
 329             dmi_ack     => dmi_ack
 330             );
 331
 332     -- DMI interconnect
 333     dmi_intercon: process(dmi_addr, dmi_req,
 334                           dmi_wb_ack, dmi_wb_dout,
 335                           dmi_core_ack, dmi_core_dout)
 336
 337         -- DMI address map (each address is a full 64-bit register)
 338         --
 339         -- Offset:   Size:    Slave:
 340         --  0         4       Wishbone
 341         -- 10        16       Core
 342
 343         type slave_type is (SLAVE_WB,
 344                             SLAVE_CORE,
 345                             SLAVE_NONE);
 346         variable slave : slave_type;
 347     begin
 348         -- Simple address decoder
 349         slave := SLAVE_NONE;
 350         if std_match(dmi_addr, "000000--") then
 351             slave := SLAVE_WB;
 352         elsif std_match(dmi_addr, "0001----") then
 353             slave := SLAVE_CORE;
 354         end if;
 355
 356         -- DMI muxing
 357         dmi_wb_req <= '0';
 358         dmi_core_req <= '0';
 359         case slave is
 360         when SLAVE_WB =>
 361             dmi_wb_req <= dmi_req;
 362             dmi_ack <= dmi_wb_ack;
 363             dmi_din <= dmi_wb_dout;
 364         when SLAVE_CORE =>
 365             dmi_core_req <= dmi_req;
 366             dmi_ack <= dmi_core_ack;
 367             dmi_din <= dmi_core_dout;
 368         when others =>
 369             dmi_ack <= dmi_req;
 370             dmi_din <= (others => '1');
 371         end case;
 372
 373         -- SIM magic exit
 374         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
 375             stop;
 376         end if;
 377     end process;
 378
 379     -- Wishbone debug master (TODO: Add a DMI address decoder)
 380     wishbone_debug: entity work.wishbone_debug_master
 381         port map(clk => system_clk, rst => rst,
 382                  dmi_addr => dmi_addr(1 downto 0),
 383                  dmi_dout => dmi_wb_dout,
 384                  dmi_din => dmi_dout,
 385                  dmi_wr => dmi_wr,
 386                  dmi_ack => dmi_wb_ack,
 387                  dmi_req => dmi_wb_req,
 388                  wb_in => wishbone_debug_in,
 389                  wb_out => wishbone_debug_out);
 390
 391
 392 end architecture behaviour;