spi_flash_ctrl.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.wishbone_types.all;
   7
   8 entity spi_flash_ctrl is
   9     generic (
  10         -- Default config for auto-mode
  11         DEF_CLK_DIV     : natural  := 2;      -- Clock divider SCK = CLK/((CLK_DIV+1)*2)
  12         DEF_QUAD_READ   : boolean  := false;  -- Use quad read with 8 clk dummy
  13
  14         -- Dummy clocks after boot
  15         BOOT_CLOCKS     : boolean  := true;   -- Send 8 dummy clocks after boot
  16
  17         -- Number of data lines (1=MISO/MOSI, otherwise 2 or 4)
  18         DATA_LINES      : positive := 1
  19         );
  20     port (
  21         clk : in std_ulogic;
  22         rst : in std_ulogic;
  23
  24         -- Wishbone ports:
  25         wb_in  : in  wb_io_master_out;
  26         wb_out : out wb_io_slave_out;
  27
  28         -- Wishbone extra selects
  29         wb_sel_reg : in std_ulogic;
  30         wb_sel_map : in std_ulogic;
  31
  32         -- SPI port
  33         sck     : out std_ulogic;
  34         cs_n    : out std_ulogic;
  35         sdat_o  : out std_ulogic_vector(DATA_LINES-1 downto 0);
  36         sdat_oe : out std_ulogic_vector(DATA_LINES-1 downto 0);
  37         sdat_i  : in  std_ulogic_vector(DATA_LINES-1 downto 0)
  38         );
  39 end entity spi_flash_ctrl;
  40
  41 architecture rtl of spi_flash_ctrl is
  42
  43     -- Register indices
  44     constant SPI_REG_BITS       : positive := 3;
  45
  46     -- Register addresses (matches wishbone addr downto 0, ie, 4 bytes per reg)
  47     constant SPI_REG_DATA         : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "000";
  48     constant SPI_REG_CTRL         : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "001";
  49     constant SPI_REG_AUTO_CFG     : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "010";
  50     constant SPI_REG_INVALID      : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111";
  51
  52     -- Control register
  53     signal ctrl_reg    : std_ulogic_vector(15 downto 0);
  54     alias  ctrl_reset  : std_ulogic is ctrl_reg(0);
  55     alias  ctrl_cs     : std_ulogic is ctrl_reg(1);
  56     alias  ctrl_rsrv1  : std_ulogic is ctrl_reg(2);
  57     alias  ctrl_rsrv2  : std_ulogic is ctrl_reg(3);
  58     alias  ctrl_div    : std_ulogic_vector(7 downto 0) is ctrl_reg(15 downto 8);
  59
  60     -- Auto mode config register
  61     signal auto_cfg_reg     : std_ulogic_vector(29 downto 0);
  62     alias  auto_cfg_cmd     : std_ulogic_vector(7 downto 0) is auto_cfg_reg(7 downto 0);
  63     alias  auto_cfg_dummies : std_ulogic_vector(2 downto 0) is auto_cfg_reg(10 downto 8);
  64     alias  auto_cfg_mode    : std_ulogic_vector(1 downto 0) is auto_cfg_reg(12 downto 11);
  65     alias  auto_cfg_addr4   : std_ulogic                    is auto_cfg_reg(13);
  66     alias  auto_cfg_rsrv1   : std_ulogic                    is auto_cfg_reg(14);
  67     alias  auto_cfg_rsrv2   : std_ulogic                    is auto_cfg_reg(15);
  68     alias  auto_cfg_div     : std_ulogic_vector(7 downto 0) is auto_cfg_reg(23 downto 16);
  69     alias  auto_cfg_cstout  : std_ulogic_vector(5 downto 0) is auto_cfg_reg(29 downto 24);
  70
  71     -- Constants below match top 2 bits of rxtx "mode"
  72     constant SPI_AUTO_CFG_MODE_SINGLE : std_ulogic_vector(1 downto 0) := "00";
  73     constant SPI_AUTO_CFG_MODE_DUAL   : std_ulogic_vector(1 downto 0) := "10";
  74     constant SPI_AUTO_CFG_MODE_QUAD   : std_ulogic_vector(1 downto 0) := "11";
  75
  76     -- Signals to rxtx
  77     signal cmd_valid    : std_ulogic;
  78     signal cmd_clk_div  : natural range 0 to 255;
  79     signal cmd_mode     : std_ulogic_vector(2 downto 0);
  80     signal cmd_ready    : std_ulogic;
  81     signal d_clks       : std_ulogic_vector(2 downto 0);
  82     signal d_rx         : std_ulogic_vector(7 downto 0);
  83     signal d_tx         : std_ulogic_vector(7 downto 0);
  84     signal d_ack        : std_ulogic;
  85     signal bus_idle     : std_ulogic;
  86
  87     -- Latch to track that we have a pending read
  88     signal pending_read : std_ulogic;
  89
  90     -- Wishbone latches
  91     signal wb_req       : wb_io_master_out;
  92     signal wb_stash     : wb_io_master_out;
  93     signal wb_rsp       : wb_io_slave_out;
  94
  95     -- Wishbone decode
  96     signal wb_valid     : std_ulogic;
  97     signal wb_reg_valid : std_ulogic;
  98     signal wb_reg_dat_v : std_ulogic;
  99     signal wb_map_valid : std_ulogic;
 100     signal wb_reg       : std_ulogic_vector(SPI_REG_BITS-1 downto 0);
 101
 102     -- Auto mode clock counts XXX FIXME: Look at reasonable values based
 103     -- on system clock maybe ? Or make them programmable.
 104     constant CS_DELAY_ASSERT    : integer := 1;   -- CS low to cmd
 105     constant CS_DELAY_RECOVERY  : integer := 10;  -- CS high to CS low
 106     constant DEFAULT_CS_TIMEOUT : integer := 32;
 107
 108     -- Automatic mode state
 109     type auto_state_t is (AUTO_BOOT, AUTO_IDLE, AUTO_CS_ON, AUTO_CMD,
 110                           AUTO_ADR0, AUTO_ADR1, AUTO_ADR2, AUTO_ADR3,
 111                           AUTO_DUMMY,
 112                           AUTO_DAT0, AUTO_DAT1, AUTO_DAT2, AUTO_DAT3,
 113                           AUTO_DAT0_DATA, AUTO_DAT1_DATA, AUTO_DAT2_DATA, AUTO_DAT3_DATA,
 114                           AUTO_SEND_ACK, AUTO_WAIT_REQ, AUTO_RECOVERY);
 115     -- Automatic mode signals
 116     signal auto_cs        : std_ulogic;
 117     signal auto_cmd_valid : std_ulogic;
 118     signal auto_cmd_mode  : std_ulogic_vector(2 downto 0);
 119     signal auto_d_txd     : std_ulogic_vector(7 downto 0);
 120     signal auto_d_clks    : std_ulogic_vector(2 downto 0);
 121     signal auto_data_next : std_ulogic_vector(wb_out.dat'left downto 0);
 122     signal auto_cnt_next  : integer range 0 to 63;
 123     signal auto_ack       : std_ulogic;
 124     signal auto_next      : auto_state_t;
 125     signal auto_lad_next  : std_ulogic_vector(31 downto 0);
 126     signal auto_latch_adr : std_ulogic;
 127
 128     -- Automatic mode latches
 129     signal auto_data      : std_ulogic_vector(wb_out.dat'left downto 0);
 130     signal auto_cnt       : integer range 0 to 63;
 131     signal auto_state     : auto_state_t;
 132     signal auto_last_addr : std_ulogic_vector(31 downto 0);
 133
 134 begin
 135
 136     -- Instanciate low level shifter
 137     spi_rxtx: entity work.spi_rxtx
 138         generic map (
 139             DATA_LINES => DATA_LINES
 140             )
 141         port map(
 142             rst => rst,
 143             clk => clk,
 144             clk_div_i => cmd_clk_div,
 145             cmd_valid_i => cmd_valid,
 146             cmd_ready_o => cmd_ready,
 147             cmd_mode_i => cmd_mode,
 148             cmd_clks_i => d_clks,
 149             cmd_txd_i => d_tx,
 150             d_rxd_o => d_rx,
 151             d_ack_o => d_ack,
 152             bus_idle_o => bus_idle,
 153             sck => sck,
 154             sdat_o => sdat_o,
 155             sdat_oe => sdat_oe,
 156             sdat_i => sdat_i
 157             );
 158
 159     -- Valid wb command
 160     wb_valid     <= wb_req.stb and wb_req.cyc;
 161     wb_reg_valid <= wb_valid and wb_sel_reg;
 162     wb_map_valid <= wb_valid and wb_sel_map;
 163
 164     -- Register decode. For map accesses, make it look like "invalid"
 165     wb_reg       <= wb_req.adr(SPI_REG_BITS - 1 downto 0) when wb_reg_valid else SPI_REG_INVALID;
 166
 167     -- Shortcut because we test that a lot: data register access
 168     wb_reg_dat_v <= '1' when wb_reg = SPI_REG_DATA else '0';
 169
 170     -- Wishbone request -> SPI request
 171     wb_request_sync: process(clk)
 172     begin
 173         if  rising_edge(clk) then
 174             -- We need to latch whether a read is in progress to block
 175             -- a subsequent store, otherwise the acks will collide.
 176             --
 177             -- We are heavy handed and force a wait for an idle bus if
 178             -- a store is behind a load. Shouldn't happen with flashes
 179             -- in practice.
 180             --
 181             if cmd_valid = '1' and cmd_ready = '1' then
 182                 pending_read <= not wb_req.we;
 183             elsif bus_idle = '1' then
 184                 pending_read <= '0';
 185             end if;
 186         end if;
 187     end process;
 188
 189     wb_request_comb: process(all)
 190     begin
 191         if ctrl_cs = '1' then
 192             -- Data register access (see wb_request_sync)
 193             cmd_valid  <= wb_reg_dat_v and not (pending_read and wb_req.we);
 194
 195             -- Clock divider from control reg
 196             cmd_clk_div <= to_integer(unsigned(ctrl_div));
 197
 198             -- Mode based on sel
 199             if wb_req.sel = "0010" then
 200                 -- dual mode
 201                 cmd_mode <= "10" & wb_req.we;
 202                 d_clks   <= "011";
 203             elsif wb_req.sel = "0100" then
 204                 -- quad mode
 205                 cmd_mode <= "11" & wb_req.we;
 206                 d_clks   <= "001";
 207             else
 208                 -- single bit
 209                 cmd_mode <= "01" & wb_req.we;
 210                 d_clks   <= "111";
 211             end if;
 212             d_tx       <= wb_req.dat(7 downto 0);
 213             cs_n       <= not ctrl_cs;
 214         else
 215             cmd_valid   <= auto_cmd_valid;
 216             cmd_mode    <= auto_cmd_mode;
 217             cmd_clk_div <= to_integer(unsigned(auto_cfg_div));
 218             d_tx        <= auto_d_txd;
 219             d_clks      <= auto_d_clks;
 220             cs_n        <= not auto_cs;
 221         end if;
 222     end process;
 223
 224     -- Generate wishbone responses
 225     --
 226     -- Note: wb_out and wb_in should only appear in this synchronous process
 227     --
 228     -- Everything else should work on wb_req and wb_rsp
 229     wb_response_sync: process(clk)
 230     begin
 231         if rising_edge(clk) then
 232             if rst = '1' then
 233                 wb_out.ack   <= '0';
 234                 wb_out.stall <= '0';
 235                 wb_stash.cyc <= '0';
 236                 wb_stash.stb <= '0';
 237                 wb_stash.sel <= (others => '0');
 238                 wb_stash.we <= '0';
 239             else
 240                 -- Latch wb responses as well for 1 cycle. Stall is updated
 241                 -- below
 242                 wb_out <= wb_rsp;
 243
 244                 -- Implement a stash buffer. If we are stalled and stash is
 245                 -- free, fill it up. This will generate a WB stall on the
 246                 -- next cycle.
 247                 if wb_rsp.stall = '1' and wb_out.stall = '0' and
 248                     wb_in.cyc = '1' and wb_in.stb = '1' then
 249                     wb_stash <= wb_in;
 250                     wb_out.stall <= '1';
 251                 end if;
 252
 253                 -- We aren't stalled, see what we can do
 254                 if wb_rsp.stall = '0' then
 255                     if wb_out.stall = '1' then
 256                         -- Something in stash ! use it and clear stash
 257                         wb_req <= wb_stash;
 258                         wb_out.stall <= '0';
 259                     else
 260                         -- Nothing in stash, grab request from WB
 261                         if wb_in.cyc = '1' then
 262                             wb_req <= wb_in;
 263                         else
 264                             wb_req.cyc <= wb_in.cyc;
 265                             wb_req.stb <= wb_in.stb;
 266                         end if;
 267                     end if;
 268                 end if;
 269             end if;
 270         end if;
 271     end process;
 272
 273     wb_response_comb: process(all)
 274     begin
 275         -- Defaults
 276         wb_rsp.ack <= '0';
 277         wb_rsp.dat <= x"00" & d_rx & d_rx & d_rx;
 278         wb_rsp.stall   <= '0';
 279
 280         -- Depending on the access type...
 281         if wb_map_valid = '1' then
 282
 283             -- Memory map access
 284             wb_rsp.stall <= not auto_ack;  -- XXX FIXME: Allow pipelining
 285             wb_rsp.ack   <= auto_ack;
 286             wb_rsp.dat   <= auto_data;
 287
 288         elsif ctrl_cs = '1' and wb_reg = SPI_REG_DATA then
 289
 290             -- Data register in manual mode
 291             --
 292             -- Stall stores if there's a pending read to avoid
 293             -- acks colliding. Otherwise accept all accesses
 294             -- immediately if rxtx is ready.
 295             --
 296             -- Note: This must match the logic setting cmd_valid
 297             -- in wb_request_comb.
 298             --
 299             -- We also ack stores immediately when accepted. Loads
 300             -- are handled separately further down.
 301             --
 302             if wb_req.we = '1' and  pending_read = '1' then
 303                 wb_rsp.stall <= '1';
 304             else
 305                 wb_rsp.ack   <= wb_req.we and cmd_ready;
 306                 wb_rsp.stall <= not cmd_ready;
 307             end if;
 308
 309             -- Note: loads acks are handled elsewhere
 310         elsif wb_reg_valid = '1' then
 311
 312             -- Normal register access
 313             --
 314             -- Normally single cycle but ensure any auto-mode or manual
 315             -- operation is complete first
 316             --
 317             if auto_state = AUTO_IDLE and bus_idle = '1' then
 318                 wb_rsp.ack   <= '1';
 319                 wb_rsp.stall <= '0';
 320
 321                 case wb_reg is
 322                 when SPI_REG_CTRL =>
 323                     wb_rsp.dat <= (ctrl_reg'range => ctrl_reg, others => '0');
 324                 when SPI_REG_AUTO_CFG =>
 325                     wb_rsp.dat <= (auto_cfg_reg'range => auto_cfg_reg, others => '0');
 326                 when others => null;
 327                 end case;
 328             else
 329                 wb_rsp.stall <= '1';
 330             end if;
 331         end if;
 332
 333         -- For loads in manual mode, we've accepted the command early
 334         -- so none of the above connditions might be true. We thus need
 335         -- to send the ack whenever we are getting it from rxtx.
 336         --
 337         -- This shouldn't collide with any of the above acks because we hold
 338         -- normal register accesses and stores when there is a pending
 339         -- load or the bus is busy.
 340         --
 341         if ctrl_cs = '1' and d_ack = '1' then
 342             assert pending_read = '1' report "d_ack without pending read !" severity failure;
 343             wb_rsp.ack <= '1';
 344         end if;
 345     end process;
 346
 347     -- Automatic mode state machine
 348     auto_sync: process(clk)
 349     begin
 350         if rising_edge(clk) then
 351             if rst = '1' then
 352                 auto_last_addr <= (others => '0');
 353                 auto_state <= AUTO_BOOT;
 354                 auto_cnt <= 0;
 355                 auto_data  <= (others => '0');
 356             else
 357                 auto_state <= auto_next;
 358                 auto_cnt   <= auto_cnt_next;
 359                 auto_data  <= auto_data_next;
 360                 if auto_latch_adr = '1' then
 361                     auto_last_addr <= auto_lad_next;
 362                 end if;
 363             end if;
 364         end if;
 365     end process;
 366
 367     auto_comb: process(all)
 368         variable addr : std_ulogic_vector(31 downto 0);
 369         variable req_is_next : boolean;
 370
 371         function mode_to_clks(mode: std_ulogic_vector(1 downto 0)) return std_ulogic_vector is
 372         begin
 373             if mode = SPI_AUTO_CFG_MODE_QUAD then
 374                 return "001";
 375             elsif mode = SPI_AUTO_CFG_MODE_DUAL then
 376                 return "011";
 377             else
 378                 return "111";
 379             end if;
 380         end function;
 381    begin
 382         -- Default outputs
 383         auto_ack <= '0';
 384         auto_cs <= '0';
 385         auto_cmd_valid <= '0';
 386         auto_d_txd <= x"00";
 387         auto_cmd_mode <= "001";
 388         auto_d_clks <= "111";
 389         auto_latch_adr <= '0';
 390
 391         -- Default next state
 392         auto_next <= auto_state;
 393         auto_cnt_next <= auto_cnt;
 394         auto_data_next <= auto_data;
 395
 396         -- Convert wishbone address into a flash address. We mask
 397         -- off the 4 top address bits to get rid of the "f" there.
 398         addr := "00" & wb_req.adr(27 downto 0) & "00";
 399
 400         -- Calculate the next address for store & compare later
 401         auto_lad_next <= std_ulogic_vector(unsigned(addr) + 4);
 402
 403         -- Match incoming request address with next address
 404         req_is_next := addr = auto_last_addr;
 405
 406         -- XXX TODO:
 407         --  - Support < 32-bit accesses
 408
 409         -- Reset
 410         if rst = '1' or ctrl_reset = '1' then
 411             auto_cs <= '0';
 412             auto_cnt_next <= 0;
 413             auto_next <= AUTO_BOOT;
 414         else
 415             -- Run counter
 416             if auto_cnt /= 0 then
 417                 auto_cnt_next <= auto_cnt - 1;
 418             end if;
 419
 420             -- Automatic CS is set whenever state isn't IDLE or RECOVERY or BOOT
 421             if  auto_state /= AUTO_IDLE and
 422                 auto_state /= AUTO_RECOVERY and
 423                 auto_state /= AUTO_BOOT then
 424                 auto_cs <= '1';
 425             end if;
 426
 427             -- State machine
 428             case auto_state is
 429             when AUTO_BOOT =>
 430                 if BOOT_CLOCKS then
 431                     auto_cmd_valid <= '1';
 432                     if cmd_ready = '1' then
 433                         auto_next <= AUTO_IDLE;
 434                     end if;
 435                 else
 436                     auto_next <= AUTO_IDLE;
 437                 end if;
 438             when AUTO_IDLE =>
 439                 -- Access to the memory map only when manual CS isn't set
 440                 if wb_map_valid = '1' and ctrl_cs = '0' then
 441                     -- Ignore writes, we don't support them yet
 442                     if wb_req.we = '1' then
 443                         auto_ack <= '1';
 444                     else
 445                         -- Start machine with CS assertion delay
 446                         auto_next <= AUTO_CS_ON;
 447                         auto_cnt_next <= CS_DELAY_ASSERT;
 448                     end if;
 449                 end if;
 450             when AUTO_CS_ON =>
 451                 if auto_cnt = 0 then
 452                     -- CS asserted long enough, send command
 453                     auto_next <= AUTO_CMD;
 454                 end if;
 455             when AUTO_CMD =>
 456                 auto_d_txd <= auto_cfg_cmd;
 457                 auto_cmd_valid <= '1';
 458                 if cmd_ready = '1' then
 459                     if auto_cfg_addr4 = '1' then
 460                         auto_next <= AUTO_ADR3;
 461                     else
 462                         auto_next <= AUTO_ADR2;
 463                     end if;
 464                 end if;
 465             when AUTO_ADR3 =>
 466                 auto_d_txd <= addr(31 downto 24);
 467                 auto_cmd_valid <= '1';
 468                 if cmd_ready = '1' then
 469                     auto_next <= AUTO_ADR2;
 470                 end if;
 471             when AUTO_ADR2 =>
 472                 auto_d_txd <= addr(23 downto 16);
 473                 auto_cmd_valid <= '1';
 474                 if cmd_ready = '1' then
 475                     auto_next <= AUTO_ADR1;
 476                 end if;
 477             when AUTO_ADR1 =>
 478                 auto_d_txd <= addr(15 downto 8);
 479                 auto_cmd_valid <= '1';
 480                 if cmd_ready = '1' then
 481                     auto_next <= AUTO_ADR0;
 482                 end if;
 483             when AUTO_ADR0 =>
 484                 auto_d_txd <= addr(7 downto 0);
 485                 auto_cmd_valid <= '1';
 486                 if cmd_ready = '1' then
 487                     if auto_cfg_dummies = "000" then
 488                         auto_next <= AUTO_DAT0;
 489                     else
 490                         auto_next <= AUTO_DUMMY;
 491                     end if;
 492                 end if;
 493             when AUTO_DUMMY =>
 494                 auto_cmd_valid <= '1';
 495                 auto_d_clks <= auto_cfg_dummies;
 496                 if cmd_ready = '1' then
 497                     auto_next <= AUTO_DAT0;
 498                 end if;
 499             when AUTO_DAT0 =>
 500                 auto_cmd_valid <= '1';
 501                 auto_cmd_mode <= auto_cfg_mode & "0";
 502                 auto_d_clks <= mode_to_clks(auto_cfg_mode);
 503                 if cmd_ready = '1' then
 504                     auto_next <= AUTO_DAT0_DATA;
 505                 end if;
 506             when AUTO_DAT0_DATA =>
 507                 if d_ack = '1' then
 508                     auto_data_next(7 downto 0) <= d_rx;
 509                     auto_next <= AUTO_DAT1;
 510                 end if;
 511             when AUTO_DAT1 =>
 512                 auto_cmd_valid <= '1';
 513                 auto_cmd_mode <= auto_cfg_mode & "0";
 514                 auto_d_clks <= mode_to_clks(auto_cfg_mode);
 515                 if cmd_ready = '1' then
 516                     auto_next <= AUTO_DAT1_DATA;
 517                 end if;
 518             when AUTO_DAT1_DATA =>
 519                 if d_ack = '1' then
 520                     auto_data_next(15 downto 8) <= d_rx;
 521                     auto_next <= AUTO_DAT2;
 522                 end if;
 523             when AUTO_DAT2 =>
 524                 auto_cmd_valid <= '1';
 525                 auto_cmd_mode <= auto_cfg_mode & "0";
 526                 auto_d_clks <= mode_to_clks(auto_cfg_mode);
 527                 if cmd_ready = '1' then
 528                     auto_next <= AUTO_DAT2_DATA;
 529                 end if;
 530             when AUTO_DAT2_DATA =>
 531                 if d_ack = '1' then
 532                     auto_data_next(23 downto 16) <= d_rx;
 533                     auto_next <= AUTO_DAT3;
 534                 end if;
 535             when AUTO_DAT3 =>
 536                 auto_cmd_valid <= '1';
 537                 auto_cmd_mode <= auto_cfg_mode & "0";
 538                 auto_d_clks <= mode_to_clks(auto_cfg_mode);
 539                 if cmd_ready = '1' then
 540                     auto_next <= AUTO_DAT3_DATA;
 541                 end if;
 542             when AUTO_DAT3_DATA =>
 543                 if d_ack = '1' then
 544                     auto_data_next(31 downto 24) <= d_rx;
 545                     auto_next <= AUTO_SEND_ACK;
 546                     auto_latch_adr <= '1';
 547                 end if;
 548             when AUTO_SEND_ACK =>
 549                 auto_ack <= '1';
 550                 auto_cnt_next <= to_integer(unsigned(auto_cfg_cstout));
 551                 auto_next <= AUTO_WAIT_REQ;
 552             when AUTO_WAIT_REQ =>
 553                 -- Incoming bus request we can take ? Otherwise do we need
 554                 -- to cancel the wait ?
 555                 if wb_map_valid = '1' and req_is_next and wb_req.we = '0' then
 556                     auto_next <= AUTO_DAT0;
 557                 elsif wb_map_valid = '1' or wb_reg_valid = '1' or auto_cnt = 0 then
 558                     -- This means we can drop the CS right on the next clock.
 559                     -- We make the assumption here that the two cycles min
 560                     -- spent in AUTO_SEND_ACK and AUTO_WAIT_REQ are long enough
 561                     -- to deassert CS. If that doesn't hold true in the future,
 562                     -- add another state.
 563                     auto_cnt_next <= CS_DELAY_RECOVERY;
 564                     auto_next <= AUTO_RECOVERY;
 565                 end if;
 566             when AUTO_RECOVERY =>
 567                 if auto_cnt = 0 then
 568                     auto_next <= AUTO_IDLE;
 569                 end if;
 570             end case;
 571         end if;
 572     end process;
 573
 574     -- Register write sync machine
 575     reg_write: process(clk)
 576         function reg_wr(r : in std_ulogic_vector;
 577                         w : in wb_io_master_out) return std_ulogic_vector is
 578             variable b : natural range 0 to 31;
 579             variable t : std_ulogic_vector(r'range);
 580         begin
 581             t := r;
 582             for i in r'range loop
 583                 if w.sel(i/8) = '1' then
 584                     t(i) := w.dat(i);
 585                 end if;
 586             end loop;
 587             return t;
 588         end function;
 589     begin
 590         if rising_edge(clk) then
 591             -- Reset auto-clear
 592             if rst = '1' or ctrl_reset = '1' then
 593                 ctrl_reset       <= '0';
 594                 ctrl_cs          <= '0';
 595                 ctrl_rsrv1       <= '0';
 596                 ctrl_rsrv2       <= '0';
 597                 ctrl_div         <= std_ulogic_vector(to_unsigned(DEF_CLK_DIV, 8));
 598                 if DEF_QUAD_READ then
 599                     auto_cfg_cmd     <= x"6b";
 600                     auto_cfg_dummies <= "111";
 601                     auto_cfg_mode    <= SPI_AUTO_CFG_MODE_QUAD;
 602                 else
 603                     auto_cfg_cmd     <= x"03";
 604                     auto_cfg_dummies <= "000";
 605                     auto_cfg_mode    <= SPI_AUTO_CFG_MODE_SINGLE;
 606                 end if;
 607                 auto_cfg_addr4   <= '0';
 608                 auto_cfg_rsrv1   <= '0';
 609                 auto_cfg_rsrv2   <= '0';
 610                 auto_cfg_div     <= std_ulogic_vector(to_unsigned(DEF_CLK_DIV, 8));
 611                 auto_cfg_cstout  <= std_ulogic_vector(to_unsigned(DEFAULT_CS_TIMEOUT, 6));
 612             end if;
 613
 614             if wb_reg_valid = '1' and wb_req.we = '1' and auto_state = AUTO_IDLE and bus_idle = '1' then
 615                 if wb_reg = SPI_REG_CTRL then
 616                     ctrl_reg     <= reg_wr(ctrl_reg, wb_req);
 617                 end if;
 618                 if wb_reg = SPI_REG_AUTO_CFG then
 619                     auto_cfg_reg <= reg_wr(auto_cfg_reg, wb_req);
 620                 end if;
 621             end if;
 622         end if;
 623     end process;
 624
 625 end architecture;
 626