src/bigint_presentation_code/_tests/test_compiler_ir2.py

   1 import unittest
   2
   3 from bigint_presentation_code.compiler_ir2 import (GPR_SIZE_IN_BYTES, Fn,
   4                                                    OpKind, PreRASimState,
   5                                                    SSAVal)
   6
   7
   8 class TestCompilerIR(unittest.TestCase):
   9     maxDiff = None
  10
  11     def make_add_fn(self):
  12         # type: () -> tuple[Fn, SSAVal]
  13         fn = Fn()
  14         op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
  15         arg = op0.outputs[0]
  16         MAXVL = 32
  17         op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
  18         vl = op1.outputs[0]
  19         op2 = fn.append_new_op(
  20             OpKind.SvLd, inputs=[arg, vl], immediates=[0], maxvl=MAXVL,
  21             name="ld")
  22         a = op2.outputs[0]
  23         op3 = fn.append_new_op(
  24             OpKind.SvLI, inputs=[vl], immediates=[0], maxvl=MAXVL, name="li")
  25         b = op3.outputs[0]
  26         op4 = fn.append_new_op(OpKind.SetCA, name="ca")
  27         ca = op4.outputs[0]
  28         op5 = fn.append_new_op(
  29             OpKind.SvAddE, inputs=[a, b, ca, vl], maxvl=MAXVL, name="add")
  30         s = op5.outputs[0]
  31         fn.append_new_op(
  32             OpKind.SvStd, inputs=[s, arg, vl], immediates=[0], maxvl=MAXVL,
  33             name="st")
  34         return fn, arg
  35
  36     def test_repr(self):
  37         fn, _arg = self.make_add_fn()
  38         self.assertEqual([repr(i) for i in fn.ops], [
  39             "Op(kind=OpKind.FuncArgR3, "
  40             "inputs=[], "
  41             "immediates=[], "
  42             "outputs=(<arg#0: <I64>>,), name='arg')",
  43             "Op(kind=OpKind.SetVLI, "
  44             "inputs=[], "
  45             "immediates=[32], "
  46             "outputs=(<vl#0: <VL_MAXVL>>,), name='vl')",
  47             "Op(kind=OpKind.SvLd, "
  48             "inputs=[<arg#0: <I64>>, <vl#0: <VL_MAXVL>>], "
  49             "immediates=[0], "
  50             "outputs=(<ld#0: <I64*32>>,), name='ld')",
  51             "Op(kind=OpKind.SvLI, "
  52             "inputs=[<vl#0: <VL_MAXVL>>], "
  53             "immediates=[0], "
  54             "outputs=(<li#0: <I64*32>>,), name='li')",
  55             "Op(kind=OpKind.SetCA, "
  56             "inputs=[], "
  57             "immediates=[], "
  58             "outputs=(<ca#0: <CA>>,), name='ca')",
  59             "Op(kind=OpKind.SvAddE, "
  60             "inputs=[<ld#0: <I64*32>>, <li#0: <I64*32>>, <ca#0: <CA>>, "
  61             "<vl#0: <VL_MAXVL>>], "
  62             "immediates=[], "
  63             "outputs=(<add#0: <I64*32>>, <add#1: <CA>>), name='add')",
  64             "Op(kind=OpKind.SvStd, "
  65             "inputs=[<add#0: <I64*32>>, <arg#0: <I64>>, <vl#0: <VL_MAXVL>>], "
  66             "immediates=[0], "
  67             "outputs=(), name='st')",
  68         ])
  69
  70     def test_pre_ra_insert_copies(self):
  71         fn, _arg = self.make_add_fn()
  72         fn.pre_ra_insert_copies()
  73         self.assertEqual([repr(i) for i in fn.ops], [
  74             "Op(kind=OpKind.FuncArgR3, "
  75             "inputs=[], "
  76             "immediates=[], "
  77             "outputs=(<arg#0: <I64>>,), name='arg')",
  78             "Op(kind=OpKind.CopyFromReg, "
  79             "inputs=[<arg#0: <I64>>], "
  80             "immediates=[], "
  81             "outputs=(<2#0: <I64>>,), name='2')",
  82             "Op(kind=OpKind.SetVLI, "
  83             "inputs=[], "
  84             "immediates=[32], "
  85             "outputs=(<vl#0: <VL_MAXVL>>,), name='vl')",
  86             "Op(kind=OpKind.CopyToReg, "
  87             "inputs=[<2#0: <I64>>], "
  88             "immediates=[], "
  89             "outputs=(<3#0: <I64>>,), name='3')",
  90             "Op(kind=OpKind.SvLd, "
  91             "inputs=[<3#0: <I64>>, <vl#0: <VL_MAXVL>>], "
  92             "immediates=[0], "
  93             "outputs=(<ld#0: <I64*32>>,), name='ld')",
  94             "Op(kind=OpKind.SetVLI, "
  95             "inputs=[], "
  96             "immediates=[32], "
  97             "outputs=(<4#0: <VL_MAXVL>>,), name='4')",
  98             "Op(kind=OpKind.VecCopyFromReg, "
  99             "inputs=[<ld#0: <I64*32>>, <4#0: <VL_MAXVL>>], "
 100             "immediates=[], "
 101             "outputs=(<5#0: <I64*32>>,), name='5')",
 102             "Op(kind=OpKind.SvLI, "
 103             "inputs=[<vl#0: <VL_MAXVL>>], "
 104             "immediates=[0], "
 105             "outputs=(<li#0: <I64*32>>,), name='li')",
 106             "Op(kind=OpKind.SetVLI, "
 107             "inputs=[], "
 108             "immediates=[32], "
 109             "outputs=(<6#0: <VL_MAXVL>>,), name='6')",
 110             "Op(kind=OpKind.VecCopyFromReg, "
 111             "inputs=[<li#0: <I64*32>>, <6#0: <VL_MAXVL>>], "
 112             "immediates=[], "
 113             "outputs=(<7#0: <I64*32>>,), name='7')",
 114             "Op(kind=OpKind.SetCA, "
 115             "inputs=[], "
 116             "immediates=[], "
 117             "outputs=(<ca#0: <CA>>,), name='ca')",
 118             "Op(kind=OpKind.SetVLI, "
 119             "inputs=[], "
 120             "immediates=[32], "
 121             "outputs=(<8#0: <VL_MAXVL>>,), name='8')",
 122             "Op(kind=OpKind.VecCopyToReg, "
 123             "inputs=[<5#0: <I64*32>>, <8#0: <VL_MAXVL>>], "
 124             "immediates=[], "
 125             "outputs=(<9#0: <I64*32>>,), name='9')",
 126             "Op(kind=OpKind.SetVLI, "
 127             "inputs=[], "
 128             "immediates=[32], "
 129             "outputs=(<10#0: <VL_MAXVL>>,), name='10')",
 130             "Op(kind=OpKind.VecCopyToReg, "
 131             "inputs=[<7#0: <I64*32>>, <10#0: <VL_MAXVL>>], "
 132             "immediates=[], "
 133             "outputs=(<11#0: <I64*32>>,), name='11')",
 134             "Op(kind=OpKind.SvAddE, "
 135             "inputs=[<9#0: <I64*32>>, <11#0: <I64*32>>, <ca#0: <CA>>, "
 136             "<vl#0: <VL_MAXVL>>], "
 137             "immediates=[], "
 138             "outputs=(<add#0: <I64*32>>, <add#1: <CA>>), name='add')",
 139             "Op(kind=OpKind.SetVLI, "
 140             "inputs=[], "
 141             "immediates=[32], "
 142             "outputs=(<12#0: <VL_MAXVL>>,), name='12')",
 143             "Op(kind=OpKind.VecCopyFromReg, "
 144             "inputs=[<add#0: <I64*32>>, <12#0: <VL_MAXVL>>], "
 145             "immediates=[], "
 146             "outputs=(<13#0: <I64*32>>,), name='13')",
 147             "Op(kind=OpKind.SetVLI, "
 148             "inputs=[], "
 149             "immediates=[32], "
 150             "outputs=(<14#0: <VL_MAXVL>>,), name='14')",
 151             "Op(kind=OpKind.VecCopyToReg, "
 152             "inputs=[<13#0: <I64*32>>, <14#0: <VL_MAXVL>>], "
 153             "immediates=[], "
 154             "outputs=(<15#0: <I64*32>>,), name='15')",
 155             "Op(kind=OpKind.CopyToReg, "
 156             "inputs=[<2#0: <I64>>], "
 157             "immediates=[], "
 158             "outputs=(<16#0: <I64>>,), name='16')",
 159             "Op(kind=OpKind.SvStd, "
 160             "inputs=[<15#0: <I64*32>>, <16#0: <I64>>, <vl#0: <VL_MAXVL>>], "
 161             "immediates=[0], "
 162             "outputs=(), name='st')",
 163         ])
 164
 165     def test_sim(self):
 166         fn, arg = self.make_add_fn()
 167         addr = 0x100
 168         state = PreRASimState(ssa_vals={arg: (addr,)}, memory={})
 169         state.store(addr=addr, value=0xffffffff_ffffffff,
 170                     size_in_bytes=GPR_SIZE_IN_BYTES)
 171         state.store(addr=addr + GPR_SIZE_IN_BYTES, value=0xabcdef01_23456789,
 172                     size_in_bytes=GPR_SIZE_IN_BYTES)
 173         self.assertEqual(
 174             repr(state),
 175             "PreRASimState(ssa_vals={<arg#0: <I64>>: (0x100,)}, memory={\n"
 176             "0x00100: <0xffffffffffffffff>,\n"
 177             "0x00108: <0xabcdef0123456789>})")
 178         fn.pre_ra_sim(state)
 179         self.assertEqual(
 180             repr(state),
 181             "PreRASimState(ssa_vals={\n"
 182             "<arg#0: <I64>>: (0x100,),\n"
 183             "<vl#0: <VL_MAXVL>>: (0x20,),\n"
 184             "<ld#0: <I64*32>>: (\n"
 185             "    0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n"
 186             "    0x0, 0x0, 0x0, 0x0,\n"
 187             "    0x0, 0x0, 0x0, 0x0,\n"
 188             "    0x0, 0x0, 0x0, 0x0,\n"
 189             "    0x0, 0x0, 0x0, 0x0,\n"
 190             "    0x0, 0x0, 0x0, 0x0,\n"
 191             "    0x0, 0x0, 0x0, 0x0,\n"
 192             "    0x0, 0x0, 0x0, 0x0),\n"
 193             "<li#0: <I64*32>>: (\n"
 194             "    0x0, 0x0, 0x0, 0x0,\n"
 195             "    0x0, 0x0, 0x0, 0x0,\n"
 196             "    0x0, 0x0, 0x0, 0x0,\n"
 197             "    0x0, 0x0, 0x0, 0x0,\n"
 198             "    0x0, 0x0, 0x0, 0x0,\n"
 199             "    0x0, 0x0, 0x0, 0x0,\n"
 200             "    0x0, 0x0, 0x0, 0x0,\n"
 201             "    0x0, 0x0, 0x0, 0x0),\n"
 202             "<ca#0: <CA>>: (0x1,),\n"
 203             "<add#0: <I64*32>>: (\n"
 204             "    0x0, 0xabcdef012345678a, 0x0, 0x0,\n"
 205             "    0x0, 0x0, 0x0, 0x0,\n"
 206             "    0x0, 0x0, 0x0, 0x0,\n"
 207             "    0x0, 0x0, 0x0, 0x0,\n"
 208             "    0x0, 0x0, 0x0, 0x0,\n"
 209             "    0x0, 0x0, 0x0, 0x0,\n"
 210             "    0x0, 0x0, 0x0, 0x0,\n"
 211             "    0x0, 0x0, 0x0, 0x0),\n"
 212             "<add#1: <CA>>: (0x0,),\n"
 213             "}, memory={\n"
 214             "0x00100: <0x0000000000000000>,\n"
 215             "0x00108: <0xabcdef012345678a>,\n"
 216             "0x00110: <0x0000000000000000>,\n"
 217             "0x00118: <0x0000000000000000>,\n"
 218             "0x00120: <0x0000000000000000>,\n"
 219             "0x00128: <0x0000000000000000>,\n"
 220             "0x00130: <0x0000000000000000>,\n"
 221             "0x00138: <0x0000000000000000>,\n"
 222             "0x00140: <0x0000000000000000>,\n"
 223             "0x00148: <0x0000000000000000>,\n"
 224             "0x00150: <0x0000000000000000>,\n"
 225             "0x00158: <0x0000000000000000>,\n"
 226             "0x00160: <0x0000000000000000>,\n"
 227             "0x00168: <0x0000000000000000>,\n"
 228             "0x00170: <0x0000000000000000>,\n"
 229             "0x00178: <0x0000000000000000>,\n"
 230             "0x00180: <0x0000000000000000>,\n"
 231             "0x00188: <0x0000000000000000>,\n"
 232             "0x00190: <0x0000000000000000>,\n"
 233             "0x00198: <0x0000000000000000>,\n"
 234             "0x001a0: <0x0000000000000000>,\n"
 235             "0x001a8: <0x0000000000000000>,\n"
 236             "0x001b0: <0x0000000000000000>,\n"
 237             "0x001b8: <0x0000000000000000>,\n"
 238             "0x001c0: <0x0000000000000000>,\n"
 239             "0x001c8: <0x0000000000000000>,\n"
 240             "0x001d0: <0x0000000000000000>,\n"
 241             "0x001d8: <0x0000000000000000>,\n"
 242             "0x001e0: <0x0000000000000000>,\n"
 243             "0x001e8: <0x0000000000000000>,\n"
 244             "0x001f0: <0x0000000000000000>,\n"
 245             "0x001f8: <0x0000000000000000>})")
 246
 247
 248 if __name__ == "__main__":
 249     unittest.main()