bd81d522df636e789a67f01cd337cb0c76ff478f
[pinmux.git] / src / bsv / Makefile.template
1 ### Makefile for the cclass project
2
3 TOP_MODULE:=mkSoc
4 TOP_FILE:=soc.bsv
5 TOP_DIR:=./
6 WORKING_DIR := $(shell pwd)
7
8 BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
9 BSVINCDIR:= $(BSVINCDIR):../../../src/core/src/core
10 BSVINCDIR:= $(BSVINCDIR):../../../src/core/src/lib
11 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/core
12 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/uncore/axi4
13 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/uncore/axi4lite
14 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/uncore/debug
15 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/lib
16 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/gpio
17 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/rgbttl
18 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/i2c
19 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/mux
20 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/plic
21 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/pwm
22 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/qspi
23 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/spi
24 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/sdmmc
25 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/flexbus
26 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/jtagdtm
27 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/uart
28
29 default: gen_verilog
30
31 check-blue:
32 @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi;
33
34 ###### Setting the variables for bluespec compile #$############################
35 BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules
36 BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires
37 VERILOGDIR:=./verilog/
38 BSVBUILDDIR:=./bsv_build/
39 BSVOUTDIR:=./bin
40 ################################################################################
41
42 ########## BSIM COMPILE, LINK AND SIMULATE TARGETS ##########################
43 .PHONY: check-restore
44 check-restore:
45 @if [ "$(define_macros)" != "$(old_define_macros)" ]; then make clean ; fi;
46
47 .PHONY: gen_verilog
48 gen_verilog: check-restore check-blue
49 @echo Compiling mkTbSoc in Verilog for simulations ...
50 @mkdir -p $(BSVBUILDDIR);
51 @mkdir -p $(VERILOGDIR);
52 bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
53 @echo Compilation finished
54
55 #############################################################################
56
57 .PHONY: clean
58 clean:
59 rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl*
60 rm -rf verilog obj_dir bsv_src