3 This BSV file has been generated by the PinMux tool available at:
4 https://bitbucket.org/casl/pinmux.
6 Authors: Neel Gala, Luke
7 Date of generation: Mon Jul 16 12:11:50 2018
12 interface MuxSelectionLines;
14 // declare the method which will capture the user pin-mux
15 // selection values.The width of the input is dependent on the number
16 // of muxes happening per IO. For now we have a generalized width
17 // where each IO will have the same number of muxes.
18 method Action cell0_mux (Bit#(2) in);
19 method Action cell1_mux (Bit#(2) in);
20 method Action cell2_mux (Bit#(2) in);
25 // declare the interface to the IO cells.
26 // Each IO cell will have 1 input field (output from pin mux)
27 // and an output and out-enable field (input to pinmux)
28 // interface declaration between IO-0 and pinmux
29 (*always_ready,always_enabled*) method Bit#(1) io0_cell_out;
30 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
31 (*always_ready,always_enabled,result="io"*) method
32 Action io0_cell_in (Bit#(1) in);
33 // interface declaration between IO-1 and pinmux
34 (*always_ready,always_enabled*) method Bit#(1) io1_cell_out;
35 (*always_ready,always_enabled*) method Bit#(1) io1_cell_outen;
36 (*always_ready,always_enabled,result="io"*) method
37 Action io1_cell_in (Bit#(1) in);
38 // interface declaration between IO-2 and pinmux
39 (*always_ready,always_enabled*) method Bit#(1) io2_cell_out;
40 (*always_ready,always_enabled*) method Bit#(1) io2_cell_outen;
41 (*always_ready,always_enabled,result="io"*) method
42 Action io2_cell_in (Bit#(1) in);
46 interface PeripheralSide;
47 // declare the interface to the peripherals
48 // Each peripheral's function will be either an input, output
49 // or be bi-directional. an input field will be an output from the
50 // peripheral and an output field will be an input to the peripheral.
51 // Bi-directional functions also have an output-enable (which
52 // again comes *in* from the peripheral)
53 // interface declaration between UART-0 and pinmux
54 (*always_ready,always_enabled*) method Action uart_tx (Bit#(1) in);
55 (*always_ready,always_enabled*) method Bit#(1) uart_rx;
56 // interface declaration between GPIOA-0 and pinmux
57 (*always_ready,always_enabled*) method Action gpioa_a0_out (Bit#(1) in);
58 (*always_ready,always_enabled*) method Action gpioa_a0_outen (Bit#(1) in);
59 (*always_ready,always_enabled*) method Bit#(1) gpioa_a0_in;
60 (*always_ready,always_enabled*) method Action gpioa_a1_out (Bit#(1) in);
61 (*always_ready,always_enabled*) method Action gpioa_a1_outen (Bit#(1) in);
62 (*always_ready,always_enabled*) method Bit#(1) gpioa_a1_in;
63 (*always_ready,always_enabled*) method Action gpioa_a2_out (Bit#(1) in);
64 (*always_ready,always_enabled*) method Action gpioa_a2_outen (Bit#(1) in);
65 (*always_ready,always_enabled*) method Bit#(1) gpioa_a2_in;
66 // interface declaration between TWI-0 and pinmux
67 (*always_ready,always_enabled*) method Action twi_sda_out (Bit#(1) in);
68 (*always_ready,always_enabled*) method Action twi_sda_outen (Bit#(1) in);
69 (*always_ready,always_enabled*) method Bit#(1) twi_sda_in;
70 (*always_ready,always_enabled*) method Action twi_scl_out (Bit#(1) in);
71 (*always_ready,always_enabled*) method Action twi_scl_outen (Bit#(1) in);
72 (*always_ready,always_enabled*) method Bit#(1) twi_scl_in;
77 // this interface controls how each IO cell is routed. setting
78 // any given IO cell's mux control value will result in redirection
79 // of not just the input or output to different peripheral functions
80 // but also the *direction* control - if appropriate - as well.
81 interface MuxSelectionLines mux_lines;
83 // this interface contains the inputs, outputs and direction-control
84 // lines for all peripherals. GPIO is considered to also be just
85 // a peripheral because it also has in, out and direction-control.
86 interface PeripheralSide peripheral_side;
88 // this interface is to be linked to the individual IO cells.
89 // if looking at a "non-muxed" GPIO design, basically the
90 // IO cell input, output and direction-control wires are cut
91 // (giving six pairs of dangling wires, named left and right)
92 // these iocells are routed in their place on one side ("left")
93 // and the matching *GPIO* peripheral interfaces in/out/dir
94 // connect to the OTHER side ("right"). the result is that
95 // the muxer settings end up controlling the routing of where
96 // the I/O from the IOcell actually goes.
97 interface IOCellSide iocell_side;
100 //(*no_default_reset*)
101 //(*no_default_clock*)
102 module mkpinmux(Ifc_pinmux);
105 //default_clock no_clock;
107 // the followins wires capture the pin-mux selection
108 // values for each mux assigned to a CELL
110 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
111 Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
112 Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
113 // following wires capture signals to IO CELL if io-0 is
115 Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
116 Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
117 Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
119 // following wires capture signals to IO CELL if io-1 is
121 Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
122 Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
123 Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
125 // following wires capture signals to IO CELL if io-2 is
127 Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
128 Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
129 Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
131 // following wires capture signals to IO CELL if uart-0 is
133 Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
134 Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
136 // following wires capture signals to IO CELL if gpioa-0 is
138 Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
139 Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
140 Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
141 Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
142 Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
143 Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
144 Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
145 Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
146 Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
148 // following wires capture signals to IO CELL if twi-0 is
150 Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
151 Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
152 Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
153 Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
154 Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
155 Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
158 /*====== This where the muxing starts for each io-cell======*/
159 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
160 // output muxer for cell idx 0
162 wrcell0_mux==0?wrgpioa_a0_out:
163 wrcell0_mux==1?wruart_tx:
164 wrcell0_mux==2?val0: // unused
167 // outen muxer for cell idx 0
169 wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
170 wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
171 wrcell0_mux==2?val0: // unused
172 wrtwi_sda_outen; // bi-directional
174 // priority-in-muxer for cell idx 0
175 rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
176 wrgpioa_a0_in<=cell0_mux_in;
179 rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
180 wrtwi_sda_in<=cell0_mux_in;
183 // output muxer for cell idx 1
185 wrcell1_mux==0?wrgpioa_a1_out:
186 wrcell1_mux==1?val0: // uart_rx is an input
187 wrcell1_mux==2?wrtwi_sda_out:
190 // outen muxer for cell idx 1
192 wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
193 wrcell1_mux==1?val0: // uart_rx is an input
194 wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
197 // priority-in-muxer for cell idx 1
198 rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
199 wrgpioa_a1_in<=cell1_mux_in;
202 rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
203 wruart_rx<=cell1_mux_in;
206 rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
207 wrtwi_sda_in<=cell1_mux_in;
210 // output muxer for cell idx 2
212 wrcell2_mux==0?wrgpioa_a2_out:
213 wrcell2_mux==1?val0: // unused
214 wrcell2_mux==2?wrtwi_scl_out:
217 // outen muxer for cell idx 2
219 wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
220 wrcell2_mux==1?val0: // unused
221 wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
224 // priority-in-muxer for cell idx 2
225 rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
226 wrgpioa_a2_in<=cell2_mux_in;
229 rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
230 wrtwi_scl_in<=cell2_mux_in;
234 /*=========================================*/
238 /*============================================================*/
240 interface mux_lines = interface MuxSelectionLines
242 method Action cell0_mux(Bit#(2) in);
246 method Action cell1_mux(Bit#(2) in);
250 method Action cell2_mux(Bit#(2) in);
255 interface iocell_side = interface IOCellSide
257 method io0_cell_out=cell0_mux_out;
258 method io0_cell_outen=cell0_mux_outen;
259 method Action io0_cell_in(Bit#(1) in);
263 method io1_cell_out=cell1_mux_out;
264 method io1_cell_outen=cell1_mux_outen;
265 method Action io1_cell_in(Bit#(1) in);
269 method io2_cell_out=cell2_mux_out;
270 method io2_cell_outen=cell2_mux_outen;
271 method Action io2_cell_in(Bit#(1) in);
276 interface peripheral_side = interface PeripheralSide
278 method Action uart_tx(Bit#(1) in);
281 method uart_rx=wruart_rx;
283 method Action gpioa_a0_out(Bit#(1) in);
286 method Action gpioa_a0_outen(Bit#(1) in);
287 wrgpioa_a0_outen<=in;
289 method gpioa_a0_in=wrgpioa_a0_in;
290 method Action gpioa_a1_out(Bit#(1) in);
293 method Action gpioa_a1_outen(Bit#(1) in);
294 wrgpioa_a1_outen<=in;
296 method gpioa_a1_in=wrgpioa_a1_in;
297 method Action gpioa_a2_out(Bit#(1) in);
300 method Action gpioa_a2_outen(Bit#(1) in);
301 wrgpioa_a2_outen<=in;
303 method gpioa_a2_in=wrgpioa_a2_in;
305 method Action twi_sda_out(Bit#(1) in);
308 method Action twi_sda_outen(Bit#(1) in);
311 method twi_sda_in=wrtwi_sda_in;
312 method Action twi_scl_out(Bit#(1) in);
315 method Action twi_scl_outen(Bit#(1) in);
318 method twi_scl_in=wrtwi_scl_in;