src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /*====== AXI4 Lite slave declarations =======*/
  14
  15 {3}
  16         /*===========================*/
  17         /*=== package imports ===*/
  18         import Clocks::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Connectable::*;
  22         import Vector::*;
  23         import FIFO::*;
  24         /*=======================*/
  25         /*===== Import the slow peripherals ====*/
  26 {0}
  27     `ifdef CLINT
  28         import clint::*;
  29     `endif
  30     `ifdef PLIC
  31         import plic             ::*;
  32     `endif
  33         `ifdef AXIEXP
  34                 import axiexpansion     ::*;
  35         `endif
  36         /*=====================================*/
  37
  38         /*===== interface declaration =====*/
  39         interface SP_ios;
  40 {1}
  41                 `ifdef AXIEXP
  42                         interface Get#(Bit#(67)) axiexp1_out;
  43                         interface Put#(Bit#(67)) axiexp1_in;
  44                 `endif
  45         endinterface
  46         interface Ifc_slow_peripherals;
  47                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  48                 interface SP_ios slow_ios;
  49     method Action external_int(Bit#(32) in);
  50                 `ifdef CLINT
  51                         method Bit#(1) msip_int;
  52                         method Bit#(1) mtip_int;
  53                         method Bit#(`Reg_width) mtime;
  54                 `endif
  55                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  56     interface IOCellSide iocell_side; // mandatory interface
  57         endinterface
  58         /*================================*/
  59
  60         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  61                      fn_address_mapping (Bit#(`PADDR) addr);
  62                 `ifdef CLINT
  63                         if(addr>=`ClintBase && addr<=`ClintEnd)
  64                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  65                         else
  66                 `endif
  67                 `ifdef PLIC
  68                         if(addr>=`PLICBase && addr<=`PLICEnd)
  69                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  70                         else
  71                 `endif
  72                 `ifdef AXIEXP
  73                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  74                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  75                         else
  76                 `endif
  77 {4}
  78                         return tuple2(False,?);
  79         endfunction
  80
  81         (*synthesize*)
  82         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  83                                Clock uart_clock, Reset uart_reset
  84                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  85                               )(Ifc_slow_peripherals);
  86                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  87                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  88
  89                 /*======= Module declarations for each peripheral =======*/
  90 {5}
  91                 `ifdef CLINT
  92                         Ifc_clint                               clint                           <- mkclint();
  93                 `endif
  94                 `ifdef PLIC
  95                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  96          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  97                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
  98                 `endif
  99                 `ifdef AXIEXP
 100                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 101                 `endif
 102     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 103     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 104                 /*=======================================================*/
 105
 106         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)
 107             slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 108                 Ifc_AXI4Lite_AXI4_Bridge
 109             bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 110
 111                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 112                 /*======= Slave connections to AXI4Lite fabric =========*/
 113 {6}
 114                 `ifdef CLINT
 115                         mkConnection (slow_fabric.v_to_slaves
 116                     [fromInteger(valueOf(CLINT_slave_num))],
 117                     clint.axi4_slave);
 118                 `endif
 119                 `ifdef PLIC
 120                         mkConnection (slow_fabric.v_to_slaves
 121                     [fromInteger(valueOf(Plic_slave_num))],
 122                     plic.axi4_slave_plic); //
 123                 `endif
 124                 `ifdef AXIEXP
 125                 mkConnection (slow_fabric.v_to_slaves
 126                     [fromInteger(valueOf(AxiExp1_slave_num))],
 127                     axiexp1.axi_slave); //
 128                 `endif
 129
 130     /*========== pinmux connections ============*/
 131 {7}
 132     rule connect_i2c0_scl;
 133       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 134       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 135     endrule
 136     rule connect_i2c0_scl_in;
 137       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 138     endrule
 139     rule connect_i2c0_sda;
 140       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 141       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 142     endrule
 143     rule connect_i2c0_sda_in;
 144       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 145     endrule
 146     rule connect_uart1tx;
 147       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 148     endrule
 149     rule connect_uart1rx;
 150       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 151     endrule
 152     rule connect_gpioa;
 153       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 154       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 155       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 156       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 157       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 158       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 159                 Vector#(3,Bit#(1)) temp;
 160                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 161                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 162                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 163       gpioa.func.gpio_in(temp);
 164     endrule
 165     for(Integer i=0;i<32;i=i+ 1)begin
 166       rule connect_int_to_plic(wr_interrupt[i]==1);
 167                                 ff_gateway_queue[i].enq(1);
 168                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 169       endrule
 170     end
 171     rule rl_completion_msg_from_plic;
 172                   let id <- plic.intrpt_completion;
 173       interrupt_id <= id;
 174       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 175                 endrule
 176
 177     for(Integer i=0; i <32; i=i+1) begin
 178             rule deq_gateway_queue;
 179                     if(interrupt_id==fromInteger(i)) begin
 180                             ff_gateway_queue[i].deq;
 181           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 182         end
 183       endrule
 184     end
 185     /* for connectin inputs from pinmux as itnerrupts
 186       rule connect_pinmux_eint;
 187         wr_interrupt<= pinmux.peripheral_side.eint_input;
 188       endrule
 189     */
 190     // NEEL EDIT OVER
 191                 /*=======================================================*/
 192                 /*=================== PLIC Connections ==================== */
 193                 `ifdef PLIC_main
 194                         /*TODO DMA interrupt need to be connected to the plic
 195                         for(Integer i=1; i<8; i=i+1) begin
 196          `ifdef DMA
 197              rule rl_connect_dma_interrupts_to_plic;
 198                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 199                                                 ff_gateway_queue[i].enq(1);
 200                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 201                                         end
 202              endrule
 203           `else
 204              rule rl_connect_dma_interrupts_to_plic;
 205                  ff_gateway_queue[i].enq(0);
 206              endrule
 207           `endif
 208          end
 209                         */
 210          rule rl_connect_i2c0_to_plic;
 211                                 `ifdef I2C0
 212                                         if(i2c0.isint()==1'b1) begin
 213                                                 ff_gateway_queue[8].enq(1);
 214                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 215                                         end
 216                                 `else
 217                                         ff_gateway_queue[8].enq(0);
 218             `endif
 219          endrule
 220
 221                         rule rl_connect_i2c1_to_plic;
 222                                 `ifdef I2C1
 223                                         if(i2c1.isint()==1'b1) begin
 224                                                 ff_gateway_queue[9].enq(1);
 225                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 226                                         end
 227             `else
 228                                         ff_gateway_queue[9].enq(0);
 229             `endif
 230                         endrule
 231
 232          rule rl_connect_i2c0_timerint_to_plic;
 233                                 `ifdef I2C0
 234                                         if(i2c0.timerint()==1'b1) begin
 235                                                 ff_gateway_queue[10].enq(1);
 236                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 237                                         end
 238             `else
 239                                         ff_gateway_queue[10].enq(0);
 240             `endif
 241                         endrule
 242
 243          rule rl_connect_i2c1_timerint_to_plic;
 244                                 `ifdef I2C1
 245                                         if(i2c1.timerint()==1'b1) begin
 246                                                 ff_gateway_queue[11].enq(1);
 247                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 248                                         end
 249             `else
 250                                         ff_gateway_queue[11].enq(0);
 251             `endif
 252          endrule
 253
 254          rule rl_connect_i2c0_isber_to_plic;
 255                                 `ifdef I2C0
 256                                         if(i2c0.isber()==1'b1) begin
 257                                                 ff_gateway_queue[12].enq(1);
 258                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 259                                         end
 260             `else
 261                                         ff_gateway_queue[12].enq(0);
 262             `endif
 263          endrule
 264
 265          rule rl_connect_i2c1_isber_to_plic;
 266                                 `ifdef I2C1
 267                                         if(i2c1.isber()==1'b1) begin
 268                                                 ff_gateway_queue[13].enq(1);
 269                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 270                end
 271             `else
 272                                         ff_gateway_queue[13].enq(0);
 273             `endif
 274          endrule
 275
 276          for(Integer i = 14; i < 20; i=i+1) begin
 277                                 rule rl_connect_qspi0_to_plic;
 278                                         `ifdef QSPI0
 279                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 280                                                         ff_gateway_queue[i].enq(1);
 281                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 282                                                 end
 283                `else
 284                                                 ff_gateway_queue[i].enq(0);
 285                `endif
 286             endrule
 287          end
 288
 289          for(Integer i = 20; i<26; i=i+1) begin
 290                                 rule rl_connect_qspi1_to_plic;
 291                                         `ifdef QSPI1
 292                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 293                                                         ff_gateway_queue[i].enq(1);
 294                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 295                                                 end
 296                `else
 297                                                 ff_gateway_queue[i].enq(0);
 298                `endif
 299             endrule
 300                         end
 301
 302                         `ifdef UART0
 303                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 304                                 rule synchronize_the_uart0_interrupt;
 305                                         uart0_interrupt.send(uart0.irq);
 306                                 endrule
 307                         `endif
 308                         rule rl_connect_uart_to_plic;
 309                                 `ifdef UART0
 310                                         if(uart0_interrupt.read==1'b1) begin
 311                                                 ff_gateway_queue[27].enq(1);
 312                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 313                end
 314
 315             `else
 316                                         ff_gateway_queue[27].enq(0);
 317             `endif
 318          endrule
 319
 320                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 321                                 rule rl_raise_interrupts;
 322                                         if((i-28)<`IONum) begin //Peripheral interrupts
 323                                                 if(gpio.to_plic[i-28]==1'b1) begin
 324                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 325                                                                 ff_gateway_queue[i].enq(1);
 326                   end
 327                                         end
 328                                 endrule
 329                         end
 330
 331          rule rl_completion_msg_from_plic;
 332                                 let id <- plic.intrpt_completion;
 333             interrupt_id <= id;
 334             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 335                         endrule
 336
 337          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 338                                 rule deq_gateway_queue;
 339                                         if(interrupt_id==fromInteger(i)) begin
 340                                                 ff_gateway_queue[i].deq;
 341                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 342                end
 343             endrule
 344          end
 345
 346
 347                 `endif
 348                         /*======================================================= */
 349
 350                 /* ===== interface definition =======*/
 351                 interface axi_slave=bridge.axi_slave;
 352                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 353                 `ifdef CLINT
 354                         method msip_int=clint.msip_int;
 355                         method mtip_int=clint.mtip_int;
 356                         method mtime=clint.mtime;
 357                 `endif
 358                 `ifdef I2C0
 359                         method i2c0_isint=i2c0.isint;
 360                 `endif
 361                 `ifdef I2C1
 362                         method i2c1_isint=i2c1.isint;
 363                 `endif
 364                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 365                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 366                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 367                 interface SP_ios slow_ios;
 368                         `ifdef UART0
 369                                 interface uart0_coe=uart0.coe_rs232;
 370                         `endif
 371                         `ifdef UART1
 372                                 interface uart1_coe=uart1.coe_rs232;
 373                         `endif
 374                         `ifdef I2C0
 375                                 interface i2c0_out=i2c0.out;
 376                         `endif
 377                         `ifdef I2C1
 378                                 interface i2c1_out=i2c1.out;
 379                         `endif
 380                         `ifdef QSPI0
 381                                 interface qspi0_out = qspi0.out;
 382                         `endif
 383                         `ifdef QSPI1
 384                                 interface qspi1_out = qspi1.out;
 385                         `endif
 386                         `ifdef AXIEXP
 387                                 interface axiexp1_out=axiexp1.slave_out;
 388                                 interface axiexp1_in=axiexp1.slave_in;
 389                         `endif
 390       `ifdef PWM_AXI4Lite
 391         interface pwm_o = pwm_bus.pwm_io;
 392       `endif
 393                 endinterface
 394     // NEEL EDIT
 395     interface iocell_side=pinmux.iocell_side;
 396     interface pad_configa= gpioa.pad_config;
 397     method Action external_int(Bit#(32) in);
 398       wr_interrupt<= in;
 399     endmethod
 400     // NEEL EDIT OVER
 401                 /*===================================*/
 402         endmodule
 403 endpackage