src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /*====== AXI4 Lite slave declarations =======*/
  14
  15 {3}
  16         /*===========================*/
  17         /*=== package imports ===*/
  18         import Clocks::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Connectable::*;
  22         import Vector::*;
  23         import FIFO::*;
  24         /*=======================*/
  25         /*===== Import the slow peripherals ====*/
  26 {0}
  27     `ifdef CLINT
  28         import clint::*;
  29     `endif
  30     `ifdef PLIC
  31         import plic             ::*;
  32     `endif
  33         `ifdef AXIEXP
  34                 import axiexpansion     ::*;
  35         `endif
  36         `ifdef QSPI
  37                 import qspi                              :: *;
  38         `endif
  39         /*=====================================*/
  40
  41         /*===== interface declaration =====*/
  42         interface SP_dedicated_ios;
  43                 `ifdef AXIEXP
  44                         interface Get#(Bit#(67)) axiexp1_out;
  45                         interface Put#(Bit#(67)) axiexp1_in;
  46                 `endif
  47         endinterface
  48         interface Ifc_slow_peripherals;
  49                 interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
  50                 interface SP_dedicated_ios slow_ios;
  51                 `ifdef CLINT
  52                         method Bit#(1) msip_int;
  53                         method Bit#(1) mtip_int;
  54                         method Bit#(`DATA) mtime;
  55                 `endif
  56                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  57     interface IOCellSide iocell_side; // mandatory interface
  58 {1}
  59         endinterface
  60         /*================================*/
  61
  62         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  63                      fn_address_mapping (Bit#(`ADDR) addr);
  64                 `ifdef CLINT
  65                         if(addr>=`ClintBase && addr<=`ClintEnd)
  66                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  67                         else
  68                 `endif
  69                 `ifdef PLIC
  70                         if(addr>=`PLICBase && addr<=`PLICEnd)
  71                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  72                         else
  73                 `endif
  74                 `ifdef AXIEXP
  75                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  76                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  77                         else
  78                 `endif
  79 {4}
  80                         return tuple2(False,?);
  81         endfunction
  82
  83         (*synthesize*)
  84         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  85                                Clock uart_clock, Reset uart_reset
  86                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  87                               )(Ifc_slow_peripherals);
  88                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  89                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  90
  91                 /*======= Module declarations for each peripheral =======*/
  92 {5}
  93                 `ifdef CLINT
  94                         Ifc_clint                               clint                           <- mkclint();
  95                 `endif
  96                 `ifdef PLIC
  97                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  98          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  99                           Vector#(`INTERRUPT_PINS, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
 100                 `endif
 101                 `ifdef AXIEXP
 102                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 103                 `endif
 104     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 105                 /*=======================================================*/
 106
 107         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
 108             slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 109                 Ifc_AXI4Lite_AXI4_Bridge
 110             bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 111
 112                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 113                 /*======= Slave connections to AXI4Lite fabric =========*/
 114 {6}
 115                 `ifdef CLINT
 116                         mkConnection (slow_fabric.v_to_slaves
 117                     [fromInteger(valueOf(CLINT_slave_num))],
 118                     clint.axi4_slave);
 119                 `endif
 120                 `ifdef PLIC
 121                         mkConnection (slow_fabric.v_to_slaves
 122                     [fromInteger(valueOf(Plic_slave_num))],
 123                     plic.axi4_slave_plic); //
 124                 `endif
 125                 `ifdef AXIEXP
 126                 mkConnection (slow_fabric.v_to_slaves
 127                     [fromInteger(valueOf(AxiExp1_slave_num))],
 128                     axiexp1.axi_slave); //
 129                 `endif
 130
 131     /*========== pinmux connections ============*/
 132 {7}
 133 {8}
 134     rule rl_completion_msg_from_plic;
 135                   let id <- plic.intrpt_completion;
 136       interrupt_id <= id;
 137       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 138                 endrule
 139
 140     for(Integer i=0; i <`NUM_INTERRUPTS; i=i+1) begin
 141             rule deq_gateway_queue;
 142                     if(interrupt_id==fromInteger(i)) begin
 143                             ff_gateway_queue[i].deq;
 144           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 145         end
 146       endrule
 147     end
 148     // NEEL EDIT OVER
 149                 /*=======================================================*/
 150                 /*=================== PLIC Connections ==================== */
 151                 `ifdef PLIC_main
 152                         /*TODO DMA interrupt need to be connected to the plic
 153                         for(Integer i=1; i<8; i=i+1) begin
 154          `ifdef DMA
 155              rule rl_connect_dma_interrupts_to_plic;
 156                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 157                                                 ff_gateway_queue[i].enq(1);
 158                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 159                                         end
 160              endrule
 161           `else
 162              rule rl_connect_dma_interrupts_to_plic;
 163                  ff_gateway_queue[i].enq(0);
 164              endrule
 165           `endif
 166          end
 167                         */
 168 {10}
 169          for(Integer i = 14; i < 20; i=i+1) begin
 170                                 rule rl_connect_qspi0_to_plic;
 171                                         `ifdef QSPI0
 172                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 173                                                         ff_gateway_queue[i].enq(1);
 174                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 175                                                 end
 176                `else
 177                                                 ff_gateway_queue[i].enq(0);
 178                `endif
 179             endrule
 180          end
 181
 182          for(Integer i = 20; i<26; i=i+1) begin
 183                                 rule rl_connect_qspi1_to_plic;
 184                                         `ifdef QSPI1
 185                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 186                                                         ff_gateway_queue[i].enq(1);
 187                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 188                                                 end
 189                `else
 190                                                 ff_gateway_queue[i].enq(0);
 191                `endif
 192             endrule
 193                         end
 194
 195                         `ifdef UART0
 196                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-
 197                                   mkSyncBitToCC(sp_clock, uart_reset);
 198                                 rule synchronize_the_uart0_interrupt;
 199                                         uart0_interrupt.send(uart0.irq);
 200                                 endrule
 201                         `endif
 202                         rule rl_connect_uart_to_plic;
 203                                 `ifdef UART0
 204                                         if(uart0_interrupt.read==1'b1) begin
 205                                                 ff_gateway_queue[27].enq(1);
 206                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 207                end
 208
 209             `else
 210                                         ff_gateway_queue[27].enq(0);
 211             `endif
 212          endrule
 213
 214                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 215                                 rule rl_raise_interrupts;
 216                                         if((i-28)<`IONum) begin //Peripheral interrupts
 217                                                 if(gpio.to_plic[i-28]==1'b1) begin
 218                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 219                                                                 ff_gateway_queue[i].enq(1);
 220                   end
 221                                         end
 222                                 endrule
 223                         end
 224
 225          rule rl_completion_msg_from_plic;
 226                                 let id <- plic.intrpt_completion;
 227             interrupt_id <= id;
 228             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 229                         endrule
 230
 231          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 232                                 rule deq_gateway_queue;
 233                                         if(interrupt_id==fromInteger(i)) begin
 234                                                 ff_gateway_queue[i].deq;
 235                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 236                end
 237             endrule
 238          end
 239
 240
 241                 `endif
 242                         /*======================================================= */
 243
 244                 /* ===== interface definition =======*/
 245                 interface axi_slave=bridge.axi_slave;
 246                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 247                 `ifdef CLINT
 248                         method msip_int=clint.msip_int;
 249                         method mtip_int=clint.mtip_int;
 250                         method mtime=clint.mtime;
 251                 `endif
 252                 `ifdef I2C0
 253                         method i2c0_isint=i2c0.isint;
 254                 `endif
 255                 `ifdef I2C1
 256                         method i2c1_isint=i2c1.isint;
 257                 `endif
 258                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 259                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 260                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 261                 interface SP_dedicated_ios slow_ios;
 262 /* template for dedicated peripherals
 263                         `ifdef UART0
 264                                 interface uart0_coe=uart0.coe_rs232;
 265                         `endif
 266                         `ifdef UART1
 267                                 interface uart1_coe=uart1.coe_rs232;
 268                         `endif
 269                         `ifdef I2C0
 270                                 interface i2c0_out=i2c0.out;
 271                         `endif
 272                         `ifdef I2C1
 273                                 interface i2c1_out=i2c1.out;
 274                         `endif
 275                         `ifdef QSPI0
 276                                 interface qspi0_out = qspi0.out;
 277                         `endif
 278                         `ifdef QSPI1
 279                                 interface qspi1_out = qspi1.out;
 280                         `endif
 281                         `ifdef AXIEXP
 282                                 interface axiexp1_out=axiexp1.slave_out;
 283                                 interface axiexp1_in=axiexp1.slave_in;
 284                         `endif
 285       `ifdef PWM_AXI4Lite
 286         interface pwm_o = pwm_bus.pwm_io;
 287       `endif
 288 */
 289                 endinterface
 290     // NEEL EDIT
 291     interface iocell_side=pinmux.iocell_side;
 292     interface pad_config0= gpioa.pad_config;
 293 {9}
 294     // NEEL EDIT OVER
 295                 /*===================================*/
 296         endmodule
 297 endpackage