src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11         /*===========================*/
  12         /*=== package imports ===*/
  13         import Clocks::*;
  14         import GetPut::*;
  15         import ClientServer::*;
  16         import Connectable::*;
  17         import Vector::*;
  18         import FIFO::*;
  19         /*=======================*/
  20         /*===== Import the slow peripherals ====*/
  21 {0}
  22         `ifdef AXIEXP
  23                 import axiexpansion     ::*;
  24         `endif
  25   import pinmux::*;
  26   import mux::*;
  27   import gpio::*;
  28         /*=====================================*/
  29
  30         /*===== interface declaration =====*/
  31         interface SP_ios;
  32 {1}
  33                 `ifdef AXIEXP
  34                         interface Get#(Bit#(67)) axiexp1_out;
  35                         interface Put#(Bit#(67)) axiexp1_in;
  36                 `endif
  37         endinterface
  38         interface Ifc_slow_peripherals;
  39                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  40                 interface SP_ios slow_ios;
  41     method Action external_int(Bit#(32) in);
  42                 `ifdef CLINT
  43                         method Bit#(1) msip_int;
  44                         method Bit#(1) mtip_int;
  45                         method Bit#(`Reg_width) mtime;
  46                 `endif
  47                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  48                 `ifdef I2C0     method Bit#(1) i2c0_isint; `endif
  49                 `ifdef I2C1     method Bit#(1) i2c1_isint; `endif
  50                 `ifdef QSPI0 method Bit#(1) qspi0_isint; `endif
  51                 `ifdef QSPI1 method Bit#(1) qspi1_isint; `endif
  52                 `ifdef UART0 method Bit#(1) uart0_intr; `endif
  53     // NEEL EDIT
  54     interface IOCellSide iocell_side; // mandatory interface
  55     interface GPIO_config#(3) pad_configa; // depends on the number of banks
  56     // NEEL EDIT OVER
  57         endinterface
  58         /*================================*/
  59
  60         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves))) fn_address_mapping (Bit#(`PADDR) addr);
  61                 `ifdef UART0
  62                         if(addr>=`UART0Base && addr<=`UART0End)
  63                                 return tuple2(True,fromInteger(valueOf(Uart0_slave_num)));
  64                         else
  65                 `endif
  66                 `ifdef UART1
  67                         if(addr>=`UART1Base && addr<=`UART1End)
  68                                 return tuple2(True,fromInteger(valueOf(Uart1_slave_num)));
  69                         else
  70                 `endif
  71                 `ifdef CLINT
  72                         if(addr>=`ClintBase && addr<=`ClintEnd)
  73                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  74                         else
  75                 `endif
  76                 `ifdef PLIC
  77                         if(addr>=`PLICBase && addr<=`PLICEnd)
  78                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  79                         else
  80                 `endif
  81                 `ifdef I2C0
  82                         if(addr>=`I2C0Base && addr<=`I2C0End)
  83                                 return tuple2(True,fromInteger(valueOf(I2c0_slave_num)));
  84                         else
  85                 `endif
  86                 `ifdef I2C1
  87                         if(addr>=`I2C1Base && addr<=`I2C1End)
  88                                 return tuple2(True,fromInteger(valueOf(I2c1_slave_num)));
  89                         else
  90                 `endif
  91                 `ifdef QSPI0
  92                         if(addr>=`QSPI0CfgBase && addr<=`QSPI0CfgEnd)
  93                                 return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
  94                         else if(addr>=`QSPI0MemBase && addr<=`QSPI0MemEnd)
  95                                 return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
  96                         else
  97                 `endif
  98                 `ifdef QSPI1
  99                         if(addr>=`QSPI1CfgBase && addr<=`QSPI1CfgEnd)
 100                                 return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
 101                         else if(addr>=`QSPI1MemBase && addr<=`QSPI1MemEnd)
 102                                 return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
 103                         else
 104                 `endif
 105                 `ifdef AXIEXP
 106                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
 107                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
 108                         else
 109                 `endif
 110     `ifdef PWM_AXI4Lite
 111       if(addr>=`PWMBase && addr<=`PWMEnd)
 112         return tuple2(True,fromInteger(valueOf(Pwm_slave_num)));
 113       else
 114     `endif
 115
 116     // NEEL EDIT
 117       // give slave number and adress map to whatever peripherals you instantiate on the AXI4_Lite
 118       // slave.
 119     // NEEL EDIT OVER
 120                 return tuple2(False,?);
 121         endfunction
 122
 123         (*synthesize*)
 124         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset, Clock uart_clock, Reset uart_reset
 125   `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_slow_peripherals);
 126                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
 127                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
 128
 129                 /*======= Module declarations for each peripheral =======*/
 130                 `ifdef UART0
 131                         Uart16550_AXI4_Lite_Ifc uart0 <- mkUart16550(clocked_by uart_clock, reset_by uart_reset, sp_clock, sp_reset);
 132                 `endif
 133                 `ifdef UART1
 134                         //Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by uart_clock, reset_by uart_reset,sp_clock, sp_reset);
 135                         Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by sp_clock, reset_by sp_reset,sp_clock, sp_reset);
 136                 `endif
 137                 `ifdef CLINT
 138                         Ifc_clint                               clint                           <- mkclint();
 139                 `endif
 140                 `ifdef PLIC
 141                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
 142          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 143                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
 144                 `endif
 145                 `ifdef I2C0
 146                         I2C_IFC                                 i2c0                            <- mkI2CController();
 147                 `endif
 148                 `ifdef I2C1
 149                         I2C_IFC                                 i2c1                            <- mkI2CController();
 150                 `endif
 151                 `ifdef QSPI0
 152                         Ifc_qspi                        qspi0                           <-      mkqspi();
 153                 `endif
 154                 `ifdef QSPI1
 155                         Ifc_qspi                        qspi1                           <-      mkqspi();
 156                 `endif
 157                 `ifdef AXIEXP
 158                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 159                 `endif
 160     `ifdef PWM_AXI4Lite
 161       Ifc_PWM_bus pwm_bus <- mkPWM_bus(ext_pwm_clock);
 162     `endif
 163     // NEEL EDIT
 164     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 165     MUX#(3) muxa <- mkmux(); // mandatory. number depends on the number of instances required.
 166     GPIO#(3) gpioa <- mkgpio(); // optional. depends the number of IO pins declared before.
 167     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 168     // NEEL EDIT OVER
 169                 /*=======================================================*/
 170
 171         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)       slow_fabric <-
 172                                                             mkAXI4_Lite_Fabric(fn_address_mapping);
 173                 Ifc_AXI4Lite_AXI4_Bridge bridge <-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 174
 175                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 176                 /*======= Slave connections to AXI4Lite fabric =========*/
 177                 `ifdef UART0
 178                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart0_slave_num))],
 179                     uart0.slave_axi_uart);
 180                 `endif
 181                 `ifdef UART1
 182                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart1_slave_num))],
 183                     uart1.slave_axi_uart);
 184                 `endif
 185                 `ifdef CLINT
 186                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))],
 187                     clint.axi4_slave);
 188                 `endif
 189                 `ifdef PLIC
 190                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))],
 191                     plic.axi4_slave_plic); //
 192                 `endif
 193                 `ifdef I2C0
 194                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c0_slave_num))],
 195                     i2c0.slave_i2c_axi);
 196                 `endif
 197                 `ifdef I2C1
 198                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c1_slave_num))],
 199                     i2c1.slave_i2c_axi); //
 200                 `endif
 201                 `ifdef QSPI0
 202                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi0_slave_num))],
 203                     qspi0.slave);
 204                 `endif
 205                 `ifdef QSPI1
 206                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi1_slave_num))],
 207                     qspi1.slave);
 208                 `endif
 209                 `ifdef AXIEXP
 210                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(AxiExp1_slave_num))],
 211                     axiexp1.axi_slave); //
 212                 `endif
 213     `ifdef PWM_AXI4Lite
 214       mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Pwm_slave_num))],
 215                     pwm_bus.axi4_slave);
 216     `endif
 217
 218     // NEEL EDIT
 219     mkConnection (slow_fabric.
 220                   v_to_slaves[fromInteger(valueOf(Muxa_slave_num))],
 221                   muxa.axi_slave);
 222     mkConnection (slow_fabric.
 223                   v_to_slaves[fromInteger(valueOf(Gpioa_slave_num))],
 224                   gpioa.axi_slave);
 225     rule connect_select_lines_pinmux;// mandatory
 226       pinmux.mux_lines.cell0_mux(muxa.mux_config.mux[0]);
 227       pinmux.mux_lines.cell1_mux(muxa.mux_config.mux[1]);
 228       pinmux.mux_lines.cell2_mux(muxa.mux_config.mux[2]);
 229     endrule
 230     rule connect_i2c0_scl;
 231       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 232       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 233     endrule
 234     rule connect_i2c0_scl_in;
 235       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 236     endrule
 237     rule connect_i2c0_sda;
 238       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 239       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 240     endrule
 241     rule connect_i2c0_sda_in;
 242       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 243     endrule
 244     rule connect_uart1tx;
 245       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 246     endrule
 247     rule connect_uart1rx;
 248       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 249     endrule
 250     rule connect_gpioa;
 251       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 252       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 253       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 254       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 255       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 256       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 257                 Vector#(3,Bit#(1)) temp;
 258                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 259                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 260                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 261       gpioa.func.gpio_in(temp);
 262     endrule
 263     for(Integer i=0;i<32;i=i+ 1)begin
 264       rule connect_int_to_plic(wr_interrupt[i]==1);
 265                                 ff_gateway_queue[i].enq(1);
 266                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 267       endrule
 268     end
 269     rule rl_completion_msg_from_plic;
 270                   let id <- plic.intrpt_completion;
 271       interrupt_id <= id;
 272       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 273                 endrule
 274
 275     for(Integer i=0; i <32; i=i+1) begin
 276             rule deq_gateway_queue;
 277                     if(interrupt_id==fromInteger(i)) begin
 278                             ff_gateway_queue[i].deq;
 279           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 280         end
 281       endrule
 282     end
 283     /* for connectin inputs from pinmux as itnerrupts
 284       rule connect_pinmux_eint;
 285         wr_interrupt<= pinmux.peripheral_side.eint_input;
 286       endrule
 287     */
 288     // NEEL EDIT OVER
 289                 /*=======================================================*/
 290                 /*=================== PLIC Connections ==================== */
 291                 `ifdef PLIC_main
 292                         /*TODO DMA interrupt need to be connected to the plic
 293                         for(Integer i=1; i<8; i=i+1) begin
 294          `ifdef DMA
 295              rule rl_connect_dma_interrupts_to_plic;
 296                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 297                                                 ff_gateway_queue[i].enq(1);
 298                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 299                                         end
 300              endrule
 301           `else
 302              rule rl_connect_dma_interrupts_to_plic;
 303                  ff_gateway_queue[i].enq(0);
 304              endrule
 305           `endif
 306          end
 307                         */
 308          rule rl_connect_i2c0_to_plic;
 309                                 `ifdef I2C0
 310                                         if(i2c0.isint()==1'b1) begin
 311                                                 ff_gateway_queue[8].enq(1);
 312                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 313                                         end
 314                                 `else
 315                                         ff_gateway_queue[8].enq(0);
 316             `endif
 317          endrule
 318
 319                         rule rl_connect_i2c1_to_plic;
 320                                 `ifdef I2C1
 321                                         if(i2c1.isint()==1'b1) begin
 322                                                 ff_gateway_queue[9].enq(1);
 323                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 324                                         end
 325             `else
 326                                         ff_gateway_queue[9].enq(0);
 327             `endif
 328                         endrule
 329
 330          rule rl_connect_i2c0_timerint_to_plic;
 331                                 `ifdef I2C0
 332                                         if(i2c0.timerint()==1'b1) begin
 333                                                 ff_gateway_queue[10].enq(1);
 334                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 335                                         end
 336             `else
 337                                         ff_gateway_queue[10].enq(0);
 338             `endif
 339                         endrule
 340
 341          rule rl_connect_i2c1_timerint_to_plic;
 342                                 `ifdef I2C1
 343                                         if(i2c1.timerint()==1'b1) begin
 344                                                 ff_gateway_queue[11].enq(1);
 345                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 346                                         end
 347             `else
 348                                         ff_gateway_queue[11].enq(0);
 349             `endif
 350          endrule
 351
 352          rule rl_connect_i2c0_isber_to_plic;
 353                                 `ifdef I2C0
 354                                         if(i2c0.isber()==1'b1) begin
 355                                                 ff_gateway_queue[12].enq(1);
 356                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 357                                         end
 358             `else
 359                                         ff_gateway_queue[12].enq(0);
 360             `endif
 361          endrule
 362
 363          rule rl_connect_i2c1_isber_to_plic;
 364                                 `ifdef I2C1
 365                                         if(i2c1.isber()==1'b1) begin
 366                                                 ff_gateway_queue[13].enq(1);
 367                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 368                end
 369             `else
 370                                         ff_gateway_queue[13].enq(0);
 371             `endif
 372          endrule
 373
 374          for(Integer i = 14; i < 20; i=i+1) begin
 375                                 rule rl_connect_qspi0_to_plic;
 376                                         `ifdef QSPI0
 377                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 378                                                         ff_gateway_queue[i].enq(1);
 379                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 380                                                 end
 381                `else
 382                                                 ff_gateway_queue[i].enq(0);
 383                `endif
 384             endrule
 385          end
 386
 387          for(Integer i = 20; i<26; i=i+1) begin
 388                                 rule rl_connect_qspi1_to_plic;
 389                                         `ifdef QSPI1
 390                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 391                                                         ff_gateway_queue[i].enq(1);
 392                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 393                                                 end
 394                `else
 395                                                 ff_gateway_queue[i].enq(0);
 396                `endif
 397             endrule
 398                         end
 399
 400                         `ifdef UART0
 401                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 402                                 rule synchronize_the_uart0_interrupt;
 403                                         uart0_interrupt.send(uart0.irq);
 404                                 endrule
 405                         `endif
 406                         rule rl_connect_uart_to_plic;
 407                                 `ifdef UART0
 408                                         if(uart0_interrupt.read==1'b1) begin
 409                                                 ff_gateway_queue[27].enq(1);
 410                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 411                end
 412
 413             `else
 414                                         ff_gateway_queue[27].enq(0);
 415             `endif
 416          endrule
 417
 418                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 419                                 rule rl_raise_interrupts;
 420                                         if((i-28)<`IONum) begin //Peripheral interrupts
 421                                                 if(gpio.to_plic[i-28]==1'b1) begin
 422                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 423                                                                 ff_gateway_queue[i].enq(1);
 424                   end
 425                                         end
 426                                 endrule
 427                         end
 428
 429          rule rl_completion_msg_from_plic;
 430                                 let id <- plic.intrpt_completion;
 431             interrupt_id <= id;
 432             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 433                         endrule
 434
 435          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 436                                 rule deq_gateway_queue;
 437                                         if(interrupt_id==fromInteger(i)) begin
 438                                                 ff_gateway_queue[i].deq;
 439                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 440                end
 441             endrule
 442          end
 443
 444
 445                 `endif
 446                         /*======================================================= */
 447
 448                 /* ===== interface definition =======*/
 449                 interface axi_slave=bridge.axi_slave;
 450                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 451                 `ifdef CLINT
 452                         method msip_int=clint.msip_int;
 453                         method mtip_int=clint.mtip_int;
 454                         method mtime=clint.mtime;
 455                 `endif
 456                 `ifdef I2C0
 457                         method i2c0_isint=i2c0.isint;
 458                 `endif
 459                 `ifdef I2C1
 460                         method i2c1_isint=i2c1.isint;
 461                 `endif
 462                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 463                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 464                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 465                 interface SP_ios slow_ios;
 466                         `ifdef UART0
 467                                 interface uart0_coe=uart0.coe_rs232;
 468                         `endif
 469                         `ifdef UART1
 470                                 interface uart1_coe=uart1.coe_rs232;
 471                         `endif
 472                         `ifdef I2C0
 473                                 interface i2c0_out=i2c0.out;
 474                         `endif
 475                         `ifdef I2C1
 476                                 interface i2c1_out=i2c1.out;
 477                         `endif
 478                         `ifdef QSPI0
 479                                 interface qspi0_out = qspi0.out;
 480                         `endif
 481                         `ifdef QSPI1
 482                                 interface qspi1_out = qspi1.out;
 483                         `endif
 484                         `ifdef AXIEXP
 485                                 interface axiexp1_out=axiexp1.slave_out;
 486                                 interface axiexp1_in=axiexp1.slave_in;
 487                         `endif
 488       `ifdef PWM_AXI4Lite
 489         interface pwm_o = pwm_bus.pwm_io;
 490       `endif
 491                 endinterface
 492     // NEEL EDIT
 493     interface iocell_side=pinmux.iocell_side;
 494     interface pad_configa= gpioa.pad_config;
 495     method Action external_int(Bit#(32) in);
 496       wr_interrupt<= in;
 497     endmethod
 498     // NEEL EDIT OVER
 499                 /*===================================*/
 500         endmodule
 501 endpackage