src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11         /*===========================*/
  12         /*=== package imports ===*/
  13         import Clocks::*;
  14         import GetPut::*;
  15         import ClientServer::*;
  16         import Connectable::*;
  17         import Vector::*;
  18         import FIFO::*;
  19         /*=======================*/
  20         /*===== Import the slow peripherals ====*/
  21 {0}
  22     `ifdef CLINT
  23         import clint::*;
  24     `endif
  25     `ifdef PLIC
  26         import plic             ::*;
  27     `endif
  28         `ifdef AXIEXP
  29                 import axiexpansion     ::*;
  30         `endif
  31         /*=====================================*/
  32
  33         /*===== interface declaration =====*/
  34         interface SP_ios;
  35 {1}
  36                 `ifdef AXIEXP
  37                         interface Get#(Bit#(67)) axiexp1_out;
  38                         interface Put#(Bit#(67)) axiexp1_in;
  39                 `endif
  40         endinterface
  41         interface Ifc_slow_peripherals;
  42                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  43                 interface SP_ios slow_ios;
  44     method Action external_int(Bit#(32) in);
  45                 `ifdef CLINT
  46                         method Bit#(1) msip_int;
  47                         method Bit#(1) mtip_int;
  48                         method Bit#(`Reg_width) mtime;
  49                 `endif
  50                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  51     interface IOCellSide iocell_side; // mandatory interface
  52         endinterface
  53         /*================================*/
  54
  55         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves))) fn_address_mapping (Bit#(`PADDR) addr);
  56                 `ifdef UART0
  57                         if(addr>=`UART0Base && addr<=`UART0End)
  58                                 return tuple2(True,fromInteger(valueOf(Uart0_slave_num)));
  59                         else
  60                 `endif
  61                 `ifdef UART1
  62                         if(addr>=`UART1Base && addr<=`UART1End)
  63                                 return tuple2(True,fromInteger(valueOf(Uart1_slave_num)));
  64                         else
  65                 `endif
  66                 `ifdef CLINT
  67                         if(addr>=`ClintBase && addr<=`ClintEnd)
  68                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  69                         else
  70                 `endif
  71                 `ifdef PLIC
  72                         if(addr>=`PLICBase && addr<=`PLICEnd)
  73                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  74                         else
  75                 `endif
  76                 `ifdef I2C0
  77                         if(addr>=`I2C0Base && addr<=`I2C0End)
  78                                 return tuple2(True,fromInteger(valueOf(I2c0_slave_num)));
  79                         else
  80                 `endif
  81                 `ifdef I2C1
  82                         if(addr>=`I2C1Base && addr<=`I2C1End)
  83                                 return tuple2(True,fromInteger(valueOf(I2c1_slave_num)));
  84                         else
  85                 `endif
  86                 `ifdef QSPI0
  87                         if(addr>=`QSPI0CfgBase && addr<=`QSPI0CfgEnd)
  88                                 return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
  89                         else if(addr>=`QSPI0MemBase && addr<=`QSPI0MemEnd)
  90                                 return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
  91                         else
  92                 `endif
  93                 `ifdef QSPI1
  94                         if(addr>=`QSPI1CfgBase && addr<=`QSPI1CfgEnd)
  95                                 return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
  96                         else if(addr>=`QSPI1MemBase && addr<=`QSPI1MemEnd)
  97                                 return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
  98                         else
  99                 `endif
 100                 `ifdef AXIEXP
 101                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
 102                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
 103                         else
 104                 `endif
 105     `ifdef PWM_AXI4Lite
 106       if(addr>=`PWMBase && addr<=`PWMEnd)
 107         return tuple2(True,fromInteger(valueOf(Pwm_slave_num)));
 108       else
 109     `endif
 110
 111     // NEEL EDIT
 112       // give slave number and adress map to whatever peripherals you instantiate on the AXI4_Lite
 113       // slave.
 114     // NEEL EDIT OVER
 115                 return tuple2(False,?);
 116         endfunction
 117
 118         (*synthesize*)
 119         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset, Clock uart_clock, Reset uart_reset
 120   `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_slow_peripherals);
 121                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
 122                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
 123
 124                 /*======= Module declarations for each peripheral =======*/
 125                 `ifdef UART0
 126                         Uart16550_AXI4_Lite_Ifc uart0 <- mkUart16550(clocked_by uart_clock, reset_by uart_reset, sp_clock, sp_reset);
 127                 `endif
 128                 `ifdef UART1
 129                         //Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by uart_clock, reset_by uart_reset,sp_clock, sp_reset);
 130                         Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by sp_clock, reset_by sp_reset,sp_clock, sp_reset);
 131                 `endif
 132                 `ifdef CLINT
 133                         Ifc_clint                               clint                           <- mkclint();
 134                 `endif
 135                 `ifdef PLIC
 136                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
 137          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 138                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
 139                 `endif
 140                 `ifdef I2C0
 141                         I2C_IFC                                 i2c0                            <- mkI2CController();
 142                 `endif
 143                 `ifdef I2C1
 144                         I2C_IFC                                 i2c1                            <- mkI2CController();
 145                 `endif
 146                 `ifdef QSPI0
 147                         Ifc_qspi                        qspi0                           <-      mkqspi();
 148                 `endif
 149                 `ifdef QSPI1
 150                         Ifc_qspi                        qspi1                           <-      mkqspi();
 151                 `endif
 152                 `ifdef AXIEXP
 153                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 154                 `endif
 155     `ifdef PWM_AXI4Lite
 156       Ifc_PWM_bus pwm_bus <- mkPWM_bus(ext_pwm_clock);
 157     `endif
 158     // NEEL EDIT
 159     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 160     MUX#(3) muxa <- mkmux(); // mandatory. number depends on the number of instances required.
 161     GPIO#(3) gpioa <- mkgpio(); // optional. depends the number of IO pins declared before.
 162     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 163     // NEEL EDIT OVER
 164                 /*=======================================================*/
 165
 166         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)       slow_fabric <-
 167                                                             mkAXI4_Lite_Fabric(fn_address_mapping);
 168                 Ifc_AXI4Lite_AXI4_Bridge bridge <-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 169
 170                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 171                 /*======= Slave connections to AXI4Lite fabric =========*/
 172                 `ifdef UART0
 173                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart0_slave_num))],
 174                     uart0.slave_axi_uart);
 175                 `endif
 176                 `ifdef UART1
 177                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart1_slave_num))],
 178                     uart1.slave_axi_uart);
 179                 `endif
 180                 `ifdef CLINT
 181                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))],
 182                     clint.axi4_slave);
 183                 `endif
 184                 `ifdef PLIC
 185                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))],
 186                     plic.axi4_slave_plic); //
 187                 `endif
 188                 `ifdef I2C0
 189                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c0_slave_num))],
 190                     i2c0.slave_i2c_axi);
 191                 `endif
 192                 `ifdef I2C1
 193                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c1_slave_num))],
 194                     i2c1.slave_i2c_axi); //
 195                 `endif
 196                 `ifdef QSPI0
 197                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi0_slave_num))],
 198                     qspi0.slave);
 199                 `endif
 200                 `ifdef QSPI1
 201                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi1_slave_num))],
 202                     qspi1.slave);
 203                 `endif
 204                 `ifdef AXIEXP
 205                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(AxiExp1_slave_num))],
 206                     axiexp1.axi_slave); //
 207                 `endif
 208     `ifdef PWM_AXI4Lite
 209       mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Pwm_slave_num))],
 210                     pwm_bus.axi4_slave);
 211     `endif
 212
 213     // NEEL EDIT
 214     mkConnection (slow_fabric.
 215                   v_to_slaves[fromInteger(valueOf(Muxa_slave_num))],
 216                   muxa.axi_slave);
 217     mkConnection (slow_fabric.
 218                   v_to_slaves[fromInteger(valueOf(Gpioa_slave_num))],
 219                   gpioa.axi_slave);
 220     rule connect_select_lines_pinmux;// mandatory
 221       pinmux.mux_lines.cell0_mux(muxa.mux_config.mux[0]);
 222       pinmux.mux_lines.cell1_mux(muxa.mux_config.mux[1]);
 223       pinmux.mux_lines.cell2_mux(muxa.mux_config.mux[2]);
 224     endrule
 225     rule connect_i2c0_scl;
 226       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 227       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 228     endrule
 229     rule connect_i2c0_scl_in;
 230       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 231     endrule
 232     rule connect_i2c0_sda;
 233       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 234       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 235     endrule
 236     rule connect_i2c0_sda_in;
 237       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 238     endrule
 239     rule connect_uart1tx;
 240       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 241     endrule
 242     rule connect_uart1rx;
 243       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 244     endrule
 245     rule connect_gpioa;
 246       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 247       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 248       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 249       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 250       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 251       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 252                 Vector#(3,Bit#(1)) temp;
 253                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 254                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 255                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 256       gpioa.func.gpio_in(temp);
 257     endrule
 258     for(Integer i=0;i<32;i=i+ 1)begin
 259       rule connect_int_to_plic(wr_interrupt[i]==1);
 260                                 ff_gateway_queue[i].enq(1);
 261                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 262       endrule
 263     end
 264     rule rl_completion_msg_from_plic;
 265                   let id <- plic.intrpt_completion;
 266       interrupt_id <= id;
 267       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 268                 endrule
 269
 270     for(Integer i=0; i <32; i=i+1) begin
 271             rule deq_gateway_queue;
 272                     if(interrupt_id==fromInteger(i)) begin
 273                             ff_gateway_queue[i].deq;
 274           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 275         end
 276       endrule
 277     end
 278     /* for connectin inputs from pinmux as itnerrupts
 279       rule connect_pinmux_eint;
 280         wr_interrupt<= pinmux.peripheral_side.eint_input;
 281       endrule
 282     */
 283     // NEEL EDIT OVER
 284                 /*=======================================================*/
 285                 /*=================== PLIC Connections ==================== */
 286                 `ifdef PLIC_main
 287                         /*TODO DMA interrupt need to be connected to the plic
 288                         for(Integer i=1; i<8; i=i+1) begin
 289          `ifdef DMA
 290              rule rl_connect_dma_interrupts_to_plic;
 291                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 292                                                 ff_gateway_queue[i].enq(1);
 293                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 294                                         end
 295              endrule
 296           `else
 297              rule rl_connect_dma_interrupts_to_plic;
 298                  ff_gateway_queue[i].enq(0);
 299              endrule
 300           `endif
 301          end
 302                         */
 303          rule rl_connect_i2c0_to_plic;
 304                                 `ifdef I2C0
 305                                         if(i2c0.isint()==1'b1) begin
 306                                                 ff_gateway_queue[8].enq(1);
 307                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 308                                         end
 309                                 `else
 310                                         ff_gateway_queue[8].enq(0);
 311             `endif
 312          endrule
 313
 314                         rule rl_connect_i2c1_to_plic;
 315                                 `ifdef I2C1
 316                                         if(i2c1.isint()==1'b1) begin
 317                                                 ff_gateway_queue[9].enq(1);
 318                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 319                                         end
 320             `else
 321                                         ff_gateway_queue[9].enq(0);
 322             `endif
 323                         endrule
 324
 325          rule rl_connect_i2c0_timerint_to_plic;
 326                                 `ifdef I2C0
 327                                         if(i2c0.timerint()==1'b1) begin
 328                                                 ff_gateway_queue[10].enq(1);
 329                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 330                                         end
 331             `else
 332                                         ff_gateway_queue[10].enq(0);
 333             `endif
 334                         endrule
 335
 336          rule rl_connect_i2c1_timerint_to_plic;
 337                                 `ifdef I2C1
 338                                         if(i2c1.timerint()==1'b1) begin
 339                                                 ff_gateway_queue[11].enq(1);
 340                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 341                                         end
 342             `else
 343                                         ff_gateway_queue[11].enq(0);
 344             `endif
 345          endrule
 346
 347          rule rl_connect_i2c0_isber_to_plic;
 348                                 `ifdef I2C0
 349                                         if(i2c0.isber()==1'b1) begin
 350                                                 ff_gateway_queue[12].enq(1);
 351                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 352                                         end
 353             `else
 354                                         ff_gateway_queue[12].enq(0);
 355             `endif
 356          endrule
 357
 358          rule rl_connect_i2c1_isber_to_plic;
 359                                 `ifdef I2C1
 360                                         if(i2c1.isber()==1'b1) begin
 361                                                 ff_gateway_queue[13].enq(1);
 362                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 363                end
 364             `else
 365                                         ff_gateway_queue[13].enq(0);
 366             `endif
 367          endrule
 368
 369          for(Integer i = 14; i < 20; i=i+1) begin
 370                                 rule rl_connect_qspi0_to_plic;
 371                                         `ifdef QSPI0
 372                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 373                                                         ff_gateway_queue[i].enq(1);
 374                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 375                                                 end
 376                `else
 377                                                 ff_gateway_queue[i].enq(0);
 378                `endif
 379             endrule
 380          end
 381
 382          for(Integer i = 20; i<26; i=i+1) begin
 383                                 rule rl_connect_qspi1_to_plic;
 384                                         `ifdef QSPI1
 385                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 386                                                         ff_gateway_queue[i].enq(1);
 387                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 388                                                 end
 389                `else
 390                                                 ff_gateway_queue[i].enq(0);
 391                `endif
 392             endrule
 393                         end
 394
 395                         `ifdef UART0
 396                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 397                                 rule synchronize_the_uart0_interrupt;
 398                                         uart0_interrupt.send(uart0.irq);
 399                                 endrule
 400                         `endif
 401                         rule rl_connect_uart_to_plic;
 402                                 `ifdef UART0
 403                                         if(uart0_interrupt.read==1'b1) begin
 404                                                 ff_gateway_queue[27].enq(1);
 405                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 406                end
 407
 408             `else
 409                                         ff_gateway_queue[27].enq(0);
 410             `endif
 411          endrule
 412
 413                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 414                                 rule rl_raise_interrupts;
 415                                         if((i-28)<`IONum) begin //Peripheral interrupts
 416                                                 if(gpio.to_plic[i-28]==1'b1) begin
 417                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 418                                                                 ff_gateway_queue[i].enq(1);
 419                   end
 420                                         end
 421                                 endrule
 422                         end
 423
 424          rule rl_completion_msg_from_plic;
 425                                 let id <- plic.intrpt_completion;
 426             interrupt_id <= id;
 427             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 428                         endrule
 429
 430          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 431                                 rule deq_gateway_queue;
 432                                         if(interrupt_id==fromInteger(i)) begin
 433                                                 ff_gateway_queue[i].deq;
 434                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 435                end
 436             endrule
 437          end
 438
 439
 440                 `endif
 441                         /*======================================================= */
 442
 443                 /* ===== interface definition =======*/
 444                 interface axi_slave=bridge.axi_slave;
 445                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 446                 `ifdef CLINT
 447                         method msip_int=clint.msip_int;
 448                         method mtip_int=clint.mtip_int;
 449                         method mtime=clint.mtime;
 450                 `endif
 451                 `ifdef I2C0
 452                         method i2c0_isint=i2c0.isint;
 453                 `endif
 454                 `ifdef I2C1
 455                         method i2c1_isint=i2c1.isint;
 456                 `endif
 457                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 458                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 459                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 460                 interface SP_ios slow_ios;
 461                         `ifdef UART0
 462                                 interface uart0_coe=uart0.coe_rs232;
 463                         `endif
 464                         `ifdef UART1
 465                                 interface uart1_coe=uart1.coe_rs232;
 466                         `endif
 467                         `ifdef I2C0
 468                                 interface i2c0_out=i2c0.out;
 469                         `endif
 470                         `ifdef I2C1
 471                                 interface i2c1_out=i2c1.out;
 472                         `endif
 473                         `ifdef QSPI0
 474                                 interface qspi0_out = qspi0.out;
 475                         `endif
 476                         `ifdef QSPI1
 477                                 interface qspi1_out = qspi1.out;
 478                         `endif
 479                         `ifdef AXIEXP
 480                                 interface axiexp1_out=axiexp1.slave_out;
 481                                 interface axiexp1_in=axiexp1.slave_in;
 482                         `endif
 483       `ifdef PWM_AXI4Lite
 484         interface pwm_o = pwm_bus.pwm_io;
 485       `endif
 486                 endinterface
 487     // NEEL EDIT
 488     interface iocell_side=pinmux.iocell_side;
 489     interface pad_configa= gpioa.pad_config;
 490     method Action external_int(Bit#(32) in);
 491       wr_interrupt<= in;
 492     endmethod
 493     // NEEL EDIT OVER
 494                 /*===================================*/
 495         endmodule
 496 endpackage