src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /*====== AXI4 Lite slave declarations =======*/
  14
  15 {3}
  16         /*===========================*/
  17         /*=== package imports ===*/
  18         import Clocks::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Connectable::*;
  22         import Vector::*;
  23         import FIFO::*;
  24         /*=======================*/
  25         /*===== Import the slow peripherals ====*/
  26 {0}
  27     `ifdef CLINT
  28         import clint::*;
  29     `endif
  30     `ifdef PLIC
  31         import plic             ::*;
  32     `endif
  33         `ifdef AXIEXP
  34                 import axiexpansion     ::*;
  35         `endif
  36         /*=====================================*/
  37
  38         /*===== interface declaration =====*/
  39         interface SP_ios;
  40 {1}
  41                 `ifdef AXIEXP
  42                         interface Get#(Bit#(67)) axiexp1_out;
  43                         interface Put#(Bit#(67)) axiexp1_in;
  44                 `endif
  45         endinterface
  46         interface Ifc_slow_peripherals;
  47                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  48                 interface SP_ios slow_ios;
  49     method Action external_int(Bit#(32) in);
  50                 `ifdef CLINT
  51                         method Bit#(1) msip_int;
  52                         method Bit#(1) mtip_int;
  53                         method Bit#(`Reg_width) mtime;
  54                 `endif
  55                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  56     interface IOCellSide iocell_side; // mandatory interface
  57         endinterface
  58         /*================================*/
  59
  60         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  61                      fn_address_mapping (Bit#(`PADDR) addr);
  62                 `ifdef CLINT
  63                         if(addr>=`ClintBase && addr<=`ClintEnd)
  64                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  65                         else
  66                 `endif
  67                 `ifdef PLIC
  68                         if(addr>=`PLICBase && addr<=`PLICEnd)
  69                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  70                         else
  71                 `endif
  72                 `ifdef AXIEXP
  73                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  74                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  75                         else
  76                 `endif
  77 {4}
  78                         return tuple2(False,?);
  79         endfunction
  80
  81         (*synthesize*)
  82         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  83                                Clock uart_clock, Reset uart_reset
  84                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  85                               )(Ifc_slow_peripherals);
  86                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  87                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  88
  89                 /*======= Module declarations for each peripheral =======*/
  90 {5}
  91                 `ifdef CLINT
  92                         Ifc_clint                               clint                           <- mkclint();
  93                 `endif
  94                 `ifdef PLIC
  95                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  96          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  97                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
  98                 `endif
  99                 `ifdef AXIEXP
 100                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 101                 `endif
 102     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 103     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 104                 /*=======================================================*/
 105
 106         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)
 107             slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 108                 Ifc_AXI4Lite_AXI4_Bridge
 109             bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 110
 111                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 112                 /*======= Slave connections to AXI4Lite fabric =========*/
 113 {6}
 114                 `ifdef CLINT
 115                         mkConnection (slow_fabric.v_to_slaves
 116                     [fromInteger(valueOf(CLINT_slave_num))],
 117                     clint.axi4_slave);
 118                 `endif
 119                 `ifdef PLIC
 120                         mkConnection (slow_fabric.v_to_slaves
 121                     [fromInteger(valueOf(Plic_slave_num))],
 122                     plic.axi4_slave_plic); //
 123                 `endif
 124                 `ifdef AXIEXP
 125                 mkConnection (slow_fabric.v_to_slaves
 126                     [fromInteger(valueOf(AxiExp1_slave_num))],
 127                     axiexp1.axi_slave); //
 128                 `endif
 129
 130     /*========== pinmux connections ============*/
 131 {7}
 132 {8}
 133     rule connect_i2c0_scl;
 134       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 135       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 136     endrule
 137     rule connect_i2c0_scl_in;
 138       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 139     endrule
 140     rule connect_i2c0_sda;
 141       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 142       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 143     endrule
 144     rule connect_i2c0_sda_in;
 145       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 146     endrule
 147     rule connect_uart1tx;
 148       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 149     endrule
 150     rule connect_uart1rx;
 151       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 152     endrule
 153     rule connect_gpioa;
 154       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 155       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 156       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 157       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 158       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 159       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 160                 Vector#(3,Bit#(1)) temp;
 161                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 162                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 163                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 164       gpioa.func.gpio_in(temp);
 165     endrule
 166     for(Integer i=0;i<32;i=i+ 1)begin
 167       rule connect_int_to_plic(wr_interrupt[i]==1);
 168                                 ff_gateway_queue[i].enq(1);
 169                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 170       endrule
 171     end
 172     rule rl_completion_msg_from_plic;
 173                   let id <- plic.intrpt_completion;
 174       interrupt_id <= id;
 175       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 176                 endrule
 177
 178     for(Integer i=0; i <32; i=i+1) begin
 179             rule deq_gateway_queue;
 180                     if(interrupt_id==fromInteger(i)) begin
 181                             ff_gateway_queue[i].deq;
 182           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 183         end
 184       endrule
 185     end
 186     /* for connectin inputs from pinmux as itnerrupts
 187       rule connect_pinmux_eint;
 188         wr_interrupt<= pinmux.peripheral_side.eint_input;
 189       endrule
 190     */
 191     // NEEL EDIT OVER
 192                 /*=======================================================*/
 193                 /*=================== PLIC Connections ==================== */
 194                 `ifdef PLIC_main
 195                         /*TODO DMA interrupt need to be connected to the plic
 196                         for(Integer i=1; i<8; i=i+1) begin
 197          `ifdef DMA
 198              rule rl_connect_dma_interrupts_to_plic;
 199                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 200                                                 ff_gateway_queue[i].enq(1);
 201                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 202                                         end
 203              endrule
 204           `else
 205              rule rl_connect_dma_interrupts_to_plic;
 206                  ff_gateway_queue[i].enq(0);
 207              endrule
 208           `endif
 209          end
 210                         */
 211          rule rl_connect_i2c0_to_plic;
 212                                 `ifdef I2C0
 213                                         if(i2c0.isint()==1'b1) begin
 214                                                 ff_gateway_queue[8].enq(1);
 215                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 216                                         end
 217                                 `else
 218                                         ff_gateway_queue[8].enq(0);
 219             `endif
 220          endrule
 221
 222                         rule rl_connect_i2c1_to_plic;
 223                                 `ifdef I2C1
 224                                         if(i2c1.isint()==1'b1) begin
 225                                                 ff_gateway_queue[9].enq(1);
 226                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 227                                         end
 228             `else
 229                                         ff_gateway_queue[9].enq(0);
 230             `endif
 231                         endrule
 232
 233          rule rl_connect_i2c0_timerint_to_plic;
 234                                 `ifdef I2C0
 235                                         if(i2c0.timerint()==1'b1) begin
 236                                                 ff_gateway_queue[10].enq(1);
 237                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 238                                         end
 239             `else
 240                                         ff_gateway_queue[10].enq(0);
 241             `endif
 242                         endrule
 243
 244          rule rl_connect_i2c1_timerint_to_plic;
 245                                 `ifdef I2C1
 246                                         if(i2c1.timerint()==1'b1) begin
 247                                                 ff_gateway_queue[11].enq(1);
 248                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 249                                         end
 250             `else
 251                                         ff_gateway_queue[11].enq(0);
 252             `endif
 253          endrule
 254
 255          rule rl_connect_i2c0_isber_to_plic;
 256                                 `ifdef I2C0
 257                                         if(i2c0.isber()==1'b1) begin
 258                                                 ff_gateway_queue[12].enq(1);
 259                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 260                                         end
 261             `else
 262                                         ff_gateway_queue[12].enq(0);
 263             `endif
 264          endrule
 265
 266          rule rl_connect_i2c1_isber_to_plic;
 267                                 `ifdef I2C1
 268                                         if(i2c1.isber()==1'b1) begin
 269                                                 ff_gateway_queue[13].enq(1);
 270                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 271                end
 272             `else
 273                                         ff_gateway_queue[13].enq(0);
 274             `endif
 275          endrule
 276
 277          for(Integer i = 14; i < 20; i=i+1) begin
 278                                 rule rl_connect_qspi0_to_plic;
 279                                         `ifdef QSPI0
 280                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 281                                                         ff_gateway_queue[i].enq(1);
 282                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 283                                                 end
 284                `else
 285                                                 ff_gateway_queue[i].enq(0);
 286                `endif
 287             endrule
 288          end
 289
 290          for(Integer i = 20; i<26; i=i+1) begin
 291                                 rule rl_connect_qspi1_to_plic;
 292                                         `ifdef QSPI1
 293                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 294                                                         ff_gateway_queue[i].enq(1);
 295                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 296                                                 end
 297                `else
 298                                                 ff_gateway_queue[i].enq(0);
 299                `endif
 300             endrule
 301                         end
 302
 303                         `ifdef UART0
 304                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 305                                 rule synchronize_the_uart0_interrupt;
 306                                         uart0_interrupt.send(uart0.irq);
 307                                 endrule
 308                         `endif
 309                         rule rl_connect_uart_to_plic;
 310                                 `ifdef UART0
 311                                         if(uart0_interrupt.read==1'b1) begin
 312                                                 ff_gateway_queue[27].enq(1);
 313                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 314                end
 315
 316             `else
 317                                         ff_gateway_queue[27].enq(0);
 318             `endif
 319          endrule
 320
 321                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 322                                 rule rl_raise_interrupts;
 323                                         if((i-28)<`IONum) begin //Peripheral interrupts
 324                                                 if(gpio.to_plic[i-28]==1'b1) begin
 325                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 326                                                                 ff_gateway_queue[i].enq(1);
 327                   end
 328                                         end
 329                                 endrule
 330                         end
 331
 332          rule rl_completion_msg_from_plic;
 333                                 let id <- plic.intrpt_completion;
 334             interrupt_id <= id;
 335             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 336                         endrule
 337
 338          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 339                                 rule deq_gateway_queue;
 340                                         if(interrupt_id==fromInteger(i)) begin
 341                                                 ff_gateway_queue[i].deq;
 342                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 343                end
 344             endrule
 345          end
 346
 347
 348                 `endif
 349                         /*======================================================= */
 350
 351                 /* ===== interface definition =======*/
 352                 interface axi_slave=bridge.axi_slave;
 353                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 354                 `ifdef CLINT
 355                         method msip_int=clint.msip_int;
 356                         method mtip_int=clint.mtip_int;
 357                         method mtime=clint.mtime;
 358                 `endif
 359                 `ifdef I2C0
 360                         method i2c0_isint=i2c0.isint;
 361                 `endif
 362                 `ifdef I2C1
 363                         method i2c1_isint=i2c1.isint;
 364                 `endif
 365                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 366                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 367                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 368                 interface SP_ios slow_ios;
 369                         `ifdef UART0
 370                                 interface uart0_coe=uart0.coe_rs232;
 371                         `endif
 372                         `ifdef UART1
 373                                 interface uart1_coe=uart1.coe_rs232;
 374                         `endif
 375                         `ifdef I2C0
 376                                 interface i2c0_out=i2c0.out;
 377                         `endif
 378                         `ifdef I2C1
 379                                 interface i2c1_out=i2c1.out;
 380                         `endif
 381                         `ifdef QSPI0
 382                                 interface qspi0_out = qspi0.out;
 383                         `endif
 384                         `ifdef QSPI1
 385                                 interface qspi1_out = qspi1.out;
 386                         `endif
 387                         `ifdef AXIEXP
 388                                 interface axiexp1_out=axiexp1.slave_out;
 389                                 interface axiexp1_in=axiexp1.slave_in;
 390                         `endif
 391       `ifdef PWM_AXI4Lite
 392         interface pwm_o = pwm_bus.pwm_io;
 393       `endif
 394                 endinterface
 395     // NEEL EDIT
 396     interface iocell_side=pinmux.iocell_side;
 397     interface pad_configa= gpioa.pad_config;
 398     method Action external_int(Bit#(32) in);
 399       wr_interrupt<= in;
 400     endmethod
 401     // NEEL EDIT OVER
 402                 /*===================================*/
 403         endmodule
 404 endpackage