src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         import slow_memory_map::*;
  11         `include "instance_defines.bsv"
  12     /* ==== define the number of slow peripheral irqs ==== */
  13 {11}
  14         /*===========================*/
  15         /*=== package imports ===*/
  16         import Clocks::*;
  17         import ifc_sync:: *;
  18         import GetPut::*;
  19         import ClientServer::*;
  20         import Connectable::*;
  21         import Vector::*;
  22         import FIFO::*;
  23         /*=======================*/
  24         /*===== Import the slow peripherals ====*/
  25 {0}
  26     `ifdef CLINT
  27         import clint::*;
  28     `endif
  29     `ifdef PLIC
  30         import plic             ::*;
  31     `endif
  32         `ifdef AXIEXP
  33                 import axiexpansion     ::*;
  34         `endif
  35         /*=====================================*/
  36
  37         /*===== interface declaration =====*/
  38         interface SP_dedicated_ios;
  39     interface IOCellSide iocell_side;
  40                 `ifdef AXIEXP
  41                         interface Get#(Bit#(67)) axiexp1_out;
  42                         interface Put#(Bit#(67)) axiexp1_in;
  43                 `endif
  44         endinterface
  45         interface Ifc_slow_peripherals;
  46                 interface AXI4_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
  47                 interface SP_dedicated_ios slow_ios;
  48                 `ifdef CLINT
  49                         method Bit#(1) msip_int;
  50                         method Bit#(1) mtip_int;
  51                         method Bit#(`DATA) mtime;
  52                 `endif
  53                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note;
  54         `endif
  55         interface IOCellSide iocell_side; // mandatory interface
  56         `ifdef PLIC
  57 {1}
  58         `endif
  59         endinterface
  60         /*================================*/
  61
  62         (*synthesize*)
  63         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  64                                Clock uart_clock, Reset uart_reset
  65                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  66                               )(Ifc_slow_peripherals);
  67                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  68                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  69
  70                 /*======= Module declarations for each peripheral =======*/
  71 {5}
  72                 `ifdef CLINT
  73                         Ifc_clint       clint <- mkclint();
  74                 `endif
  75                 `ifdef PLIC
  76                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  77             Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  78             Vector#(`INTERRUPT_PINS, FIFO#(bit))
  79                             ff_gateway_queue <- replicateM(mkFIFO);
  80                 `endif
  81                 `ifdef AXIEXP
  82                         Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
  83                 `endif
  84         Ifc_pinmux pinmux <- mkpinmux; // mandatory
  85 {14}
  86
  87                 /*=======================================================*/
  88
  89             AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `DATA,`USERSPACE)
  90                 slow_fabric <- mkAXI4_Lite_Fabric(fn_slow_address_mapping);
  91                 Ifc_AXI4Lite_AXI4_Bridge
  92                 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
  93
  94                 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
  95                 /*======= Slave connections to AXI4Lite fabric =========*/
  96 {6}
  97                 `ifdef CLINT
  98                         mkConnection (slow_fabric.v_to_slaves
  99                     [fromInteger(valueOf(CLINT_slave_num))],
 100                     clint.axi4_slave);
 101                 `endif
 102                 `ifdef PLIC
 103                         mkConnection (slow_fabric.v_to_slaves
 104                     [fromInteger(valueOf(Plic_slave_num))],
 105                     plic.axi4_slave_plic); //
 106                 `endif
 107                 `ifdef AXIEXP
 108                 mkConnection (slow_fabric.v_to_slaves
 109                     [fromInteger(valueOf(AxiExp1_slave_num))],
 110                     axiexp1.axi_slave); //
 111                 `endif
 112
 113     /*========== pinmux connections ============*/
 114 {7}
 115 {8}
 116
 117     /*=================== PLIC Connections ==================== */
 118 `ifdef PLIC
 119 {10}
 120
 121     rule rl_completion_msg_from_plic;
 122           let id <- plic.intrpt_completion;
 123       interrupt_id <= id;
 124       `ifdef verbose
 125         $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
 126        `endif
 127         endrule
 128
 129     for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 130             rule deq_gateway_queue;
 131                     if(interrupt_id==fromInteger(i)) begin
 132                             ff_gateway_queue[i].deq;
 133           `ifdef verbose
 134             $display($time,"Dequeing the Interrupt request for ID: %d",i);
 135           `endif
 136         end
 137       endrule
 138     end
 139     /*TODO DMA interrupt need to be connected to the plic */
 140     for(Integer i=1; i<8; i=i+1) begin
 141       rule rl_connect_dma_interrupts_to_plic;
 142        `ifdef DMA
 143             if(dma.interrupt_to_processor[i-1]==1'b1) begin
 144                 ff_gateway_queue[i].enq(1);
 145                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 146             end
 147         `else
 148             ff_gateway_queue[i].enq(0);
 149         `endif
 150       endrule
 151     end
 152
 153 `endif // end PLIC
 154         /*======================================================= */
 155
 156                 /* ===== interface definition =======*/
 157                 interface axi_slave=bridge.axi_slave;
 158                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 159                 `ifdef CLINT
 160                         method msip_int=clint.msip_int;
 161                         method mtip_int=clint.mtip_int;
 162                         method mtime=clint.mtime;
 163                 `endif
 164 `ifdef PLIC
 165 {12}
 166 `endif // end PLIC
 167                 interface SP_dedicated_ios slow_ios;
 168         /* template for dedicated peripherals
 169                         `ifdef UART0
 170                                 interface uart0_coe=uart0.coe_rs232;
 171                         `endif
 172                         `ifdef UART1
 173                                 interface uart1_coe=uart1.coe_rs232;
 174                         `endif
 175                         `ifdef I2C0
 176                                 interface i2c0_out=i2c0.out;
 177                         `endif
 178                         `ifdef I2C1
 179                                 interface i2c1_out=i2c1.out;
 180                         `endif
 181                         `ifdef QSPI0
 182                                 interface qspi0_out = qspi0.out;
 183                         `endif
 184                         `ifdef QSPI1
 185                                 interface qspi1_out = qspi1.out;
 186                         `endif
 187                         `ifdef AXIEXP
 188                                 interface axiexp1_out=axiexp1.slave_out;
 189                                 interface axiexp1_in=axiexp1.slave_in;
 190                         `endif
 191             `ifdef PWM_AXI4Lite
 192                 interface pwm_o = pwm_bus.pwm_io;
 193             `endif
 194        */
 195                 endinterface
 196         interface iocell_side=pinmux.iocell_side;
 197 {9}
 198 {13}
 199                 /*===================================*/
 200         endmodule
 201 endpackage