src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /* ==== define the number of slow peripheral irqs ==== */
  14 {11}
  15     /*====== AXI4 Lite slave declarations =======*/
  16
  17 {3}
  18         /*===========================*/
  19         /*=== package imports ===*/
  20         import Clocks::*;
  21         import GetPut::*;
  22         import ClientServer::*;
  23         import Connectable::*;
  24         import Vector::*;
  25         import FIFO::*;
  26         /*=======================*/
  27         /*===== Import the slow peripherals ====*/
  28 {0}
  29     `ifdef CLINT
  30         import clint::*;
  31     `endif
  32     `ifdef PLIC
  33         import plic             ::*;
  34     `endif
  35         `ifdef AXIEXP
  36                 import axiexpansion     ::*;
  37         `endif
  38         /*=====================================*/
  39
  40         /*===== interface declaration =====*/
  41         interface SP_dedicated_ios;
  42                 `ifdef AXIEXP
  43                         interface Get#(Bit#(67)) axiexp1_out;
  44                         interface Put#(Bit#(67)) axiexp1_in;
  45                 `endif
  46         endinterface
  47         interface Ifc_slow_peripherals;
  48                 interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
  49                 interface SP_dedicated_ios slow_ios;
  50                 `ifdef CLINT
  51                         method Bit#(1) msip_int;
  52                         method Bit#(1) mtip_int;
  53                         method Bit#(`DATA) mtime;
  54                 `endif
  55                 `ifdef PLIC method ActionValue#(SlowTuple2#(Bool,Bool)) intrpt_note;
  56         `endif
  57         interface IOCellSide iocell_side; // mandatory interface
  58         `ifdef PLIC
  59 {1}
  60         `endif
  61         endinterface
  62         /*================================*/
  63
  64         function SlowTuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  65                      fn_address_mapping (Bit#(`ADDR) addr);
  66         `ifdef CLINT
  67             if(addr>=`ClintBase && addr<=`ClintEnd)
  68                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  69             else
  70         `endif
  71         `ifdef PLIC
  72             if(addr>=`PLICBase && addr<=`PLICEnd)
  73                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  74             else
  75         `endif
  76         `ifdef AXIEXP
  77             if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  78                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  79             else
  80         `endif
  81 {4}
  82         return tuple2(False,?);
  83         endfunction
  84
  85         (*synthesize*)
  86         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  87                                Clock uart_clock, Reset uart_reset
  88                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  89                               )(Ifc_slow_peripherals);
  90                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  91                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  92
  93                 /*======= Module declarations for each peripheral =======*/
  94 {5}
  95                 `ifdef CLINT
  96                         Ifc_clint       clint <- mkclint();
  97                 `endif
  98                 `ifdef PLIC
  99                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
 100             Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 101             Vector#(`INTERRUPT_PINS, FIFO#(bit))
 102                             ff_gateway_queue <- replicateM(mkFIFO);
 103                 `endif
 104                 `ifdef AXIEXP
 105                         Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
 106                 `endif
 107         Ifc_pinmux pinmux <- mkpinmux; // mandatory
 108
 109                 /*=======================================================*/
 110
 111             AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
 112                 slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 113                 Ifc_AXI4Lite_AXI4_Bridge
 114                 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 115
 116                 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
 117                 /*======= Slave connections to AXI4Lite fabric =========*/
 118 {6}
 119                 `ifdef CLINT
 120                         mkConnection (slow_fabric.v_to_slaves
 121                     [fromInteger(valueOf(CLINT_slave_num))],
 122                     clint.axi4_slave);
 123                 `endif
 124                 `ifdef PLIC
 125                         mkConnection (slow_fabric.v_to_slaves
 126                     [fromInteger(valueOf(Plic_slave_num))],
 127                     plic.axi4_slave_plic); //
 128                 `endif
 129                 `ifdef AXIEXP
 130                 mkConnection (slow_fabric.v_to_slaves
 131                     [fromInteger(valueOf(AxiExp1_slave_num))],
 132                     axiexp1.axi_slave); //
 133                 `endif
 134
 135     /*========== pinmux connections ============*/
 136 {7}
 137 {8}
 138
 139     /*=================== PLIC Connections ==================== */
 140 `ifdef PLIC
 141 {10}
 142
 143     rule rl_completion_msg_from_plic;
 144           let id <- plic.intrpt_completion;
 145       interrupt_id <= id;
 146       `ifdef verbose
 147         $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
 148        `endif
 149         endrule
 150
 151     for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 152             rule deq_gateway_queue;
 153                     if(interrupt_id==fromInteger(i)) begin
 154                             ff_gateway_queue[i].deq;
 155           `ifdef verbose
 156             $display($time,"Dequeing the Interrupt request for ID: %d",i);
 157           `endif
 158         end
 159       endrule
 160     end
 161     /*TODO DMA interrupt need to be connected to the plic */
 162     for(Integer i=1; i<8; i=i+1) begin
 163       rule rl_connect_dma_interrupts_to_plic;
 164        `ifdef DMA
 165             if(dma.interrupt_to_processor[i-1]==1'b1) begin
 166                 ff_gateway_queue[i].enq(1);
 167                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 168             end
 169         `else
 170             ff_gateway_queue[i].enq(0);
 171         `endif
 172       endrule
 173     end
 174
 175 `endif // end PLIC
 176         /*======================================================= */
 177
 178                 /* ===== interface definition =======*/
 179                 interface axi_slave=bridge.axi_slave;
 180                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 181                 `ifdef CLINT
 182                         method msip_int=clint.msip_int;
 183                         method mtip_int=clint.mtip_int;
 184                         method mtime=clint.mtime;
 185                 `endif
 186 `ifdef PLIC
 187 {12}
 188 `endif // end PLIC
 189                 interface SP_dedicated_ios slow_ios;
 190         /* template for dedicated peripherals
 191                         `ifdef UART0
 192                                 interface uart0_coe=uart0.coe_rs232;
 193                         `endif
 194                         `ifdef UART1
 195                                 interface uart1_coe=uart1.coe_rs232;
 196                         `endif
 197                         `ifdef I2C0
 198                                 interface i2c0_out=i2c0.out;
 199                         `endif
 200                         `ifdef I2C1
 201                                 interface i2c1_out=i2c1.out;
 202                         `endif
 203                         `ifdef QSPI0
 204                                 interface qspi0_out = qspi0.out;
 205                         `endif
 206                         `ifdef QSPI1
 207                                 interface qspi1_out = qspi1.out;
 208                         `endif
 209                         `ifdef AXIEXP
 210                                 interface axiexp1_out=axiexp1.slave_out;
 211                                 interface axiexp1_in=axiexp1.slave_in;
 212                         `endif
 213             `ifdef PWM_AXI4Lite
 214                 interface pwm_o = pwm_bus.pwm_io;
 215             `endif
 216        */
 217                 endinterface
 218         interface iocell_side=pinmux.iocell_side;
 219 {9}
 220 {13}
 221                 /*===================================*/
 222         endmodule
 223 endpackage