src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /* ==== define the number of slow peripheral irqs ==== */
  14 {11}
  15     /*====== AXI4 Lite slave declarations =======*/
  16
  17 {3}
  18         /*===========================*/
  19         /*=== package imports ===*/
  20         import Clocks::*;
  21         import GetPut::*;
  22         import ClientServer::*;
  23         import Connectable::*;
  24         import Vector::*;
  25         import FIFO::*;
  26         /*=======================*/
  27         /*===== Import the slow peripherals ====*/
  28 {0}
  29     `ifdef CLINT
  30         import clint::*;
  31     `endif
  32     `ifdef PLIC
  33         import plic             ::*;
  34     `endif
  35         `ifdef AXIEXP
  36                 import axiexpansion     ::*;
  37         `endif
  38         `ifdef QSPI
  39                 import qspi                              :: *;
  40         `endif
  41         /*=====================================*/
  42
  43         /*===== interface declaration =====*/
  44         interface SP_dedicated_ios;
  45                 `ifdef AXIEXP
  46                         interface Get#(Bit#(67)) axiexp1_out;
  47                         interface Put#(Bit#(67)) axiexp1_in;
  48                 `endif
  49         endinterface
  50         interface Ifc_slow_peripherals;
  51                 interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
  52                 interface SP_dedicated_ios slow_ios;
  53                 `ifdef CLINT
  54                         method Bit#(1) msip_int;
  55                         method Bit#(1) mtip_int;
  56                         method Bit#(`DATA) mtime;
  57                 `endif
  58                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  59     interface IOCellSide iocell_side; // mandatory interface
  60 {1}
  61         endinterface
  62         /*================================*/
  63
  64         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  65                      fn_address_mapping (Bit#(`ADDR) addr);
  66                 `ifdef CLINT
  67                         if(addr>=`ClintBase && addr<=`ClintEnd)
  68                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  69                         else
  70                 `endif
  71                 `ifdef PLIC
  72                         if(addr>=`PLICBase && addr<=`PLICEnd)
  73                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  74                         else
  75                 `endif
  76                 `ifdef AXIEXP
  77                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  78                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  79                         else
  80                 `endif
  81 {4}
  82                         return tuple2(False,?);
  83         endfunction
  84
  85         (*synthesize*)
  86         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  87                                Clock uart_clock, Reset uart_reset
  88                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  89                               )(Ifc_slow_peripherals);
  90                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  91                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  92
  93                 /*======= Module declarations for each peripheral =======*/
  94 {5}
  95                 `ifdef CLINT
  96                         Ifc_clint                               clint                           <- mkclint();
  97                 `endif
  98                 `ifdef PLIC
  99                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
 100          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 101                           Vector#(`INTERRUPT_PINS, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
 102                 `endif
 103                 `ifdef AXIEXP
 104                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 105                 `endif
 106     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 107                 /*=======================================================*/
 108
 109         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
 110             slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 111                 Ifc_AXI4Lite_AXI4_Bridge
 112             bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 113
 114                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 115                 /*======= Slave connections to AXI4Lite fabric =========*/
 116 {6}
 117                 `ifdef CLINT
 118                         mkConnection (slow_fabric.v_to_slaves
 119                     [fromInteger(valueOf(CLINT_slave_num))],
 120                     clint.axi4_slave);
 121                 `endif
 122                 `ifdef PLIC
 123                         mkConnection (slow_fabric.v_to_slaves
 124                     [fromInteger(valueOf(Plic_slave_num))],
 125                     plic.axi4_slave_plic); //
 126                 `endif
 127                 `ifdef AXIEXP
 128                 mkConnection (slow_fabric.v_to_slaves
 129                     [fromInteger(valueOf(AxiExp1_slave_num))],
 130                     axiexp1.axi_slave); //
 131                 `endif
 132
 133     /*========== pinmux connections ============*/
 134 {7}
 135 {8}
 136     rule rl_completion_msg_from_plic;
 137                   let id <- plic.intrpt_completion;
 138       interrupt_id <= id;
 139       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 140                 endrule
 141
 142     for(Integer i=0; i <`NUM_INTERRUPTS; i=i+1) begin
 143             rule deq_gateway_queue;
 144                     if(interrupt_id==fromInteger(i)) begin
 145                             ff_gateway_queue[i].deq;
 146           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 147         end
 148       endrule
 149     end
 150     // NEEL EDIT OVER
 151                 /*=======================================================*/
 152                 /*=================== PLIC Connections ==================== */
 153                 `ifdef PLIC_main
 154                         /*TODO DMA interrupt need to be connected to the plic
 155                         for(Integer i=1; i<8; i=i+1) begin
 156          `ifdef DMA
 157              rule rl_connect_dma_interrupts_to_plic;
 158                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 159                                                 ff_gateway_queue[i].enq(1);
 160                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 161                                         end
 162              endrule
 163           `else
 164              rule rl_connect_dma_interrupts_to_plic;
 165                  ff_gateway_queue[i].enq(0);
 166              endrule
 167           `endif
 168          end
 169                         */
 170 {10}
 171          for(Integer i = 14; i < 20; i=i+1) begin
 172                                 rule rl_connect_qspi0_to_plic;
 173                                         `ifdef QSPI0
 174                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 175                                                         ff_gateway_queue[i].enq(1);
 176                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 177                                                 end
 178                `else
 179                                                 ff_gateway_queue[i].enq(0);
 180                `endif
 181             endrule
 182          end
 183
 184          for(Integer i = 20; i<26; i=i+1) begin
 185                                 rule rl_connect_qspi1_to_plic;
 186                                         `ifdef QSPI1
 187                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 188                                                         ff_gateway_queue[i].enq(1);
 189                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 190                                                 end
 191                `else
 192                                                 ff_gateway_queue[i].enq(0);
 193                `endif
 194             endrule
 195                         end
 196
 197                         `ifdef UART0
 198                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-
 199                                   mkSyncBitToCC(sp_clock, uart_reset);
 200                                 rule synchronize_the_uart0_interrupt;
 201                                         uart0_interrupt.send(uart0.irq);
 202                                 endrule
 203                         `endif
 204                         rule rl_connect_uart_to_plic;
 205                                 `ifdef UART0
 206                                         if(uart0_interrupt.read==1'b1) begin
 207                                                 ff_gateway_queue[27].enq(1);
 208                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 209                end
 210
 211             `else
 212                                         ff_gateway_queue[27].enq(0);
 213             `endif
 214          endrule
 215
 216                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 217                                 rule rl_raise_interrupts;
 218                                         if((i-28)<`IONum) begin //Peripheral interrupts
 219                                                 if(gpio.to_plic[i-28]==1'b1) begin
 220                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 221                                                                 ff_gateway_queue[i].enq(1);
 222                   end
 223                                         end
 224                                 endrule
 225                         end
 226
 227          rule rl_completion_msg_from_plic;
 228                                 let id <- plic.intrpt_completion;
 229             interrupt_id <= id;
 230             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 231                         endrule
 232
 233          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 234                                 rule deq_gateway_queue;
 235                                         if(interrupt_id==fromInteger(i)) begin
 236                                                 ff_gateway_queue[i].deq;
 237                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 238                end
 239             endrule
 240          end
 241
 242
 243                 `endif
 244                         /*======================================================= */
 245
 246                 /* ===== interface definition =======*/
 247                 interface axi_slave=bridge.axi_slave;
 248                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 249                 `ifdef CLINT
 250                         method msip_int=clint.msip_int;
 251                         method mtip_int=clint.mtip_int;
 252                         method mtime=clint.mtime;
 253                 `endif
 254                 `ifdef I2C0
 255                         method i2c0_isint=i2c0.isint;
 256                 `endif
 257                 `ifdef I2C1
 258                         method i2c1_isint=i2c1.isint;
 259                 `endif
 260                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 261                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 262                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 263                 interface SP_dedicated_ios slow_ios;
 264 /* template for dedicated peripherals
 265                         `ifdef UART0
 266                                 interface uart0_coe=uart0.coe_rs232;
 267                         `endif
 268                         `ifdef UART1
 269                                 interface uart1_coe=uart1.coe_rs232;
 270                         `endif
 271                         `ifdef I2C0
 272                                 interface i2c0_out=i2c0.out;
 273                         `endif
 274                         `ifdef I2C1
 275                                 interface i2c1_out=i2c1.out;
 276                         `endif
 277                         `ifdef QSPI0
 278                                 interface qspi0_out = qspi0.out;
 279                         `endif
 280                         `ifdef QSPI1
 281                                 interface qspi1_out = qspi1.out;
 282                         `endif
 283                         `ifdef AXIEXP
 284                                 interface axiexp1_out=axiexp1.slave_out;
 285                                 interface axiexp1_in=axiexp1.slave_in;
 286                         `endif
 287       `ifdef PWM_AXI4Lite
 288         interface pwm_o = pwm_bus.pwm_io;
 289       `endif
 290 */
 291                 endinterface
 292     // NEEL EDIT
 293     interface iocell_side=pinmux.iocell_side;
 294     interface pad_config0= gpioa.pad_config;
 295 {9}
 296     // NEEL EDIT OVER
 297                 /*===================================*/
 298         endmodule
 299 endpackage