src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package socgen;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41
  42     /*=== Project imports === */
  43     import ConcatReg::*;
  44     import AXI4_Types::*;
  45     import AXI4_Fabric::*;
  46     import defined_types::*;
  47     import MemoryMap             :: *;
  48     import slow_peripherals::*;
  49     import fast_memory_map::*;
  50     import slow_memory_map::*;
  51 `ifdef DEBUG
  52     `include "defines.bsv"
  53 `endif
  54     `include "instance_defines.bsv"
  55     `include "core_parameters.bsv"
  56 {8}
  57
  58     `ifdef DMA
  59         import DMA                               :: *;
  60     `endif
  61     `ifdef BOOTROM
  62         import BootRom                  ::*;
  63     `endif
  64     `ifdef SDRAM
  65         import sdr_top                   :: *;
  66     `endif
  67     `ifdef BRAM
  68         import Memory_AXI4      ::*;
  69     `endif
  70     `ifdef TCMemory
  71         import TCM::*;
  72     `endif
  73     `ifdef Debug
  74         import DebugModule::*;
  75     `else
  76         import core::*;
  77     `endif
  78     `ifdef  VME
  79         import vme_top ::*;
  80     `endif
  81
  82     `ifdef VME
  83         import vme_master::*;
  84     `endif
  85     `ifdef FlexBus
  86         import FlexBus_Types::*;
  87     `endif
  88 {0}
  89
  90     /*========================= */
  91     interface Ifc_Soc;
  92         interface SP_dedicated_ios slow_ios;
  93         (*always_ready,always_enabled*)
  94         method Action boot_sequence(Bit#(1) bootseq);
  95
  96         `ifdef SDRAM
  97             (*always_ready*) interface Ifc_sdram_out sdram_out;
  98         `endif
  99         `ifdef DDR
 100             (*prefix="M_AXI"*) interface
 101                    AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
 102         `endif
 103         `ifdef HYPER
 104              (*always_ready,always_enabled*)
 105              interface Ifc_flash ifc_flash;
 106         `endif
 107         /*=============================================== */
 108         `ifdef VME
 109              interface Vme_out  proc_ifc;
 110              interface Data_bus_inf proc_dbus;
 111         `endif
 112 {1}
 113     endinterface
 114
 115     //============ mkSoc module =================
 116
 117     (*synthesize*)
 118     module mkSoc #(Bit#(`VADDR) reset_vector,
 119                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 120                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 121                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 122         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 123         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 124 {2}
 125         `ifdef Debug
 126             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 127         `else
 128             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 129         `endif
 130         `ifdef BOOTROM
 131             BootRom_IFC bootrom <-mkBootRom;
 132         `endif
 133         `ifdef SDRAM
 134             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 135         `endif
 136         `ifdef BRAM
 137             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 138                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 139         `endif
 140         `ifdef TCMemory
 141             Ifc_TCM                                     tcm                             <- mkTCM;
 142         `endif
 143         `ifdef DMA
 144             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 145         `endif
 146             `ifdef VME
 147             Ifc_vme_top             vme             <-mkvme_top();
 148             `endif
 149         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 150                           core_clock, core_reset,
 151                           uart_clock, uart_reset,
 152                           clocked_by slow_clock, reset_by slow_reset
 153                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 154
 155         // clock sync mkConnections
 156 {12}
 157
 158         // Fabric
 159         AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
 160                           `PADDR, `DATA,`USERSPACE)
 161                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 162
 163         // Connect traffic generators to fabric
 164         mkConnection (core.dmem_master,fabric.v_from_masters
 165                               [fromInteger(valueOf(Dmem_master_num))]);
 166         mkConnection (core.imem_master, fabric.v_from_masters
 167                               [fromInteger(valueOf(Imem_master_num))]);
 168         `ifdef Debug
 169             mkConnection (core.debug_master, fabric.v_from_masters
 170                               [fromInteger(valueOf(Debug_master_num))]);
 171         `endif
 172         `ifdef DMA
 173          mkConnection (dma.mmu, fabric.v_from_masters
 174                               [fromInteger(valueOf(DMA_master_num))]);
 175         `endif
 176
 177
 178         // Connect fabric to memory slaves
 179             `ifdef Debug
 180                 mkConnection (fabric.v_to_slaves
 181                               [fromInteger(valueOf(Debug_slave_num))],
 182                               core.debug_slave);
 183             `endif
 184             `ifdef SDRAM
 185                 mkConnection (fabric.v_to_slaves
 186                               [fromInteger(valueOf(Sdram_slave_num))],
 187                               sdram.axi4_slave_sdram); //
 188             mkConnection (fabric.v_to_slaves
 189                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 190                               sdram.axi4_slave_cntrl_reg); //
 191       `endif
 192       `ifdef BRAM
 193                 mkConnection(fabric.v_to_slaves
 194                               [fromInteger(valueOf(Sdram_slave_num))],
 195                               main_memory.axi_slave);
 196             `endif
 197             `ifdef BOOTROM
 198                 mkConnection (fabric.v_to_slaves
 199                               [fromInteger(valueOf(BootRom_slave_num))],
 200                               bootrom.axi_slave);
 201             `endif
 202             `ifdef DMA
 203             mkConnection (fabric.v_to_slaves
 204                               [fromInteger(valueOf(Dma_slave_num))],
 205                               dma.cfg); //DMA slave
 206             `endif
 207             `ifdef TCMemory
 208                 mkConnection (fabric.v_to_slaves
 209                               [fromInteger(valueOf(TCM_slave_num))],
 210                               tcm.axi_slave);
 211             `endif
 212             mkConnection(fabric.v_to_slaves
 213                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 214                               slow_peripherals.axi_slave);
 215             `ifdef VME
 216                 mkConnection (fabric.v_to_slaves
 217                               [fromInteger(valueOf(VME_slave_num))],
 218                               vme.slave_axi_vme);
 219             `endif
 220
 221 //          pin connections
 222 {9}
 223
 224             // fabric connections
 225 {5}
 226
 227             `ifdef DMA
 228             // rule to connect all interrupt lines to the DMA
 229             // All the interrupt lines to DMA are active
 230             // HIGH. For peripherals that are not connected,
 231             // or those which do not
 232             // generate an interrupt (like TCM), drive a constant 1
 233             // on the corresponding interrupt line.
 234 {7}
 235             `endif
 236
 237
 238         /*==== Synchornization between the JTAG and the Debug Module ===== */
 239         `ifdef Debug
 240             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 241                                         mkSyncFIFOToCC(1,tck,trst);
 242             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 243                                         mkSyncFIFOFromCC(1,tck);
 244             rule connect_tap_request_to_syncfifo;
 245                 let x<-tap.request_to_dm;
 246                 sync_request_to_dm.enq(x);
 247             endrule
 248             rule read_synced_request_to_dm;
 249                 sync_request_to_dm.deq;
 250                 core.request_from_dtm(sync_request_to_dm.first);
 251             endrule
 252
 253             rule connect_debug_response_to_syncfifo;
 254                 let x<-core.response_to_dtm;
 255                 sync_response_from_dm.enq(x);
 256             endrule
 257             rule read_synced_response_from_dm;
 258                 sync_response_from_dm.deq;
 259                 tap.response_from_dm(sync_response_from_dm.first);
 260             endrule
 261         `endif
 262         /*============================================================ */
 263
 264         `ifdef FlexBus
 265             //rule drive_flexbus_inputs;
 266                //flexbus.flexbus_side.m_TAn(1'b1);
 267                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 268             //endrule
 269          `endif
 270
 271         `ifdef CLINT
 272             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 273                                         mkSyncBitToCC(slow_clock,slow_reset);
 274             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 275                                         mkSyncBitToCC(slow_clock,slow_reset);
 276             Reg#(Bit#(`DATA)) clint_mtime_value <-
 277                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 278             rule synchronize_clint_data;
 279                 clint_mtip_int.send(slow_peripherals.mtip_int);
 280                 clint_msip_int.send(slow_peripherals.msip_int);
 281                 clint_mtime_value<=slow_peripherals.mtime;
 282             endrule
 283             rule connect_msip_mtip_from_clint;
 284                 core.clint_msip(clint_msip_int.read);
 285                 core.clint_mtip(clint_mtip_int.read);
 286             core.clint_mtime(clint_mtime_value);
 287             endrule
 288         `endif
 289         `ifdef PLIC
 290             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 291                                         mkSyncRegToCC(tuple2(False,False),
 292                                                       slow_clock,slow_reset);
 293             rule synchronize_interrupts;
 294                 let note <- slow_peripherals.intrpt_note;
 295                 plic_interrupt_note<=note;
 296             endrule
 297             rule rl_send_external_interrupt_to_csr;
 298                 core.set_external_interrupt(plic_interrupt_note);
 299             endrule
 300         `endif
 301
 302         `ifdef VME
 303             interface  proc_ifc = vme.proc_ifc;
 304             interface   proc_dbus = vme.proc_dbus;
 305         `endif
 306          method Action boot_sequence(Bit#(1) bootseq) =
 307                             core.boot_sequence(bootseq);
 308         `ifdef SDRAM
 309             interface sdram_out=sdram.ifc_sdram_out;
 310         `endif
 311         `ifdef DDR
 312           interface master=fabric.v_to_slaves
 313                                 [fromInteger(valueOf(Sdram_slave_num))];
 314         `endif
 315         interface slow_ios=slow_peripherals.slow_ios;
 316 {6}
 317     endmodule
 318 endpackage