2 Copyright (c) 2013, IIT Madras
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14 * Neither the name of IIT Madras nor the names of its contributors
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16 without specific prior written permission.
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------
32 /*====== Package imports === */
35 import SpecialFIFOs::*;
37 import ClientServer::*;
39 import Connectable::*;
42 /*=== Project imports === */
46 import AXI4_Fabric::*;
47 import defined_types::*;
48 import MemoryMap :: *;
49 import slow_peripherals::*;
50 import fast_memory_map::*;
51 import slow_memory_map::*;
53 `include "defines.bsv"
55 `include "instance_defines.bsv"
56 `include "core_parameters.bsv"
69 import Memory_AXI4 ::*;
75 import DebugModule::*;
87 import FlexBus_Types::*;
91 /*========================= */
93 interface SP_dedicated_ios slow_ios;
94 interface IOCellSide iocell_side;
95 (*always_ready,always_enabled*)
96 method Action boot_sequence(Bit#(1) bootseq);
99 (*always_ready*) interface Ifc_sdram_out sdram_out;
102 (*prefix="M_AXI"*) interface
103 AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
106 (*always_ready,always_enabled*)
107 interface Ifc_flash ifc_flash;
109 /*=============================================== */
111 interface Vme_out proc_ifc;
112 interface Data_bus_inf proc_dbus;
117 //============ mkSoc module =================
120 module mkSoc #(Bit#(`VADDR) reset_vector,
121 Clock slow_clock, Reset slow_reset, Clock uart_clock,
122 Reset uart_reset, Clock clk0, Clock tck, Reset trst
123 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
124 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
125 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
128 Ifc_DebugModule core<-mkDebugModule(reset_vector);
130 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
133 BootRom_IFC bootrom <-mkBootRom;
136 Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
139 Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
140 mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
143 Ifc_TCM tcm <- mkTCM;
146 DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
149 Ifc_vme_top vme <-mkvme_top();
151 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
152 core_clock, core_reset,
153 uart_clock, uart_reset,
154 clocked_by slow_clock, reset_by slow_reset
155 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
157 // clock sync mkConnections
161 AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
162 `PADDR, `DATA,`USERSPACE)
163 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
165 // Connect traffic generators to fabric
166 mkConnection (core.dmem_master,fabric.v_from_masters
167 [fromInteger(valueOf(Dmem_master_num))]);
168 mkConnection (core.imem_master, fabric.v_from_masters
169 [fromInteger(valueOf(Imem_master_num))]);
171 mkConnection (core.debug_master, fabric.v_from_masters
172 [fromInteger(valueOf(Debug_master_num))]);
175 mkConnection (dma.mmu, fabric.v_from_masters
176 [fromInteger(valueOf(DMA_master_num))]);
180 // Connect fabric to memory slaves
182 mkConnection (fabric.v_to_slaves
183 [fromInteger(valueOf(Debug_slave_num))],
187 mkConnection (fabric.v_to_slaves
188 [fromInteger(valueOf(Sdram_slave_num))],
189 sdram.axi4_slave_sdram); //
190 mkConnection (fabric.v_to_slaves
191 [fromInteger(valueOf(Sdram_cfg_slave_num))],
192 sdram.axi4_slave_cntrl_reg); //
195 mkConnection(fabric.v_to_slaves
196 [fromInteger(valueOf(Sdram_slave_num))],
197 main_memory.axi_slave);
200 mkConnection (fabric.v_to_slaves
201 [fromInteger(valueOf(BootRom_slave_num))],
205 mkConnection (fabric.v_to_slaves
206 [fromInteger(valueOf(Dma_slave_num))],
207 dma.cfg); //DMA slave
210 mkConnection (fabric.v_to_slaves
211 [fromInteger(valueOf(TCM_slave_num))],
214 mkConnection(fabric.v_to_slaves
215 [fromInteger(valueOf(SlowPeripheral_slave_num))],
216 slow_peripherals.axi_slave);
218 mkConnection (fabric.v_to_slaves
219 [fromInteger(valueOf(VME_slave_num))],
226 // fabric connections
230 // rule to connect all interrupt lines to the DMA
231 // All the interrupt lines to DMA are active
232 // HIGH. For peripherals that are not connected,
233 // or those which do not
234 // generate an interrupt (like TCM), drive a constant 1
235 // on the corresponding interrupt line.
240 /*==== Synchornization between the JTAG and the Debug Module ===== */
242 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
243 mkSyncFIFOToCC(1,tck,trst);
244 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
245 mkSyncFIFOFromCC(1,tck);
246 rule connect_tap_request_to_syncfifo;
247 let x<-tap.request_to_dm;
248 sync_request_to_dm.enq(x);
250 rule read_synced_request_to_dm;
251 sync_request_to_dm.deq;
252 core.request_from_dtm(sync_request_to_dm.first);
255 rule connect_debug_response_to_syncfifo;
256 let x<-core.response_to_dtm;
257 sync_response_from_dm.enq(x);
259 rule read_synced_response_from_dm;
260 sync_response_from_dm.deq;
261 tap.response_from_dm(sync_response_from_dm.first);
264 /*============================================================ */
267 //rule drive_flexbus_inputs;
268 //flexbus.flexbus_side.m_TAn(1'b1);
269 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
274 SyncBitIfc#(Bit#(1)) clint_mtip_int <-
275 mkSyncBitToCC(slow_clock,slow_reset);
276 SyncBitIfc#(Bit#(1)) clint_msip_int <-
277 mkSyncBitToCC(slow_clock,slow_reset);
278 Reg#(Bit#(`DATA)) clint_mtime_value <-
279 mkSyncRegToCC(0,slow_clock,slow_reset);
280 rule synchronize_clint_data;
281 clint_mtip_int.send(slow_peripherals.mtip_int);
282 clint_msip_int.send(slow_peripherals.msip_int);
283 clint_mtime_value<=slow_peripherals.mtime;
285 rule connect_msip_mtip_from_clint;
286 core.clint_msip(clint_msip_int.read);
287 core.clint_mtip(clint_mtip_int.read);
288 core.clint_mtime(clint_mtime_value);
292 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
293 mkSyncRegToCC(tuple2(False,False),
294 slow_clock,slow_reset);
295 rule synchronize_interrupts;
296 let note <- slow_peripherals.intrpt_note;
297 plic_interrupt_note<=note;
299 rule rl_send_external_interrupt_to_csr;
300 core.set_external_interrupt(plic_interrupt_note);
305 interface proc_ifc = vme.proc_ifc;
306 interface proc_dbus = vme.proc_dbus;
308 method Action boot_sequence(Bit#(1) bootseq) =
309 core.boot_sequence(bootseq);
311 interface sdram_out=sdram.ifc_sdram_out;
314 interface master=fabric.v_to_slaves
315 [fromInteger(valueOf(Sdram_slave_num))];
317 interface slow_ios = slow_peripherals.slow_ios;
318 interface iocell_side = slow_peripherals.iocell_side;